SU1272333A1 - Multimicroprogram control device with checking - Google Patents

Abstract

The invention relates to the field of automation and digital computing and can be used in the design of multi-microprogramming systems for monitoring and controlling complex identical objects. The purpose of the invention is to reduce the warming of just objects of control, the realization of the mode of selective locks. The multi-microprogram control device with control contains a microprogram memory block, address registers, N registers of logic conditions code, microinstruction register, mask register, mask copy register, clock generator, counter, first control trigger, second control trigger, operation end register, code multiplexer logical conditions, first and second logical conditions multiplexers, address multiplexer, first and second blocking signal multiplexers, demultiplexer, decoder, N switches, w There are groups of elements AND, (About three groups of elements OR, five elements (List I, third control trigger, three elements OR, element AND-NOT, mask switch. The goal is achieved with the help of the specified combination of features. 2 Il. IsD CO WITH

Description

The invention relates to automation and digital computing and can be used in the design of multi-microprogramming systems for monitoring and controlling complex identical objects. The aim of the invention is to reduce the time of just the objects of control, the implementation of the selective lock mode. FIG. 1 to 3 are functional diagrams of a multi-microprogrammed control device with a control in FIG. 2-6 - timing charts of the device. A multi-microprogrammed control unit with a control (Fig. 1) contains a microprogram memory block 1, N registers 2.1-2.N addresses, N registers 3.1-3.N code of logical conditions, register 4 microcommands with 4.1 outputs for the end of operation, 4 .Z - sign of the end of the work, 4.3 address floor, 4.4 - micro-operation floor, 4.5 - logic field, mask register 5 register mask copy 6, clock generator 7, counter 8, first control trigger 9, second control trigger 10, register 11 end of operation, multiplexer 12 codes of logical conditions, the first multiplex 13, the logical conditions, the second multiplexer 14 logical conditions. address multiplexer 15, first mule typelexer 16 blocking signals, second multiplexer 17 blocking signals, demultiplexer 18, decoder 19, N switches 20f - 20d switch 21 masks, groups of elements AND 22-27, second and third groups of elements OR. 28 and 29, elements AND 30-34, third trigger 35, control elements OR 36-38, element AND-NOT 39, inputs 40.1-40.N of the command codes of the device, input 41 of starting the device, inputs 42.1-42.N of logical signals conditions of the device, the first - the fourth outputs 43-46 of the clock generator 7, the outputs 47.1-47.N of the decoder 19, the outputs 48.1-48.N the mask code field of the microprogram memory 1, microprograms, 49 output of the end of blocking of the micro memory 1 block programs, output 50 of the indication of blocking permission of the microprogram memory block 1, outputs 51.1-51.N of the device micro-operations, the first group of elements AND LI 52. The proposed multimicroprocessor control device functions in the following modes: realizing control of N objects in the absence of busy signals from objects of control (mode 1); implementation of the control of N objects in the presence of signals that control objects are busy (mode 2); selective locks (mode 3). The initial state registers 5, 6, 11, the triggers 9, 10, 35 and the device counter B are in the zero state. In the 4.1 field of the register 4 the unit is written (the setup circuits are not shown in the initial state). Operation of the device begins with a signal. Start-up to input 41. Non-zero command codes are received at the corresponding inputs 40.1-40.N of the device. In this case, the signals from the outputs of the SHW elements of the group 28 corresponding to the operating objects pass through the group of the elements AND 26 and set the corresponding triggers of the register 11 to one state. In this case, a single signal appears at the output of the NAND 39 element, which includes a generator of 7 clock pulses. The signal from the input 41 of the device goes through the OR 52 elements of the first group to the synchronization inputs of the 2.1-2.N registers of the addresses and writes into these registers the command codes (initial addresses of the microprograms) coming from the outputs of the switches 20.1-20.N. Address codes from registers 2.1-2.N are sent to the information inputs of multiplexer 15. The control input of multiplexer 15 receives a control signal (the number of the first control object, counter 8 is in the zero state), allowing the opcode from register 1 to pass through multiplexer 15 to the input of memory block 1. In this case, the first microinstruction (MK1-1) for the first control object is read from the memory unit 1 and is fed to the information input of the 4 microinstruction register. Consider the features of the operation of the device modes. Sharp 1. When the output of the generator 7 of the pulse of the first phase (pulse T1) appears in the register 4, the microcommands, MK1-1. The pulse T1 passes through the element And 30 to the input of the synchronization register 4 and

on the falling edge, writes the code MK1-1. At the same time, at output 4.1 of register 4, a zero signal appears allowing the recording of the address of the second microcommand for the first control object MK1-2 from output 4.3 of register 4 to register 2.1 and the code checked after its logical condition from output 4.5 of register 4 in the register 3.1. Micro-operation signals for the first control object from output 4.4; the register 4 is fed through the demultiplexer 18 to the outputs of the micro-operations 51.1 (the control input of the demultiplexer from the counter 8 receives the address of the first control object).

The second clock pulse from the output 44 of the generator 7 (pulse T2) passes through the element 22 22 of the group 22 And 3.1 of the group 22 And 3.1 that are opened by the signals 4.1 from the output 4.1 of the register 4 and the output 47.1 from the decoder 19. On the leading edge of the pulse T2, the address code of the next microcommand and the logic condition code checked after its execution are written into these registers. When a third clock pulse (pulse TZ) appears at generator 45 output 7, the device is prepared for servicing the next (second) control object: register 4 is set to the zero state, and the contents of counter 8 are incremented by one (Fig. 2). The management of work from the second to the dth control objects will be carried out similarly to the described algorithm. The BN + 1 device operation cycle will control the first control object. In this case, counter 8 will be in the zero state. The counter 8 is reset to the zero state by the overflow signal, which is the internal signal of the counter 8. Therefore, in the operation cycle of the device N + 1, 2N + 1, 3N + 1, etc. In register 4, the micro-command MK1-2, MK1-3, MK1-4, etc. will be recorded. (Fig. 2). The addresses of microinstructions in the device are formed as follows. The upper bits of the address from the output of the multiplexer 15 are directly fed to the input of memory block 1, and the low bit of the address from the output of multiplexer 15 is fed to the input of the lower bit of the address of memory block 1 through the OR 36 element. With the help of the OR 36 element, the the least significant bit of the address is the value of the checked logical condition coming from the output of the multiplexer 13 (if the value of the checked logical condition is zero, the value of the low order bit of the address is preserved, and when it is 1, it is replaced by the value of logical of conditions).

When issuing to the register of the last 4 microcommand of the current microprogram of operation of the i-ro control object (i 1, N) at output 4.1, a single signal value is displayed. End of operation. This signal will allow the passage of the next operation code to register 2.1 from input 40.1.

Claims (2)

The end of the device is as follows. When writing to the register 4 of the last microinstruction for the i-th control object, a single signal appears at output 4.2. End of operation. This signal passes through an AND 25.1 element of the AND 25 group of elements, opening the second input with a signal from the output 47.1 of the decoder 19 to the input of setting the trigger 11.1 of register 11 to zero and sets it to the zero state. When all the triggers of the register 11 are set to the zero state (which corresponds to the termination of work by all control objects), the signal disappears at the output of the NAND element 39. When this generator 7 is turned off and the operation of the device is terminated. Mode 2. The operation of the device in this mode differs from that considered in that if the 1st control object is occupied (the object did not have time to finish the work according to the previous micro-command), the next micro-command is recorded in the 4 micro-commands register, and the next micro-command addresses in the 2.1 and the code being checked after its execution of a logical condition in the register. 3.1 should not occur. That is, the control unit must skip the control cycles of the 1st object until it executes the micro-command, and after its execution make the next micro-command. Thus, an arbitrary time must be stored in the device with information about the next micro-command (its address and the code being checked after its logical condition is met). Consider the algorithm of the functioning of the device under the assumption that when issuing the next microcommand to the second control object, the latter was busy (i.e., the second object had not yet completed the previous microcommand). At the same time, at the input 42.2 of the signals of the occupation of the inputs of the logic terminals of the device 42.1-42, N there is a single signal. When the device goes to the service of the second object, the contents of the counter 8 will become equal to one (cT8j 1). At the same time, the signal of the second object's occupancy from the device input 42.2 through the multiplexer 16 is fed to the control input of the trigger 35. When the fourth phase clock pulse (pulse. T4, FIG. 2) arrives, the trigger 35 goes to the unit state and outputs a busy signal through element OR 38 to element 30. At the same time, the transmission of pulse T1 to the synchronization input of register 4 and the pulse T2 to the synchronization input of registers 2.2 and 3.2 is prohibited. In this case, it will be prohibited to write the next microcommand to the register 4 and the addresses of the next microcommand and the logical condition checked after its fulfillment in the registers 2.2 and 3.2, respectively. Thus, in the current cycle at the output 51.2 of the device, micro-operations signals are not received and are not detected at the second control object. The clock pulse TZ contents counter 8 is increased by unit st8 2 and the device will go to control the work of the third object. After the microcommand completes the second object, the busy signal at input 42.2 disappears, with the subsequent control of the second object, the trigger 35 does not go into one state and the device operates in the same way as the mode 1 operation, Mode 3. In this mode, it is possible to block several control objects with one control object. The proposed device starts functioning in this mode if, when the next microcommand from memory 1 is read, at the outputs 48.1-48.N of the mask code of the objects to be blocked, a nonzero one (mask) lock appears (each code bit corresponds to the number of the control object being blocked ). The blocking mask from memory block 1 will then go to the installation inputs of the corresponding register 5 triggers, and through the block of elements 23 to the inputs of the installation into register triggers 6, assume that the i-th control object will block the jth and kth objects. Then, when reading the micro-blocking commands, the triggers 5.j, 5,, k and 6, j, 6.k go into one state, Ka is noted, the device should only block the j-ro and k-ro of control objects only when they perform sections firmware where locking is possible. Consider the operation of the device in mode 3 in the above example. After the mask has been written to registers 5 and 6, a single signal appears at the output of switch 21. At the same time at the output of the element And 31 there is a single signal. When the pulse T1 arrives, the trigger 9 goes into one state and the code of the next micro-command for the i-th object is controlled. neither is register 4 registered. The address of the next microcommand in register 2.1 and the code of the checked logical condition in register 3.1 remain the same. When a pulse of TZ arrives, the contents of counter 8 increase by one and the device proceeds to control the operation of the (i + 1) -ro object. Further, the device functions similarly to operation in mode 2. If the jth (kth) control object cannot be blocked, then when reading a microcommand to control the Jth (kth) object at output 50 of memory 1, the signal is absent and the device is functioning similar to the described algorithm. If the j-ro (k-ro) object lock is possible, then a single signal appears at the output 50 of the memory block 1. The element And 24.j (24.k) of the group of elements And 24, opened on the second input by a signal from the output 47.j (47.k) of the decoder 19, outputs to the input of the setting to zero the trigger 6.j (6.k a) single signal and sets it to the zero state. If all blocked objects execute firmware sections where locking is possible, then the 6.J and 6.k triggers of register 6 are set to the zero state. When the microcontrol of the J-M control command is recalled, the object at the output of the OR 37 element is a single signal. Since there is no signal at the output of switch 21 (register 6 is in the zero state), the output of element 31 will be a zero signal. When the pulse T1 arrives in register 4, a micro-command will be recorded to control the J-M object and the trigger 10 will be set to one. When the pulses of T2 and TZ are received, the device will function similarly to the algorithm described. Blocking the work of j-ro (k-ro) objects is as follows. In the transition to control of the device JM (k-m) by an object, a single signal from the output of the trigger 5.j (5.k) through multiplexer 17 and the element AND 34 enters the element OR 38 and prohibits the issuance of the next microcommand for j-ro (k-ro ) object in register 4. After the i-th control object of the firmware section is executed, c. In the lockdown mode of the j-ro and k-r control objects, the device operation mode 3 is terminated. The end of mode 3 is as follows. When the next microcommand is formed, the i-th control object at the output 49 of the memory unit 1 appears a single signal. In this case, register 6, triggers 9 and 10 are set to the zero state. The time diagram of the device operation is shown in FIG. 2. In cycle 1, object 1 is controlled. In cycle 2, object 2 is controlled. In cycle 3, the MC1-2 is not outputted to object 1, since an occupancy signal is received at input 42.1 of the device. In loop 4, object 2 executes micro-command MK2-2. In loop 5, a micro-command for blocking is issued by the first object of the second object. In cycle 6, microcontrol MK2-3 is output to object 2. At that, the blocking enable signal at the output 50 of the memory block 1 is absent. In cycle 7, the micro-command MK1-2 is not assigned to object 1. In cycle 8, microcontrol MK2-4 is issued to object 2 and blocking of object 2 is allowed. In cycle 9 on the object 1 micro-command MK1-2. In cycle 10, the micro-command MK2-5 does not appear on the object, since object 2 is blocked. In cycle 11, object 1 is issued micro-command MK1-3 and the object is locked 2. In cycle 12, the micro-command MK2-5 is issued to the object. Multi-microprogrammed control device with control, containing a microprogram memory block, N address registers, microinstruction register, N address switches, N logic condition code registers, address multiplexer, two logic condition multiplexer, logical condition code multiplexer, first lock multiplexer, a demultiplexer, three control triggers, a counter, a work end register, consisting of N triggers, a clock generator, a decoder, the first group of elements OR, The first element OR, five elements AND, the element NAND, and the device start input is connected to the first inputs of the elements OR of the first group, the output of the sign of the end of the micro-command register operation is connected to the control inputs from the first to the N-th address switch, the outputs of which are connected with the information inputs from the first to the N-th address register, respectively, the outputs from the first to the N-th address register are connected to the first to the N-th information input of the address multiplexer, the output of the low-order address of the address multiplexer is connected to the first the input of the first OR element, the output of which is connected to the lower-order information input of the microprogram memory block, the output of the higher-order address bits of the multiplexer of the address is connected to the information input of the higher-order bits of the microprogram memory block, the output of the microinstruction of its microcommands is connected to the register information input microinstructions, the output of the field of microoperations of which is connected to the information input of the demultiplexer, the inputs of the device command codes are connected to the second information inputs from the first through N- address switches, the output of the field of logical conditions of the register of microoperations is connected with in-. formation inputs from the first to the Nth logical condition registers, the outputs of which are connected from the first to the Nth informational inputs of the multiplexer of the logic conditions code, the output of which is connected to the control input of the first multiplexer and logical conditions, the output of which is connected to the second input of the first element OR, the first output of the clock pulse generator is connected to the first input of the first element AND, the counter output is connected to the input of the decoder, the control input of the first multiplexer of the interlock signals, the control the multiplexer path of the logic conditions code, the control input of the second multiplexer of the logic conditions and the control input of the demultiplexer, whose outputs are the outputs of the device microoperation for the first n Nth control objects, the inputs of the signals of the logical conditions of the device and the inputs of the device lock signals are respectively connected to the information the inputs of the second multiplexer of logical conditions and with the information inputs of the first mule of the blocking type multiplexer, so that, in order to reduce time just objects of management. implementations of the selective blocking mode, a mask register and a mask copy register consisting of N triggers each, the second blocking signal multiplexer, the mask switch, six AND groups, the second and third OR groups, the second and third OR elements, and the outputs of the mask storage unit field of the microprogram are connected to the first inputs of elements AND of the second group, with the installation inputs to 1 from the first to the Nth trigger register of the mask register and the inputs to the second element OR, the output of which is connected to the first inputs of the second, third and h And the fourth element, the output of the recognition of blocking the memory block of the microprogram, is connected to the first inputs of the AND elements of the third group,. the outputs of which are connected to the installation inputs in O from the first to the Nth trigger register of the mask copy, the outputs of which are connected to the control inputs of the mask switch, the outputs of the mask register are connected to the information inputs of the mask switch, the output of which is connected to the second inputs of the second and third elements And, the output of the second element AND is connected to the first input of the third element OR, the output of which is connected to the third inputs of the elements AND of the first group and to the second input of the first element AND, the output of which is connected to the synchronization input register of micro-commands, the first output of the clock generator is connected to the third input of the third element I and the second input of the fourth element I, the output of which is connected to the installation input of 1 of the first control trigger, the inverted output of which is connected to the second inputs of the elements of the second group, outputs which are connected to the inputs of the installation in 1 from the first to the N-th triggers of the mask copy register, the outputs of the mask register are connected to the information inputs of the second lockout multiplexer, the output of which is connected to the The second input of the And element, the output of the third element And is connected to the installation input 1 of the second control trigger, the output of which is connected to the second input of the fifth element AND whose output is connected to the second input of the third element OR, the output of the end of blocking of the memory block These microprograms are connected to the installation inputs in the mask register triggers, to the installation input to zero of the second control trigger, the output of the sign of the end of the micro-command register operation is connected to the first inputs of the elements of the fourth group, whose outputs are are connected to the inputs of the I installation in O from the first to the Nth trigger of the end of operation register, the inverse outputs of which are connected to the inputs of the AND – NE element whose output is connected to the control input of the clock generator, the third input of which is connected to the counting input of the counter, output whose so11 dinene with the control input of the second multiplexer of the interlock signals, each of the inputs of the device command codes is connected to the inputs of the corresponding OR elements of the second group, the outputs of which are connected to the first inputs of the elements And the fifth group, the outputs of which are connected to the installation inputs of 1 trigger register of the end of operation, the output of the sign of the end of the micro-command register operation is connected to the second inputs of the elements of the sixth group, the outputs of which are connected to the first inputs of the elements OR of the third group, the outputs of which are connected to torymi inputs and the KJ elements of the group decoder outputs are connected to second inputs of AND gates of the first group to the second inputs of AND gates of the third and fourth groups, the first inputs 2723332 elements of the sixth group, outputs of the elements of the first group are connected to the second inputs of the corresponding elements OR of the third group and with the synchronization inputs from the first to the Nth registers of the logic conditions code, the output of the first multiplexer of the lock signals is connected to the information input of the third control trigger, output which is connected to the third input of the third OR element, the fourth output of the clock pulse generator is connected to the synchronization input of the third trigger set 15, the second output of the clock generator and pulses coupled to the second inputs of AND gates of the first group, the third output, the clock generator with entrance connected to the register of micC I I UuKflt I zamg I Uu / fffJ I UuKntf -W / ifffl liSi ff6l Sh SSI ffl i5 FIG. 6