SU1280608A1 - Device for comparing numbers - Google Patents

Abstract

The invention relates to automation and computing and can be used in digital computers. The purpose of the invention is the expansion of the field of application due to the possibility of comparing with the standard and combining the processes of recording and comparing numbers. The device contains a master register, ring shift registers, comparison circuits, triggers, AND elements, priority block. The device allows bit-wise comparison of the codes recorded in the ring shift registers with the reference and comparison locks in those registers in which a mismatch with the reference occurred. In registers excluded from further comparison, it is possible to write new codes when controlling signals from a priority block. 2 Il. (/

Description

The invention relates to automation and computing and can be used in digital computers.

The purpose of the invention is to expand the field of application due to the possibility of comparing with the standard and combining the processes of recording and comparing numbers.

FIG. 1 shows a functional diagram of the device; time diagram of the device; 2 a priority block diagram.

The device (Fig. 1) contains a register of 1 standard, ring shift registers 2, comparison circuits 3, interlocking elements AND 4, triggers 5, analysis elements AND 6, triggers 7, priority block 8, mode selection elements 9, initial setup input 10 11 clock pulses, information bus 12, mode selection input 13, reference code input 14 and recording resolution input 15.

The device works as follows.

In the register of the standard there is a reference binary code, in the registers

2- codes, compared with the standard. A pulse is applied to the input 10, which sets the triggers 5 to 1, and the triggers 7 to the O. Setting the triggers 5 to 1 allows the shift in the registers 2. On the bus 11, the clock pulses are fed to the synchro input of the shift of the standard 1 and through And 4 elements - on the shift register register 2 inputs, which causes a sequential shift of information in all registers. Circuit 3 comparisons compare the bit of information at the output of register 1 of the standard with the corresponding bit of information at the outputs of registers 2. In case of a discrepancy between the discharge of the standard and the bit at the output of register 2 at the output of the circuit

3 comparisons appear level 1,

coming through an open element And 6 to the input of the trigger setup 7 and the reset input of the trigger 5. Level 1 from the trigger output 7 enters the input of the priority block, and the logic zero level from the trigger output 5 closes the And 4 and 6 elements, stopping the shift in the corresponding register 2 and block the further receipt of the mismatch signals to the inputs of the triggers 5 and 7. Since each

the house of registers 2 the mismatch is fixed independently; several single signals are simultaneously fed to the inputs of block 8 with the trigger output

7. The priority block selects only

one (for example, the leftmost one according to the scheme) of the incoming signals, i.e. a single signal appears only at one output of a priority block corresponding to the left-most (according to the scheme) of its inputs to which unit levels are applied. This signal from the output of the priority block is fed to one input of the corresponding element AND 9, opening it. After this, a new code can be fed to the information bus to write to the corresponding register 2. The recording is performed by applying a gate pulse to input 13. This gate pulse through an open element 9 enters the synchronization input of register 2, recording information supplied to bus 12, and entering the reset input of trigger 7, i resets it to O. After this, priority block 8 selects a new one (the leftmost one) trigger 7, opens the corresponding AND 9 element. to write information to the new register 2. etc. while there are set in 1 triggers 7.Pro. The process of recording information in registers 2, in which a mismatch with the standard occurred, can occur simultaneously (and independently) with the continuation of comparison with the standard of the contents of other registers. At the end of the comparison cycle, the reference code is, in register 1, the former position (the same as before the commencement of the comparison) due to the fact that in each step of the comparison the bit from the last bit of the register to

its output is fed from the output to the serial information input of the register and is written to its first bit. Similarly, in registers 2, in which there was no discrepancy,

codes at the end of the cycle occupy the same position as before it began. About the results of comparing the code recorded in this register 2 (a mismatch occurred or did not occur),

can be judged by the status of the corresponding trigger 5. If the trigger 5 at the end of the comparison cycle remained in one state, the code in register 2 is the same. with reference. By

312806084

the condition of the corresponding trigger of the standards and the combination of the processes of recording and comparing numbers, n parameters of the analysis are entered into it, n additional triggers, the priority block 7 is the same, then the corresponding register and the register of the standard can be judged whether new code is in register 2 or not. If trigger 5 is turned into O and trigger

There was a mismatch with the standard, and a new code could be written to it. After finishing the comparison cycle, you can start a new one as described.

Claims (2)

The invention relates to automation and computing and can be used in digital computers. The purpose of the invention is to expand the field of application due to the possibility of comparing with the standard and combining the processes of recording and comparing numbers. FIG. 1 shows the functional scheme of the device; time diagram of the device; 2 a priority block diagram. The device (Fig. 1) contains a register of 1 standard, ring shift registers 2, comparison circuits 3, interlocking elements AND 4, triggers 5, analysis elements AND 6, triggers 7, priority block 8, mode selection elements 9, input 10 of the mouth 11 clock pulses, information bus 12, mode selection input 13, reference code input 14 and recording resolution input 15. The device works as follows. In register 1 of the standard there is a reference binary code, in registers 2 there are codes comparing with the standard. A pulse is applied to the input 10, which sets the triggers 5 to 1, and the triggers 7 to the O. Setting the triggers 5 to 1 allows the shift in the registers 2. On the bus 11, the clock pulses are applied to the shift register register 1 of the standard and through the And 4 elements - to the synchronous inputs of the shift of the register 2, which causes a sequential shift of information in all registers. Circuit 3 compares the bit of information at the output of register 1 of the standard with the corresponding bit of information at the outputs of registers 2. If the discharge of the pattern does not coincide with the bit at the output of register 2, level 1 appears at the output of the comparison circuit 3 element 6 to the input of the trigger setup 7 and the trigger reset input 5. Level 1 from the trigger output 7 enters the priority block input, and the logical zero level from the trigger trigger output 5 closes the elements 4 and 6, stopping the shift in the corresponding register 2 and blocking The earliest receipt of the mismatch signals to the inputs of the triggers 5 and 7. Since in each of the registers 2 the mismatch is fixed independently, the inputs of block 8 receive several single signals at once with the output of the trigger 7. The priority block selects only one (for example, the leftmost one according to the scheme) signals, i.e. a single signal appears only at one output of a priority block corresponding to the left-most (according to the scheme) of its inputs to which unit levels are applied. This signal from the output of the priority block is fed to one input of the corresponding element AND 9, opening it. “After this, a new code can be fed to the information bus to write to the corresponding register 2. Recording is performed by applying a strobe pulse to input 13. This strobe pulse through the open element I 9 arrives at the synchronization input of the register 2 record, records information supplied to the bus 12, and enters the reset input of the trigger 7, i resets it to O After this, the priority block 8 selects a new (leftmost of the remaining) trigger 7, opens the corresponding AND 9 element. To write information to the new register 2. etc. the triggers set in 1 are still present. The process of recording information in registers 2, in which a mismatch with the standard has occurred, can occur simultaneously (and independently) with the continuation of comparison with the standard of the contents of other registers. At the end of the comparison cycle, the reference code occupies the previous position in register 1 (the same as before the beginning of the comparison) due to the fact that at each comparison step the bit generated from the last bit of the register to its output is output from the serial information input of the register is recorded in its first bit. Similarly, in registers 2, in which there was no discrepancy, the codes occupy the same position at the end of the cycle as before its beginning. The results of the comparison of the code recorded in this register 2 (a mismatch occurred or did not occur) can be judged by the status of the corresponding trigger 5. If the trigger 5 at the end of the comparison cycle remained in one state, the code in register 2 matches. with reference. According to the 312 state of the corresponding trigger 7, it is possible to judge whether the new code is written to register 2 or not. If trigger 5 is set to O and trigger 7 is the same, then in the corresponding register 2 there was a mismatch with the standard, and a new code could be written to it. After finishing the comparison cycle, you can start a new one as described. Apparatus of the Invention A device for comparing numbers, containing n ring registers, r shift, where n is the number of compared numbers, n comparison circuits, n blocking elements, n –– mode selection elements, l triggers, the input of the initial installation of the device connected to the installation inputs a single state of the trigger, the output of the i-ro trigger, where i 1,2 ,, .., p, is connected to the first input of the i-ro element And blocking, the input for selecting the device mode is connected to the first inputs of the element AND for selecting the mode, the first inputs of all comparison schemes are combined, inform The register inputs are connected to the device information bus, characterized in that, in order to expand the field of application J due to the possibility of comparing with standards and combining the processes of recording and comparing numbers, n parameters of the analysis, n additional triggers, priority block and the reference register, whose information inputs are connected to the device reference code inputs, and the high-order output is connected to the first inputs of all comparison circuits, the second input of the i-th comparison circuit is connected to the high-output output i -ro annular shift register, and the output is connected to the first input of the i-ro element of the analysis, the second input of which is connected to the output of the i-ro trigger, the output of the i-ro element of the analysis And is connected to the inputs of the installation in the zero and single states, respectively ro trigger and i-ro additional trigger Irepa, the output of which is connected, with the i-th input of the priority block, the i-th output of which is connected to the second input of the i-ro element AND mode selection, the output of which is connected to the recording enable input of the i-ro ring register shift, the shift input of which is connected to the output of the i-ro ele And the interlocks, the second inputs of all the elements And the interlocks and the shift input of the reference register are connected to the clock input of the device.