AU643512B2

AU643512B2 - A sequencer for generating binary output signals

Info

Publication number: AU643512B2
Application number: AU73713/91A
Authority: AU
Inventors: Dominique Castel
Original assignee: Alcatel NV
Current assignee: Alcatel Lucent NV
Priority date: 1990-03-26
Filing date: 1991-03-22
Publication date: 1993-11-18
Anticipated expiration: 2011-03-22
Also published as: DE69112462T2; ES2076394T3; FI98665C; NO911215L; NO301446B1; FR2660087A1; FI911396A0; FR2660087B1; DK0449190T3; FI911396A; EP0449190A1; EP0449190B1; ATE127247T1; AU7371391A; FI98665B; DE69112462D1; NO911215D0; GR3017644T3

Abstract

The programmer producing binary output signals (5) in response to a clock signal (R) identifying time intervals, each output signal starting and terminating within distinct time intervals, comprises a memory (1) provided with a start location having an allocated address and an end location having an allocated address for each output signal (S), means of reading making it possible to read the digital values in these locations, means of control (2, 5) determining the operation of the means of reading with the aid of an address generator in such a way that all the locations are read during each of the time intervals, means of comparison (3) producing an equality signal (E) when a first field of a location has the same value as a first field of the time interval in which the reading takes place, and means of decoding (4) producing or interrupting the output signal (S) which corresponds to the location for which the said equality signal is produced according to whether the latter is respectively a start location or an end location. <IMAGE>

Description

643512

ORIGINAL

COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 S S 9.

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COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED .90.0

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5505 59 "A SEQUENCE FOR GENERATING BINARY OUTPUT SIGNALS" The following statement is a full description of this invention, including the best method of performing it known to us:- 05 0 S oS S S This invention relates to a program control element for generating binary output signals in response to a timing signal.

Such a program control element is known as a sequencer and is a device whose output signal controls the operation of various equipments according to a set sequence. This sequence is generally recorded in the sequencer itself and progresses according to a rhythm defined by an external timing signal.

A first known solution, in which this timing signal is a clock signal, consists of using for each equipment to be controlled, a first reversible counter preset to a start value and a second reversible counter preset at an end value, each receiving this clock signal. The corresponding output signal starts when the first reversible counter reaches zero, and it ends when the second reversible counter reaches zero.

A second known solution, in which the timing signal is a digital signal issued from a counter being incremented by a clock, consists of having for each equipment to be vontrolled, a first and a second comparator respectively comparing the timing 15 signal start xalue and end value. The corresponding output signal starts when the first comparator detects an identity at its inputs, and ends when the second comparator also detects an identity.

Both solutions are well suited when the sequencer generates few output signals.

When the number of equipments to be controlled becomes significant, the number of modules associated with each output signal (comparator, counter) consequently increases and the sequencer requires a great number of elementary cells such as logic gates in order to be implemented. There follows an increase in the silicon surface required for its integration, an increase in energy consumption and consequently, an *6 increase in cost.

Hence, the aim of the present invention is to provide a sequencer for generating output signals in response to a timing signal and including a small number of lementary cells if ever the number of these output signals exceeds a few units.

S"According to the present invention there is provided a program control element for generating binary output signals in response to a timing signal used to identify the time slots, each output signal starting and ending during distinct time slots, said control element including a memory having a start location assigned with an address and an end location assigned with an address for each output signal, read facilities used to read the digital values within these locations, control devices determining the operation of the said read facilities by means of an address generator such that all locations are read during each of the said time slots, a comparator generating an equality signal when a first location field has the same value as a first time slot field in which reading occurs, and a decoding device which either generates or interrupts the output signal corresponding to the location for which the equality signal is produced, depending on whether the location is either a start location or an end location.

According to an alternate implementation of the present invention, the comparator generates the equality signal if, in addition, a second location field has a defined value called periodicity value.

The invention has the advantage that the decoding device also includes a sync register such that all the output signals having to change state during the said time slot do so in synchronism.

O OO Preferably, the timing signal is issued from a first counter.

Preferably, the memory is a RAM including write facilities used to write the :0.15 digital data to memory, and the :ontrol devices generate a control signal capable of controlling either the read or the write facilities. Preferably, the control devices in- Sclude an address selector which positions the memory either at the address indicated Sby the address generator or at a write address depending on whether the control signal is respectively controlling either the read or the write facilities.

Preferably, in the control devices receiving the clock signal, the address generator includes a second counter receiving this clock signal and producing as address a frst field of the value indicated by this second counter.

Preferably, the control devices determine the value of the control signal in relation to the value of a second field of the second counter.

Preferably, the clock signal frequency and the capacity of the second counter are S. designed such that the second counter can perform a complete cycle during each of the time slots.

Preferably, the decoding device includes an enabling register delivering an output signal only if an enable information peculiar to it is present.

In order that the invention may be readily carried into effect, an embodiment thereof will now be described in relation to the drawings, in which: Figure 1 is a diagram of the sequencer generating binary output signals in response to a timing signal, in accordance with the invention.

Figure 2 is a diagram of the devices controlling the sequencer memory.

Figure 3 is a diagram of the sequencer comparator.

Figure 4 is a diagram of the sequencer decoding device.

Identical components appearing in several figures bear the same reference number.

The sequencer according to the invention is shown in Figure 1. It is arranged to receive a digital timing signal which, by convention, identifies time slots. It generates 2-state output signals It consists mainly of a memory where the information pertaining to the various output signals is stored, a memory control device a comparator used to detect the equality between a memory information and a time slot, and a decoding device used to either generate or interrupt an output signal when the comparator has identified an information concerning it.

Memory is of no particular type. It can be A ROM or a PROM. In the following implementation example it is a RAM. It is therefore design i to receive a .15 read signal (RD) placing it in read mode and a write signal (RW) placing it in write 6** S mode. Both signals are shaped by a scan cell receiving control signal the nature of which will be detailed later.

This memory has locations identified by an address whose number is set at 2" in this example. These are designed to contain the digital values made up of k-bits. The memory is therefore structured to receive an address signal on n-wires and an input data (Di) on k-wires, and to generate an output data (Do) also on k-wires.

In read mode, the memory generates as output data (Do) the digital value stored at the location identified by the address signal while in write mode, it writes the S.input data (Di) to this location.

Both locations are associated with each of the output signals, the first corresponding to the start of such a signal, and the second corresponding to the end. It will later be assumed that all memory locations are associated with an output signal.

This hypothesis designed to cla.rify the description should not be considered as a restriction of the invention which, in the opposite case remains perfectly applicable.

Timing signal successively identifies time slots, each of them being likely to trigger the change of state of one of the output signals if they have the same value as the content of one of the two locations assigned to this signal. Memory control device shown in Figure 2 are designed such that the digital values written in all locations can be accessed during each time slot. It includes an address generator (21) generating a read address signal (Ar) successively assuming all values between 0 and 2"-1 which correspond to, the addresses of all memory locations. The generator will be, for instance, a counter incremented by a clock signal (Ck).

Control device is also designed to allow the digital values to be written to memory during each time slot. To this end, the capacity of the counter is greater than the number of addresses.

It may be set equal to 2" 2" for instance, this implies that the counter has an output on n 1 bits. The most significant bit, ie. the bit which identifies the values greater than or equal to is used to generate control signal which, when at 1 or 0 respectively defines the write or read mode. In addition, memory control device includes a multiplexer (22) which generates address signal having a value equal to the read address signal (Ar) or to a write address signal (Aw) received '0.0 by the sequencer depending on whether control signal is respectively equal to 0 or 1.

9 9 15 Hence, driing a complete cycle of counter all memory locations are read S •o accessed by their address which is determined by a field of this counter corresponding to the n-least significant bits, then when the most significant bit is aL 1, input data (Di) are written to the locations identified by write address signal If clock signal (Ck) is periodical and has a frequency f, such that the counter cycle occurs exactly during one time slot, two thirds of this time slot are used in read mode and the remaining third in write mode.

Memory control device described above is given as an example, and the invention does not exclude other means of implementation. In particular, the devices S allowing a write operation during a time slot are not strictly necessary to the operation of the invention, especially if the memory is a ROM. It is also possible to envisage other facilities to write the d'gital values to memory whether it be during time slots or during a period when the sequencer does not fulfil its control function on o output signals The sequencer also includes a comparator receiving a timing signal made up of k-bits and memory data output (Do) also made up of k-bits. In a first form, they produce an equality signal when the time slot and the output data are identical, and therefore consists of a simple equality comparator. The values to be compared can be subdivided into fields, in this case, the scan fields include the i.itegrality of these values. In a more elaborated form, shown in Figure 3, they generate this equality signal in case of partial identity of output data (Do) of the time slot, ie. for the identity of one field of these values. In the example shown, the latter include 16 bits 16). The output data and the time slot each including a first field made up of 11 LSB (at the top of the figure) and a second field made up of 5 MSB (at the bottom of the figure). The equality signal is generated in this case, if there is identity of the first fields and if periodicity signal P is present. This signal is shaped by a periodicity detector (31) when there is identity of the second fields and if the second output data field has a specific value called periodicity value. The periodicity detector comprises five "EXCLUSIVE NOR" gates (32) each receiving a bit of the second output data field and of the time slot, and hence generating a I in case of identity; the outputs of the five gates are injected on the inputs of a first "NAND" gate (33) which therefore generates a 0 in case cf identity of the second fields. It also includes a second "NAND" gate (34) which generates a 0 if, and only if, the five bits of the second data output field are at 1, ie. if the periodicity value is mde up of five I.

15 Periodicity signal is issued from a third "NAND" (35) receiving the outputs of the

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other two NAND gates (33, 34).

Comparison of the first output data fields and of the time slot occurs in a similar manner, the bits of either one being compared one by one by means of "EXCLUSIVE NOR" gates Three "NAND" gates (36) receive each a part of the outputs of the previous gates, one of the "NAND" gates also receives periodicity signal If the lgo.: first fields are identical, if, in addition, peridicity signil is present, and only in this case, the outputs of these three "NAND" gates (36) are therefore at 0. A "NOR" gate 37 generates the equality signal from these three outputs.

S• The timing signal has the advantage to be issued from a counter although this is not a requirement according to the invention. In this case, this counter incremented by a timing clock will trigger the generation of equality signal for each memory Slocation whose second field is assigned the periodicity value with a repetition period S •corresponding to 211 timing clock pulses of frequency f 2 An advantageous solution consists of setting f 2 equal to the ratio of control device counter frequency f, over the counter capacity (counter 21 of control device 2).

Comparator described above, and in particular the means used to generate an equality signal repetitively by using the periodicity value, are given as examples and should not be considered as a restriction of the invention.

Decoding device making up the last component of the sequencer, is described below in reference to Figure 4. It includes a decoder (40) controlled by equality signal linked via a first link (L1) to a first register (41) comprising one bit for each memory location, ie. Decoder (40) places to 1 the bit of the first register corresponding to the location during a read operation when the equality signal is present.

The first register (41) is connected via a second link (L2) to a second 2"- 1 -bit register Each bit of this register associated with an output signal is set to 1 when the bit of the first register (41) corresponding to the output signal start location is at 1, it is set to 0 when the first bit of register (41) corresponding to the output signal end location is at I. This second register (42) is eventually synchronised on timing signal It will therefore be called sync register.

Facilities used to reset the first register (41) and not illustrated, are provided to reset all the bits of this register once they have been acknowledged by the second register These facilities are periodically controlled at the frequency of the timing signal at the start or at the end of each time slot for instance.

s ea an optional implementation alternative, a third 2"'-bit register each bit associated with an output signal, receives the information issued from register (42) via a third link An output signal is generated if its corresponding bits in the second (42) and third (43) register are at 1. This third register can be advantageously used to individually enable each output signal, it will therefore be called enabling register.

As an example, when memory is powered up, the digital values it contains are undefined. It is therefore desirable to enable an output signal only when it will S have effectively been written to this memory.

The sequencer as described above, using a memory having 2" words of k-bits, ucan control 2 1 output signals according to a sequence presenting 2 k steps. It can also periodically control certain signals during the same sequence.

In a slightly different version of the sequencer, the output signal start and end locations are assigned the same address. The comparator is structured to compare both locations and to generate and send two signals to decoding device such that the latter can determine whether this is the start or the end of the output signal identified by this address. This version being easily implcmented by a person versed in this art, it will not be detailed further.

Claims

1. A sequencer for generating binary output signals in response to a timing signal useu to identify the time slots, each output signal starting and ending during distinct time slots, said sequencer including a memory having a start location assigned with an address and an end location assigned with an address for each output signal, read facilities used to read the digital values within these locations, some control devices determining the operation of the said read facilities by means of an address generator such that all locations are read during each of the said time slots, a comparator generating an equality signal when a first location field has the same value as a first time slot field in which reading occurs, and a decoding device which either generates or interrupts the output signal corresponding to the location for which the equality signal is produced, depending on whether the location is either a start location or an end location.

2. A sequencer as claimed in claim 1, wherein the said comparator generates 15 the said equality signal if, in addition, a second location field has a defined value S called periodicity value.

3. A sequencer as claimed in claim 1 or claim 2, wherein the said decoding device also includes a sync register such that all output signals having to change state during the said time slot do so in synchronism. 20

4. A sequencer as claimed in any one of the preceding claims, wherein the said timing signal is issued from a first counter.

A sequencer as claimed in any one of the preceding claims, wherein the said memory is a RAM, and including some write facilities used to write the digital value to memory, and in that, the said control devices generate a control signal capable of controlling either the read facilities or the write facilities.

6. A sequencer as claimed in claim 5, wherein the said control device also includes an address selector positioning the said memory either at a read or write address depending on whether the said control signal respectively controls either the read facilities or the write facilities.

7. A sequencer as claimed in claim 6, wherein the said control device receives a clock signal, the said address generator comprises a second counter 'for receiving said clock signal and generates as address a first field of the value indicated by this second counter. 9

8. A sequencer as claimed in claim 7, wherein the said control device determines the value of the said control signal in relation to the value of the second location field of the said second counter.

9. A sequencer as claimed in claim 8, wherein the frequency of the said clock signal and the capacity of the said second counter are arranged such that said second counter can prform a complete cycle during each of the said time slots.

A sequencer as claimed in any one of the preceding claims, wherein the said decoding device includes an enabling register delivering a said output signal only if an enable information peculiar to it is present.

11. A sequencer for generating binary output signals in response to a timing signal used to identify the time slots, each output signal starting and ending during distinct time slots, substantially as herein described with reference to Figures 1 4 of the accompanying drawings. DATED THIS SEVENTEENTH DAY OF AUGUST 1993 A N ALCATEL N.V. *i