SU1089576A1 - Device for classifying n-bit binary combinations - Google Patents

Abstract

A CLASSIFICATION DEVICE FOR VARIABLE BINARY COMBINATIONS containing m binary correlators, where m is the number of classes containing one binary combination each, information inputs, clock pulse inputs and sync binary correlators are connected to the information input, clock pulse inputs and device sync inputs, and outputs binary correlators are connected to the corresponding code inputs of the extremator. characterized in that, in order to expand the field of application by providing a classification into (fn + O classes, among which m classes contain by an optional combination, and () th class -

Description

The invention relates to communications and can be used in discrete message processing devices for classifying -digit binary combinations of m classes containing one each and one class containing 2 -t) combinations. A classification device containing an N-bit shift register is known, the discharge outputs of which through the elements are connected to the vertical buses of the memory unit, whose horizontal buses m are connected via threshold circuits to the outputs of the device ft 1. The disadvantage of this device is the low accuracy of the class cases, if the alphabet of selective combinations significantly exceeds m. A false classification, in this case, is determined by the low resolution of the analog circuit for the formation of a correlation measure and a large number of combinations inations close to standards. The closest in technical capacity to the present invention is a classification device containing Hp binary decoder matched filters whose outputs are connected to the extremator inputs, which "high" is the output of the C 23 device. Not | 1 () is the remainder of this device x, when m classes contain one combination at a time, and (mon-1) -th class - the rest (2 -n) combinations. This disadvantage is determined by the logic of the device, which, from some 2 selective combinations, belongs to one of the m classes. This deficiency in pinching can be eliminated if (2G-t) binary decoding matched filters are introduced in the device for the (m-fl) -th class. However, such a classification device for large M will be extremely difficult. The second drawback of the classification device is the low efficiency of its adjustment to new class standards, which is associated with the need to replace matched filters. This disadvantage can be eliminated by using instead of the correlators on the matched filters of digital binary correlators that contain the selective combination register, the reference register and the comparator of these combinations. However, the disadvantage of such a correlator is the impossibility of using standards with non-informational positions, i.e. positions whose binary signals do not participate in comparison with the corresponding signals and selective combination signals. The purpose of the invention is to enhance the functionality of the device for classifying N-bit binary combinations by providing classification into (pm-1) classes. Among which m classes contain one combination each, and the () class - (2 -n) combinations. This goal is achieved by the fact that the classification device for N-bit binary combinations contains m binary correlators, where m is the number of classes containing one binary combination each, with information inputs, clock and synchronization inputs of binary correlators being connected respectively to info 1 The input input, clock pulse inputs and device synchronization, binary correlator outputs are connected to the corresponding extremator code inputs, a symphonic block is entered, a group of in elements And elements t W-NB, the inputs of the first group of the threshold block are connected to the outputs of the extremal extremals code, the inputs of the second group with the inputs of the device Threshold task numbers, the first inputs of the AND elements of the group are connected to the corresponding positional outputs of the accelerator, the second inputs to the corresponding outputs of the threshold block, and the output elements and groups - to the corresponding positioning outputs of the device and the inputs of the SH- KE element, the output of which is the (n + 1) th position of the device. FIG. t shows the scheme of the classification device (an example of the implementation of the binary correlator of N-bit binary combinations); FIG. 2 is a diagram of a threshold unit with an “n-threshold classification; in fig. 3 is a diagram of a threshold unit for single-threshold classification; in fig. 4 is a block diagram of a cyclic shift of the combinations included in the binary eagle torus; in fig. 5 - diagrams of input binary signals and clock 3 10 out pulses; in fig. 6 - examples of the contents of the registers selective combination of the standard and the mask. The device for classifying N-bit binary combinations (Fig. 1) contains t-binary correlators 1, extremator 2, threshold block 3, to elements AND 4, element OR-NOT 5. Each binary correlator 1 contains .6 cyclic shift block selective combination, block 7 of the cyclic shift of the standard, block 8: cyclic. shift mask, block 9 comparison, the element And 10, a summing counter 11, block 12 synchronization, the element OR 13 the first element NO 14, the driver 15 command shift reference, the second element NO 16, the driver 17 command shift mask. FIG. 1 also shows information input device 18, input 19 clock pulses, reference input 20, reference clock input, reference input 22, reference input commands, input 23, masks, output 24 of the mask input clock, input 25 of the mask input command, input 26 Sync pulses in each binary correlator 1, positional outputs of the device 27, the first group of inputs of the threshold unit 28, the inputs for setting the threshold 29, the outputs 30. threshold block 3. The threshold block 3 at the m-threshold classification (. 2) contains m blocks 31 comparing the type of threshold registers 32.

Thresholds unit 3 for single-threshold classification (Fig. 3) contains a comparison unit 33 and a threshold register 34. 40

The cyclic shift unit 6 of the sampling combination (Fig. 4) contains the shift register 35, the first element AND 36, the element IL 37, the element 38, the second element AND 39, the infrared 5 stroke 18, the clock input 40, the control input 41 , exit 42..

Block 7 of the cyclic shift of the standard and block 8 of the cyclic shift of the mask are identical to block 6.50

The pa6oTaet classification device is as follows.

Received binary signals in the form of a sequence of elementary parcels O, 1 (Fig. 5 ") receive ss yo to the input 18 of the correlators 1 to the information input of the cyclic shift block 6 of the selective combination (Fig. 1).

Shift ditch pattern and masks, respectively, of the classes.

After the 3-bit binary signal, the correlators 1 compare the sample combination with the references at their informational positions. For this TI from input 19, simultaneously with the recording of the binary signal, the counter 11 is set to 1 O in summation, and the synchronization unit 12 is initiated, which, in sync pulses arriving at input 26, generates the following control signals w in the clock interval: on the first output a packet of pulses, on the second the output of the recirculation command (CRC) in the form of a logical .I signal, coinciding in time with the packet. CRC arrives at the control input 4f of block 6, opens the element AND 36 in it and closes the element AND 39 (thanks to the element NOT 38). As a result, block 6 is transferred to mode 6. Input 19 from the synchronization device (not shown in Fig. 1) receives clock pulses synchronized with t binary signals (Fig. 5S). Each clock pulse (TI) passes through the OR element 13 to the clock input 40 of block 6, clocking with the clock input of the shift register 35 (FIG. 4), shifts the register contents one bit to the right and writes into the register the followed binary signal that goes to its information input 18 through the element AND 39, element OR 37, which is open at this time. As a result, at each clock interval (interval between adjacent TIs) the N -digit shift register 35 contains a selective combination formed by binary signals received in this and in (N-1) previous clock intervals. For the example in FIG. white, 6 shows selective combinations contained in shift register 35, respectively, in k and (k + 1) -th clock intervals. The N-bit register — the shift in the standard cyclic shift unit 7 and the cyclic shift unit 8 of the correlator mask 1 contain a standard and a mask of its class, and the mask code indicates the information positions of the standard (in the Information Positions of the mask shift register contain 1, on non-informational dosages - O). For the example in FIG. no, V shows the contents of the register $ 1 of the recirculation, in which the information input 18 is prohibited, and the output of the shift register 35 through the elements AND 36, OR 37 is connected to its input. Logic 1 at the control input of block 7, coming from the output of the body of the command 15 of the shift command in the absence of the input command 22 at the input 22, and logical 1 at the control input of block 8, coming from the output of the mask shifter 17 of the input command when there is no input de 25 commands for entering masks, similarly, blocks 7 and 8 are transferred to recirculation mode. In this case, information inputs 20 of block 7 and 23 of block 8 are prohibited. Packet pulses from the first output of synchronization block 12 to clock inputs of blocks 7 and 8 directly and block 6 through the element. OR 13, synchronous cyclic shift (recirculation) of the contents of the shift registers 35 of blocks 6, 7 and 8 is performed. At the output of block 6, the selective combination bits appear, the standard bits output 7, and bits 8 at the output of block 8 masks. Block 9 compares the bits of the sampling combination and the reference and generates at its output a logical 1 signal with a coincidence and a logical O with a mismatch of the compared bits. Comparison results are gated with burst pulses to an output of an AND 10 element, which blocks the flow of comparison signals to the input of summing counter 11 when the output of the block 8 bit O corresponds to a non-information position. At the end of the burst, the sampling combination, the master and mask will take up their original position in the shift registers of 35 blocks 6, 7 and 8, and the counter 11 will contain the number of coincidences of the binary signals of the sample and the sampling combination at the information positions (correlation number). The correlation codes m of correlators 1 from the outputs of counters 11 are fed to the code inputs of the extruder 2, which outputs the maximum number code at outputs 28, and the maximum number number code signal (logical signal 1) is generated at the m position outputs the positional output of an extremator, if its -i code input contains 6 maximum number). Thus, extremator 2 performs classification into m classes, the selective combination is related to that class, with the standard of which at informational positions it has the greatest coincidence. The threshold unit 3, the elements AND 4, OR-NOT 5 carry out the classification into () classes, not selective combinations belonging to (ti-1) -th class, which have an inadequate proximity to the standards. When tn is the threshold classification in threshold block 3 (Fig. 2), comparison blocks 31 compare the maximum number arriving at inputs 28 to the thresholds contained in registers 32, If the maximum number is not less than the i-ro threshold (, 2, ... , m), the comparison unit 31 outputs a signal at the output 30, an opening element AND 4.J. If, at the same time, extremator 2 attributed the selective combination to the i-th class, then the signal from the i-ro positional output of the extremer 2 passes through the element 4/4 to the positional output 27, i.e. The selective combination is left in the jth grade. In the remaining cases at the positional outputs 27, 27, ..., 27fp. there is a logical O, at output 27. ,, of an element OR NOT 5 - logical 1, i.e. Selective combination belongs to the OP + O-MU class. With one threshold classification in threshold block 3 (Fig. 3.), the maximum number is compared by block 33 with one threshold contained in register 34, the classification is the same. Inputs 29 serve to load the threshold numbers into registers {32 and 34. To enter the reference, input 22 of the corresponding correlator 1 is given a command to enter the reference, which starts the driver 15 of the command for shifting the reference. The latter isolates a single inverted CRC from the CHC sequence received at its second input from the second output of the synchronization unit 12. The inverted CRC from the output of the imaging unit 15 allows the passage of a burst of pulses through the element NO 14 to the output 21. It switches the block 7 to the input mode of the standard, opening the E39 element in it (thanks to the HE 38 element) and closing the E 36 element (Fig. 4). The reference bits are read by a burst of pulses from an external register (not shown in Fig. 1) to the input 20 of the reference and are written to the shift register 35. Simultaneously with the recording, the selective combination is also compared with the old reference, since block 7 is recirculated and the reference is sequentially pushed out Record the data to the input of the block 9 of the comparison. Similarly, a mask is introduced when applying to the input 25 a command for inputting a mask to the input of the former 17 108 6 using a packet of pulses at output 6 and 24 dp of synchronization of the external register. The technical and economic effect of using the proposed device consists in expanding the field of application of the classification device, which is ensured by classifying into O + 1) classes, and the flexibility of using correlators 1 due to separate input of the standard and mask.

lh (ovf / cMf / Koffdt / ffotfffff ntche / t

eiMfffferowoff / ft dffifAXitf / ff

A

1- :: jfi

/ /

 7bfyrr9 6f € ivime f & "SrSt /

TtfK / ifo t /

- - “w @ F :: -; -,

Tb ftffM l

-g- Ufff ffotfifOf /

/ | W

Tixtyr kf

 T t;

vfffjif

3

-I

I t 11 I t

ffiifre

i / f.ff

Claims (1)

CLASSIFICATION DEVICE ^ BIT BINARY COMBINATIONS containing m binary correlators, where tn is the number of classes containing one binary combination, and the information inputs, inputs of clock pulses and synchronization of binary correlators are connected respectively to the information input, inputs of clock pulses and device synchronization, binary outputs The correlators are connected to the corresponding code inputs of the extremator, Does it mean that, in order to expand the scope by providing classification into (tn + Ι) classes, among which m classes contain one combination each, and the (pm-1) th class - ( 2 ^Ν -π \) combinations, a threshold block, a group of r elements AND and an OR-NOT element are introduced into it, the inputs of the first group of the threshold block being connected to the outputs of the extremator extremal code, the inputs of the second group with the inputs of the numbers' setting the device threshold, the first inputs of elements AND groups are connected to the corresponding positional outputs of the extremator, torye inputs to outputs coot- g sponding block threshold, and outputs the AND groups - corresponding to the position output device and inputs of the OR-Nyo, whose output is the (m + 1) th position output device.