SU1270898A1 - Detector of combination of binary signals - Google Patents

Description

The invention relates to communications and MOKet is used in discrete message processing devices for detecting composite combinations of binary signals formed by 1 classes of n combinations of a known type with an unknown time of its arrival.

The purpose of the invention is to enhance the functionality by providing detection of a composite combination of binary signals formed by 1 classes of n combinations of known code.

FIG. 1 shows a structural electrical circuit for detecting a combination of binary signals, FIG. 2 is a variant of implementation of the cyclic shift signal, standard and mask blocks in FIG. 3 - timing diagrams explaining the operation of the binary signal detector.

Detection: the binary combination pattern tunic contains n1 correlators 1, - Inf, adder 2, comparison block 3, threshold register 4, cyclic signal shift block 5, element OR 6, first and second elements NOT 7 and 8, element 9, block 10 synchronizers, shaper 1 of shift commands 1 of extruders 12j - 12p and 1 cyclic shift blocks of masks 13 - 13, with the reference cyclic shift block 14, reference block 15, AND 16 element and summing counter 17 being part of each correlator , and the blocks of cyclic shift of the signal, the standard and the mask 5, 14 and 13 include the element ents I 18 I. 19, the element of ILR-20 and the shift register 21.

Binary Combination Detector

The signals works as follows. I

The received binary signals in the form of a sequence of elementary parcels 1 and O (Fig. Over) arrive at the information input of the cyclic shift unit 5, the clock input of which is synchronized with the binary signals through the element OR 6; Each clock pulse shifts the contents of shift register 21 one bit to the right and writes the received binary signal to it through the AND 18 element and the OR 20 element open at this time. As a result, in each clock interval (interval between adjacent clock pulses) N-bit shift register 21 contains a selective combination formed by binary signals received in the given and in N-1 previous clock internals (N is the number of binary signals in the composite combination: 1: 1). In FIG. 3c, d shows selective combinations contained in shift register 21 in K and (k + 1) -th

clock intervals

The N-bit shift registers 21 in the cyclic shift blocks of the mask 13 and the reference 14 contain masks and standards of their class, while the mask code indicates the formation positions of the reference (at the information positions the bits of the shift register 21 positions - O), for an example on

FIG. 3 shows the contents of the pattern and shift registers 21 in the case of a composite combination formed by two classes: in FIG. Zd, e - standards of the first class; in fig. Zzh mask first class; in fig. Зз, and standards of the second class; in FIG. 3, a second-class mask (an X indicates an indifferent state of the discharge of the shift register 21). In general

a composite combination is formed by 1 combination, with each class in a composite combination being represented by one combination, and the combinations of classes follow in a strictly defined

, follow up. In the above

An example of the first time is followed by a combination of the second class (Fig. Za, b, c, g, k).

Clock pulses simultaneously with

By writing a binary signal to the cyclic shift signal block 5, summing counters 17 are set to O and initiates synchronization block 10, which of the sync pulses arriving at its sync input generates the following control at the first output — a recirculation command into the logical 1 signal , at the second output, a packet of N pulses, at the additional output, a single pulse. The recirculation command receives the first control input jsa and through the second element NOT 8 - to the second control 1-th input of the cyclic signal shift block 5, opens And 19 in it and closes And 18 and puts it into recirculation mode, in which the information input is prohibited, and the output of register 2 G connects to its input through AND 19 and OR 20. In the absence of commands to input the second input, the shift command 11 generates a logical 1 at the output, which goes directly and through the first element NOT 7 to the first and the second control the inputs of the cyclic shift blocks of the standard 14.j -, and the cyclic shift blocks of the mask 13–13p and n-translates them into recirculation mode Packet pulses from the second output of the synchronization block 10 to the clock inputs of the cyclic shift blocks of the mask and the reference 13 , 13 and 14, - lAnl directly and to the clock input of the unit 5 cyclic- 20

shift signal through the element OR 6, synchronous cyclic shift (recirculation) of the contents of the shift registers 21 is performed. In this case, the output of block 5 of the cyclic shift of the 25 signal sequentially appears from the bits of the sampling combination, the output of blocks of 14 of the cyclic shift of the standard — the bits of the standards, and at the output of blocks 13 of the cyclic shift of the macro, bits of the mask. Blocks 15, -15, J juxtapose at their output a logical 1 signal with a coincidence and a logical 0 with a mismatch of the compared bits of the selective combination and standards. Comparison results are gated with pulses of bundles of output elements I. 16–16, which block the arrival of comparison results at the input of summing counters 17, –17 when a 13–13 bit O mask corresponding to the non-informational position appears at the output of the cyclic shift mask blocks. At the end of the packet, the sample combination, standards and masks will take up their initial position in the registers 21 of the shift of the cyclic shift units of the reference signal and the mask 5, 14 - 14f, and 13, - 13, and the summing counters 17, - 17, will contain the number of coincidences of the binary signals of the sampling combination and the corresponding standards at the information positions (correlation number). The correlation numbers obtained in this way in each group of n correlators 1 are a measure

Claims (1)

a composite combination that is read into the output of the device by a single pulse arriving at the gating 1-input of the block 3 of the comparison with the addition of the coincidence of the selective combination with the standards of this class. The correlation number codes from the outputs of the summing counters 15-15 are fed to the inputs of extremator 12, which selects the maximum number corresponding to the best match of the sampling combination with the class of combinations. The correlation codes from the outputs of the extremators 12 -12 are fed to the inputs of the adder 2, at the output of which a correlation number is formed equal to the number of coincidences of binary signals of the sampling combination and the composite combination at the information positions. If this number is not less than the threshold number contained in the threshold register 4, block 3 will compare the detection output signal of synchronization unit 10. Similarly, the detection processes take place in each clock interval. To enter the patterns and masks, an input command is sent to the corresponding input of the device, which triggers the shift instruction generator 11, which selects a single inverted recirculation command from the sequence of recirculation commands received at its first input from the first output of the synchronization unit 10. The inverted recirculation command from the output of the shift command generator 11 passes through the first element NOT 7 and opens element 9, but also directly and through the first element NOT 7 enters the first and second control, the inputs of the cyclic shift mask and reference blocks 13 - 13р and 14 - 14f, p, in which the element opens And 18 and closes the element And 19. Pulses of a packet with WTO,. synchronization passes through the element AND 9 to the output of the device, read the bits of the standards and masks from external registers (not shown), which arrive at the information inputs of the cyclic mask and standard 13 and 14 blocks, respectively, and are written into the corresponding shift registers 21. Simultaneously with the recording, the selective combination is also compared with the old standard 1 No., since. 5 cyclic shift of the signal is recirculated, and the standards are successively replaced by recorded data to the input of comparison blocks 15, masks to the input of elements AND 16 The invention The detector of a combination of binary signals containing the first correlator is made in the form of serially connected block of cyclic shift of a standard, comparison block And and summing counter elements, and the output of the cyclic shift mask unit is connected to the second input of the And element, and the third input of the And element is combined with the clock inputs of the cycle blocks the standard shift and the mask, to the combined first control inputs of which the output of the shift command generator is connected directly and to the combined second control inputs through the first element NOT, and the output of the cyclic shift signal is connected to the second input of the reference block, to the first control input which and to the first input form (U1 shift commands connected the first output of the synchronization unit directly and to the second control input through the second element NOT, the second output of the synchronization unit s to a first input of AND ensue. threshold connected register and comparison unit, the information inputs of the cyclic shift signal, reference and mask blocks, the second input of the shift command generator, the inputs of the threshold register and output comparison block are respectively the inputs of the information signal, reference, mask, input commands. threshold number and output of the device, characterized in that, in order to extend the functionality by ensuring detection of a composite combination of binary signals formed by 1 classes of n combinations of a known code, (1-1) correlators, made identical to the first correlator, are introduced, clock, the first and second control inputs of which are combined with the corresponding inputs of the first correlator,. extremators, (1.-1) cyclic shift blocks of the mask, adder and OR element, with the clock, first and second control inputs of each cyclic shift mask block combined with the corresponding inputs of the corresponding group of p correlators, to the third inputs of the elements And which the output of the corresponding cyclic shift mask is connected, and the outputs of each n correlators are connected to the corresponding inputs of the adder via the corresponding extremator, the outputs of which are connected to the corresponding inputs of the comparison unit To the gate input of which is connected an additional synchronization block, the second output of which is connected to clock inputs of P1 correlators, the installation inputs of summing counters of which are combined with the clock input of the synchronization block, which is the clock input of the device, the clock input of which is the clock input of the block synchronization, the clock input and the second output of which through the OR element are connected to the clock input of the cyclic shift unit, and the output of the first element This is NOT connected to the second input of an AND element, the output of which is the output of the device clock. Selective comte 6 Monent t Selective combination of 6 moment t 00110001 0011- 10 101000 1 01 1 1 g 1 a.). . . P . I. . . I P P,. P I. . . . I I I I I I I I I I I I I I I I I I I I I I I I I I I /) ./. . Entrance.. d) Entrance. „Rhijfnff J ±: LiiJi-jOinoiy | o | g | / | g | x {xlxlxlxlxlxlxixlxixixixixix x1- e) od mg77Tn gTfixlx | xixix | x x | xlxfxlxlx | xlx | xrx g) 5) (0д Bkiynd () bi (Qd ,,,,,., ,,,., -r-T-1,,.... 1.,,,, g jy. ± lJ i- rxixlxlxlxixl7 xi / ig | gTgTg | f | / HI / l (7lf | gin / lffg1  Bcode ... Bhiicnd u) -g i xixixlxixlxixlxl / m f fiPigi / | g | I HIPtg | yi / l  Login fihfjffj / Kj 1 1 i 1 1 i Code .г.3