RU2116665C1 - Unit of microprogram system - Google Patents

Abstract

FIELD: automation and computer engineering, in particular, design of distributed microprogram control systems which implement parallel information processing algorithms. SUBSTANCE: device has microprogram memory unit, generator of microinstruction address, microinstruction register, N branch-control registers, control flip-flop, two clock oscillators, access and request counters, comparison circuit, access and request decoders, two groups of N units of three-state elements, group of N NOR gates, three groups of N AND gates, three OR gates, group of N delay gates, univibrator, generator of membership feature, delay counter, four flip-flops, two units of three-state elements, NOR gate, thirteen AND gates, four delay gates. EFFECT: increased speed. 2 cl, 5 dwg

Description

 The invention relates to the field of automation and digital computing and can be used to build algorithmically distributed microprogram devices for computing and high-performance control systems designed on the basis of the same type of LSI (VLSI) and implementing parallel information processing algorithms.

 A microprogram control device comprising a read-only memory unit, a micro-command address generation unit, a micro-command register, a micro-program start register, a micro-program end register, an address decoder, a control trigger, a pulse generator, four OR elements, a group of N-1 OR elements, an OR element block , five AND elements, two blocks of AND elements, a delay element, a microprogram end trigger, a microprogram start trigger, five one-shots, an N-1 switch and an OR-NOT element (A.S. N 1168936 USSR, class G 06 F 9/22 ; publ. 23.07.85, BI N 27).

 The disadvantage of this device is the significant number of external inputs / outputs used to organize interaction with other similar devices (receiving and issuing control transfer addresses), which leads to a sharply limited scalability of the control systems formed on its basis, and therefore the narrow scope of the device.

 Closest to the proposed device in technical essence is a microprogram control device with control, including a read-only memory block, micro-command address generation unit, micro-command register, a group of N write registers (where N is the number of stand-alone microprograms), a counter control switch, a sample counter, a decoder samples, four groups of N bus drivers, a start control unit, a stop control unit, a group of N delay elements, a group of N record switches, a polling counter, d survey interrogator, N + 1 blocks of AND elements, 2N + 1 AND elements, a group of N elements OR NOT, an OR element, an operating mode trigger, a control trigger, a pulse generator (A.S. N 1142832 USSR, class G 06 F 9/22; G 06 F 11/00; publ. 28.02.85, BI N 8).

 The disadvantage of this device is the lack of the ability to poll the status (completed / not completed) of parallel sections of microprograms assigned to other similar devices as part of a multicroprogram control system, and, as a result, a narrow scope of its application.

 An object of the invention is to expand the scope of the device based on the organization of the ability to interrogate the status of other similar devices and synchronize the completion of arbitrary groups of parallel sections of microprograms when the device operates as part of a multi-microprogram control system.

 The technical problem is solved by the fact that the multicroprogram system module containing the microprogram memory block, the micro-command address generation block, the micro-command register, N control transfer registers, the control trigger, the first clock pulse generator, sampling and polling counters, the first trigger, the sampling and polling decoders, the circuit comparison, the first and second groups of N blocks of tristable elements, a group of N elements OR NOT, the first and second groups of N elements AND, from the first to third elements AND, from the first to third elements of the IL And, a group of N delay elements, a one-shot, control transfer bus and a synchronization bus of parallel sections, with the direct output of the control trigger connected to the control input of the first clock pulse generator, the first and second information inputs of the micro-command address generation unit are respectively inputs of logical conditions and operation code module, the information output of the micro-command address generation unit is connected to the address input of the microprogram memory unit, the output of which is connected to the information input ohms of the micro-command register, the outputs of the address and logical condition code of which are connected to the third information and control inputs of the micro-command address generation unit, respectively, the micro-operation output of the micro-command register is the micro-operation output of the module, the output of the sample counter is connected to the input of the sample decoder, the outputs from the first to the Nth of which connected to the first inputs of the AND elements of the first group from the first to the Nth respectively, the outputs of which are connected to the synchronization inputs of the control transfer registers from the first on the Nth, respectively, the direct outputs of which are connected to the information inputs of the blocks of tristable elements of the first group from the first to the Nth, respectively, the outputs of which are connected to the control bus, which is connected to the information inputs of the blocks of the tristable elements of the second group from the first to the Nth the outputs of which are connected to the inputs of the elements of the OR-NOT group from the first to the Nth, respectively, the output of the Nth element of the OR-NOT groups is connected to the first input of the first element And, the output of which is connected to the counting input of the counter CA, the output of which is connected to the input of the polling decoder, the outputs from the first to the Nth of which are connected to the first inputs of the elements And of the second group from the first to the Nth, respectively, the outputs of which are connected to the control inputs of the blocks of tristable elements of the first and second groups from the first to Nth, respectively, as well as the inputs of the delay elements of the group from the first to the Nth, respectively, the outputs of which are connected to the reset inputs of the control transfer registers from the first to the Nth, respectively, the outputs of the elements OR NOT of the group from the first to the Nth are connected to the second inputs of the AND elements of the second group, from the first to the Nth, respectively, the first input, the second input and the output of the first OR element are connected to the control input of the module, the output of the second AND element and the reset trigger input, respectively, additionally includes an attribute indicator driver, a second generator clock pulses, latency counter, second, third and fourth triggers, first and second blocks of tristable elements, a third group of N elements AND, an OR-NOT element, an AND-NOT element, from the fourth to thirteen And elements, from the first to the fourth delay elements, the status line of parallel sections, and the output of the control transfer / initialization register of micro command registers is connected to the first inputs of the third and fourth And elements, the outputs of which are connected to the reset input and the counting input of the sample counter, respectively, the output of control information microcommand register is connected to the first input of the comparison circuit, to the information input of the first block of tristable elements and to the information inputs of control transfer registers with first in the Nth direction, the inverse outputs of which are connected to the inputs of the elements of the third group I from the first to the Nth, respectively, the status output of the micro-command register is connected to the first input of the fifth element And, the output of which is connected to the input of the one-shot, the output of which is connected to the input of the first element the delay and the installation input of the second trigger, the inverse output of which is connected to the control input of the second block of tristable elements, the direct output of the second trigger is connected to the control input of the first block of tristable elements, output which is connected to the synchronization bus of parallel sections, which is connected to the information input of the second block of tristable elements, the output of which is connected to the inputs of the OR-NOT element, the address input of the membership attribute generator and to the second input of the comparison circuit, the first and second outputs of the first clock generator are connected to the first inputs of the sixth and seventh elements AND, the output of the sixth element AND is connected to the synchronization input of the micro-command address generation unit, the fourth information input of which o connected to the control bus, the output of the seventh element And is connected to the synchronization input of the micro command register and to the input of the second delay element, the output of which is connected to the second input of the third AND element, the inverse output of the second trigger is connected to the first input of the AND gate, the second input of which connected to the output of the shaper of an attribute of ownership, the output of the AND-NOT element is connected to the first input of the second OR element, the output of which is connected to the status line of parallel sections, the output of the first delay element is connected inen with a counting input of the second trigger, as well as with the first inputs of the eighth and ninth AND elements, the second inputs of which are connected to the status line of parallel sections, the outputs of the eighth and ninth AND elements are connected respectively to the installation input of the first trigger and the first input of the third OR element, direct output the first trigger is connected to the control input of the second clock generator, the output of which is connected to the counting input of the timeout counter, the output of which is connected to the inputs of the tenth element And, the output which is connected to the reset inputs of the first trigger and the latency counter, the outputs of the And elements of the third group from the first to the Nth are connected to the third input of the third And element, the third output of the first clock generator is connected to the second input of the fourth And element, the first input of the eleventh element And and with the input of the third delay element, the output of which is connected to the second inputs of the element And of the first group from the first to the Nth, the second input of the first element And and the input of the fourth delay element, the output of which is connected to the input of the twelfth element And, the second input and output of which is connected to the Nth output of the polling decoder and the reset input of the polling counter, respectively, the output of the mark of the end of the micro-register register section is connected to the first input of the thirteenth And, the second input of which is connected to the output of the second delay element , the output of the thirteenth element And is connected to the counting input of the third trigger, the direct output of which is connected to the second inputs of the sixth and seventh elements And, the inverse output of the third trigger is connected to the second input of the fifth of the And element, the third, fourth, and fifth inputs of which are connected respectively with the inverse output of the fourth trigger, the inverse output of the first trigger, and the output of the OR-NOT element, the output of the comparison circuit is connected to the second input of the second OR element, the output of the label mark of the micro-register of the microcommands is connected to the output of the end of the module firmware and with the first input of the second AND element, the second input of which is connected to the third output of the first clock pulse generator, the control output of the micro-command address generation unit It is connected to the installation input of the control trigger and to the second input of the third OR element, the output of which is connected to the installation input of the fourth trigger, the direct output of which is connected to the second input of the eleventh element AND, the output of which is connected to the installation input of the third trigger and the counting input of the fourth trigger, and in a micro command address generation unit including a start address encoder, a multiplexer, a first block of OR elements, a first OR element and a micro command address register, wherein the input of the start address encoder is is the fourth information input of the micro-command address generation unit, the control and information inputs of the multiplexer are respectively the control and first information inputs of the micro-command address formation unit, n-1 high-order bits of the third information input (where n is the bit capacity of the micro-command address) are connected to n-1 high-order bits the first input of the first block of OR elements, and the least significant bit is connected to the first input of the first OR element, the second input and output of which are connected respectively to the output the multiplexer’s house and the low-order bit of the first input of the first block of OR elements, the synchronization input of the micro command address register is connected to the synchronization input of the micro command address generation block, and the output is the information output of the micro command address generation block, the second block of OR elements, the second OR element, the register and the one-shot are introduced wherein the second information input of the micro-instruction address generating unit is connected to the first input of the second OR element and the first input of the second block of OR elements, the course of which is connected to the information input of the register, the reset input of which is connected to the synchronization input of the micro-command address generation unit, and the output is connected to the second input of the first block of OR elements, the output of which is connected to the information input of the micro-command address register, the output address encoder output is connected to the second input of the second block of OR elements and the second input of the second OR element, the output of which is connected to the input of a single-vibrator, the output of which is connected to the register synchronization input and the control output row block forming microinstruction addresses.

 The essence of the invention is as follows.

 The proposed module, together with other similar devices, forms a multi-microprogram system (MMS), which is intended for the implementation of complex microprogram complexes that provide for both sequential and parallel execution of various microcommands, forming respectively sequential and parallel sections. Each module implements a subset of parallel and sequential sections allocated during the partition (decomposition) of the original microprogram complex.

 During the execution of certain sections of microprograms, the system modules can exchange control information through the corresponding information buses and launch parallel or serial sections assigned to other modules, as well as interrogate the MMS modules in order to determine the status of parallel sections implemented by them. Along with the initialization of sections of microprograms (main microprograms), the MMSM modules, similarly to the prototype, can issue tasks for executing stand-alone microprograms, standard microprograms, and also initiate the transfer of the results of their implementation, while, unlike the prototype, bus systems are used only for transmitting control messages, while how data between operating devices is transmitted via its own data bus (or through its own communication subsystem) of the managed system (object).

 To identify the sections of microprograms at their launch, special features (codes) are used that are assigned in such a way that sections (sections that open with a single parallelization vertex) that are initialized in accordance with the algorithm receive the same signs, and signs of sections of the microprograms belonging to different vertices (microcommands) a) parallelization are different. Similar features are used to identify stand-alone microprograms and standard microprograms, however, in the future, to simplify the description between stand-alone microprograms, standard microprograms, and sections of microprograms, conditionally no differences are made.

 The procedure for parallel sections is as follows.

The module M _i , which initiates the start, generates and issues on the MMPS bus (control transfer bus) a sign code of initialized parallel sections P _s . This code is simultaneously perceived by all other IMF modules and, if a module with the attribute П _{s is} assigned to some module M _j , j ≠ i, then, in accordance with the code П _{s, the} j-th module forms the address of the beginning of this section А _js (А _beg ) and starts the firmware from address A _js , otherwise the module M _{j is} not started.

 Unlike the prototype, where there is no possibility of synchronization of the completion of various groups of parallel sections, the proposed module, during the implementation of the microprogram section assigned to it, can interrogate the state of other modules and proceed to the execution of certain microcommands only after completion of the required parallel sections. To realize the possibility of synchronizing parallel sections (branches of the parallel algorithm), all the merging points of various groups of parallel sections (synchronization points) are labeled with numbers 1, 2, ..., R, where R is the number of synchronization points of parallel sections in all the firmware implemented by the system (it is assumed that the indicated numbers and the above-mentioned features of the sites do not match). A special field is included in the format of the microcommands implemented by the device, in which the code of the synchronization point number (NTS) is fixed, which closes the corresponding section of the firmware. This field is filled only if the corresponding microcommand is the last in the realizable section, and this section is parallel (otherwise the contents of the field in question is zero).

 Synchronization of the end of parallel sections is as follows.

IMPS modules after the execution of the corresponding parallel sections of the firmware go into standby mode. One of the indicated modules (for example, М _i ), considered to be the leader, issues the NTS code Т _r to the system bus (synchronization bus for parallel sections), closing the executed and interrogated sections. This code goes to the inputs of all other modules and generates status signals at their outputs. The signal S _{k of the} module M _k , k ≠ i, is generated according to the following rule.

1. The state signal S _k acquires a zero value if a section ending in the synchronization point T _{r is} assigned to the k-th module, but this section is not completed.

2. The state signal S _k takes a single value if the kth module is secured by a section that is closed by the point T _r , and, in addition, this section is completed, or the section ending by the point T _r and assigned to the kth module does not exist .

The status signal of the master module S _i is single.

The state signals from the outputs of the MIMS modules are transmitted to the common status line of parallel sections and form a signal of a generalized state Z. If at least one of the required parallel sections is not completed (ie, for some module M _t - S _t = "0"), then Z = "0" takes place, otherwise Z takes on a single value. The module M _i (master) interrogates the state of the signal level Z on the status line of parallel sections and for Z = "0" for some time T releases the MMS bus, after which it re-polls the status of parallel sections, and when Z = "1" leaves standby mode and resumes the execution of the firmware.

 In FIG. 1 is a functional diagram of a module of a multi-microprogram system; in FIG. 2 is a functional block diagram of the formation of the address of microcommands; in FIG. 3 shows the microcommand formats implemented by the device; in FIG. 4 depicts a block diagram of a multi-microprogram system; in FIG. 5 shows the timing diagrams of the operation of the device in the mode of polling the status of parallel sections.

 The multi-microprogram system module (Fig. 1) contains a microprogram memory block 1, a micro-command address generating unit 2, a micro-command register 3, registers 4.1-4. N control transmission, trigger 5 control, the first generator 6 clock pulses, counters 7 samples and 8 polls, decoders 9 samples and 10 polls, circuit 11 comparison, the first trigger 13, the first 16.1-16.N and the second group 17.1-17.N blocks of tristable elements, a group of elements OR NOT 18.1-18. N, the first 19.1-19.N and the second 20.1-20.N of the group of AND elements, the first 22, the second 23 and the third 24 elements AND, the first 25, the second 26 and the third 27 elements OR, the group of delay elements 28.1-28.N, a single vibrator 29, a control transfer bus 49 and a parallel section synchronization bus 50, the direct output of the trigger 5 of the control being connected to the control input of the clock generator 6, the first and second information inputs of the micro-command address generating unit 2 are respectively inputs 52 of the logical conditions and 53 of the module operation code , information output of the block 2 f rmirovaniya microinstruction address connected to the address input of the memory unit 1 firmware whose output is connected to data input register 3 microinstructions, address outputs 3.1 and 3.2. the logical condition code of which is connected to the third information and control inputs of the microcommand address generation block 2, respectively, the output 3.3 of microoperations register 3 of the microcommands is the output of 54 microoperations of the module, the output of the sample counter 7 is connected to the input of the decoder 9, the outputs of which are connected from the first to the Nth to the first inputs of the elements AND 19.1-19.N, respectively, the outputs of which are connected to the synchronization inputs of the registers 4.1-4.N of the control transmission, respectively, the direct outputs of which are connected to information to the input entrances of blocks of tristable elements 16.1-16. N, respectively, the outputs of which are connected to the control transfer bus 49, which is connected to the information inputs of the blocks of tristable elements 17.1-17.N, the outputs of which are connected to the inputs of the elements OR NOT 18.1-18.N, respectively, the output of the element OR NOT 18.N connected to the first input of the And 22 element, the output of which is connected to the counting input of the poll counter 8, the output of which is connected to the input of the poll decoder 10, the first through Nth outputs of which are connected to the first inputs of And 20.1-20 elements. N, respectively, the outputs of which are connected to the control inputs of the blocks of tristable elements 16.1, 17.1; ...; 16.N, 17.N, respectively, as well as with the inputs of delay elements 28.1-28.N, respectively, the outputs of which are connected to the reset inputs of the control transfer registers 4.1-4-N, respectively, the outputs of the elements OR NOT 18.1-18.N are connected to the second inputs of the elements AND 20.1-20.N, respectively, the first input, the second input and the output of the element OR 25 are connected to the control input of the module, the output of the element And 23 and the reset input of the trigger 5 of the control, respectively, as well as additionally included shaper 12 attribute of ownership, the second generator 14 clock pulses, count a timer 15, a third group of elements AND 21.1-21. N, second 30, third 31 and fourth 32 triggers, first 33 and second 34 blocks of tristable elements, element OR NOT 35, element NOT 36, fourth 37, fifth 38, sixth 39.1, seventh 39.2, eighth 40.1, ninth 40.2 , tenth 41, eleventh 42, twelfth 43 and thirteenth 44 elements And, the first 45, second 46, third 47 and fourth 48 delay elements, a line 51 of the status of parallel sections, and the output 3.5 mark transfer control / initialization register 3 microcommands connected to the first inputs elements 24 and 37, the outputs of which are connected to the reset input and the counting input of the midrange sensor 7 of the sample, respectively, the output 3.4 of the control information of the register 3 microcommands is connected to the first input of the comparison circuit 11, to the information input of the block 33 of the tristable elements and to the information inputs of the control registers 4.1-4.N, the inverse outputs of which are connected to the inputs of the elements And 21.1.- 21.N, respectively, the output 3.6 of the status of the register of 3 microcommands is connected to the first input of the AND element 38, the output of which is connected to the input of the single-shot 29, the output of which is connected to the input of the delay element 45 and the trigger input of the trigger 30, inverted the stroke of which is connected to the control input of the block 34 of the tristable elements, the direct output of the trigger 30 is connected to the control input of the block 33 of the tristable elements, the output of which is connected to the synchronization bus 50 of parallel sections, which is connected to the information input of the block 34 of the tristable elements, the output of which is connected to the inputs of the element OR NOT 35, to the address input of the driver 12 of the sign of belonging and to the second input of the comparison circuit 11, the first and second outputs of the clock generator 6 are connected to the first inputs of the electronic I 39.1 and 39.2, the output of the And 39.1 element is connected to the synchronization input of the micro-command address generating unit 2, the fourth information input of which is connected to the control transfer bus 49, the output of the And 39.2 element is connected to the synchronization input of the micro-command register 3 and with the input of the delay element 46, the output which is connected to the second input of the AND element 24, the inverse output of the trigger 30 is connected to the first input of the AND-NOT 36 element, the second input of which is connected to the output of the shaper 12 of the membership attribute, the output of the AND-NOT 36 element is connected to the first input ohm of the OR element 26, whose output is connected to the parallel sections state line 51, the output of the delay element 45 is connected to the counting input of the trigger 30, as well as to the first inputs of the AND elements 40.1 and 40.2, the second inputs of which are connected to the parallel sections state line 51, the outputs of the elements And 40.1 and 40.2 are connected respectively to the installation input of the trigger 13 and the first input of the OR element 27, the direct output of the trigger 13 is connected to the control input of the clock generator 14, the output of which is connected to the counting input of the latency counter 15, the output of which is connected to the inputs of the And 41 element, the output of which is connected to the reset inputs of the trigger 13 and the standby counter 15, the outputs of the And 21.1-21.N elements are connected to the third input of the And 24 element, the third output of the clock pulse generator 6 is connected to the second input of the element And 37, the first input of the element And 42 and with the input of the element 47 of the delay, the output of which is connected to the second inputs of the elements And 19.1-19. N, to the second input of AND element 22 and to the input of the delay element 48, the output of which is connected to the first input of AND element 43, whose second input and output are connected to the Nth output of the polling decoder 10 and to the reset input of the polling counter 8, respectively, output 3.7 marks the end of the register portion 3 of the microcommands is connected to the first input of the And 44 element, the second input of which is connected to the output of the delay element 46, the output of And 44 is connected to the counting input of the trigger 31, the direct output of which is connected to the second inputs of And 39.1 and 39.2, the inverse trigger output 31 connection nen with the second input of the AND 38 element, the third, fourth and fifth inputs of which are connected respectively with the inverse output of the trigger 32, the inverse output of the trigger 13 and the output of the OR-NOT 35 element, the output of the comparison circuit 11 is connected to the second input of the OR element 26, output 3.8 the marks of the end of the microprogram register 3 micro-commands are connected to the output 55 of the end of the firmware of the module and to the first input of the And 23 element, the second input of which is connected to the third output of the clock generator 6, the control output of the micro-address formation unit 2 n to the installation input of the trigger 5 of the control and to the second input of the OR element 27, the output of which is connected to the installation input of the trigger 32, the direct output of which is connected to the second input of the And 42 element, the output of which is connected to the installation input of the trigger 31 and the counting input of the trigger 32.

 The micro-command address generating unit 2 (FIG. 2) includes a start address encoder 56, a multiplexer 57, a first 58 and a second 59 blocks of OR elements, a first OR element 60, a micro-command address register 61, a register 62, a one-shot 63 and a second OR element 64, the input of the encoder 56 is the fourth information input of the micro-command address generating unit, the control and information inputs of the multiplexer 57 are the control and first information inputs of the micro-command address generating unit, n-1 senior bits of the third information the input of which (where n is the bit depth of the address of the microcommand) is connected to n-1 by the highest bits of the first input of the block of 58 OR elements, and the least significant bit is connected to the first input of the OR element 60, the second input and output of which are connected respectively to the output of multiplexer 57 and the least significant bit the first input of the OR element block 58, the synchronization input of the register 61 is connected to the synchronization input of the micro-command address generating unit, and the output is the information output of the micro-command address generating unit, the second information input which is connected to the first input of the OR element 64 and the first input of the block 59 of the OR elements, the output of which is connected to the information input of the register 62, the reset input of which is connected to the synchronization input of the unit for generating the micro-command address, and the output is connected to the second input of the block of OR elements 58, the output of which connected to the information input of the register 61, the output of the encoder 56 is connected to the second input of the block 59 of the OR elements and the second input of the element OR 64, the output of which is connected to the input of the one-shot 63, the output of which is connected to the sync input lowering the register 62 and the control output of the micro-command address generating unit.

 The purpose of the elements of the module multimedia system (figure 1) is as follows.

 The microprogram memory unit 1 (BMP) serves for the permanent storage and issuance of microcommands included in various sections of microprograms assigned to this module.

 The register 3 microcommands is intended for receiving and fixing microcommands coming from the output of block 1, for the time of their analysis or processing.

 Registers 4.1-4. N control transmissions are intended for receiving, temporarily storing and issuing feature codes of microprogram sections during control transfer or initialization of other similar modules of the control system.

The generator 6 clock pulses is used to form three shifted relative to each other pulse sequences t ₁ , t ₂ , t ₃ that synchronize the operation of various elements of the device.

 The counter 7 samples, the decoder 9 samples and the elements And 19.1-19.N are designed to control the recording of signs of sections of microprograms in registers 4.1-4. N, and the elements And 24 and 37 are used to form control pulses of the counter 7 of the sample.

 Poll counter 8, polling decoder 10 are designed to control the reading of information and organize cyclic polling of registers 4.1-4.N, and blocks 16.1-16. N tristable elements are used to transmit information (feature codes of microprogram sections) from the outputs of the registers 4.1-4.N, respectively, to the control transfer bus 49.

 The control transfer buses 49 and synchronization parallel sections 50 are used for transmitting feature codes of microprogram sections and NTS codes, respectively, while transferring control and polling the status of parallel sections, respectively, and line 51 is used to generate a generalized signal Z of the polled parallel sections.

 Blocks 17.1-17. N tristable elements in conjunction with the elements OR NOT 18.1-18. N respectively serve to generate signals characterizing the state of the bus 49, the elements And 20.1-20.N are designed to generate signals that are simultaneously control signals of blocks 16.1-16.N, 17.1-17. N tristable elements, respectively, and reset signals of the registers 4.1-4. N, respectively, and elements 28.1-28. N are used to delay the arrival of reset signals of the registers 4.1-4.N, respectively, at the time of issuing the information to the control transfer bus 49.

The element And 22 is designed to control the counting process of the counter 8 polling depending on the current state of the bus 49, and the elements And 43 and delays 48 are used to generate a reset signal of the counter 8 at the end of the next cycle of polling (the appearance of a single signal at the N-th output of the decoder 10) , while the element 48 prevents the reset of the counter 8 immediately after it switches to the state "11 ... 1" and the excitation of a single signal at the Nth output of the decoder 10, shifting the reset pulse t ₃ at the time of issuing information from the register 4.N by tire 49.

 The trigger 5 in combination with the element And 23 and the element OR 25 serves to control the operation of the generator 6.

Triggers 31 and 32, together with AND 44, 42, 39.1, 39.2, OR 27 and delay 46, are used to block the supply of pulses t ₁ and t ₂ to the synchronization inputs of block 2 and register 3 of micro-commands when the module is operating in the parallel state polling mode plots and in a state of waiting for the transfer of control from another similar device; wherein the OR element 27 provides a combination of trigger signals that occur when the control is transferred to the current module or the polling of the status of parallel sections is completed, the And 42 element generates a switch signal to the single state of the trigger 31, and the delay element 46 is inserted to prevent the trigger 31 from switching again at the moment of disappearance a single signal at the output of 3.7 marks the end of the section of the register 3 and the pulse delay t ₂ at the time of establishing a single signal at the output of 3.5 register 3.

 Block 34 of the tristable elements is designed to transmit information (NTS codes) from the bus 50 to the inputs of the shaper 12 of the membership attribute, the OR-NOT 35 element and the comparison circuit 11.

 The element OR-NOT 35 is used to generate a signal state bus 50 synchronization of parallel sections.

 Block 33 of tristable elements provides the transfer of NTS codes from the output of 3.4 register 3 to bus 50 when the module is in the polling state of parallel sections.

 Element And 38 in combination with a single-shot 29 is designed to generate an impulse p to initialize the polling cycle of the state of parallel sections.

 The trigger 30 is used to control the reception (issuance) of control information from the bus (to the bus) 50 through the block 34 (33) of the tristable elements, respectively.

Схема 11 сравнения введена для сопоставления кода НТС Tr, поступающего с шины 50, с кодом НТС Ts, соответствующим точке синхронизации, которая закрывает параллельный участок, выполненный текущим модулем.The membership attribute generator 12 is executed in the form of an EPROM with Qx1 bits organization (where Q is the number of different synchronization points that end the microprogram sections assigned to the current module) and is designed to convert the STC code Tr coming from the bus 50 into a one-bit attribute D, determined in the following way:

A comparison circuit 11 is introduced to match the TCV code Tr coming from the bus 50 with the TCV code Ts corresponding to a synchronization point that closes the parallel section made by the current module.

 The OR element 26 is used to generate a Si state signal of the current module. The OR element 26 has an output stage with an "open" collector, the load for which is the external resistance R (Fig. 1).

 The AND-NOT 36 element provides the formation of a signal — a mask, which blocks the signal transmission from the output of the comparison circuit 11 to the state line 51 of parallel sections.

 Element 45 is designed to delay the supply of the pulse p from the output of the single-shot 29 to the counting input of the trigger 30 and the inputs of the elements And 40.1 and 40.2 at the time of generating the signal of the generalized state Z on line 51 when the module is operating in the mode of polling the state of parallel sections.

 The generator 14, trigger 13, the latency counter 15 and the And 41 element are designed to count the time T between two adjacent polling cycles of the state of parallel sections, while the trigger 13 is used to control the start of the generator 14 and block the And 38 element, and the And 41 element is used to the formation of the signal "Timeout", which is the reset signal of the trigger 13 and the counter 15 and marking the end of the required time interval T.

 Elements And 40.1 and 40.2 are used to generate signals for starting the process of counting the waiting time T and initialize the current module after completion of all the required parallel sections, respectively.

 The purpose of the elements of block 2 of the formation of the address of microcommands (Fig. 2) is as follows.

 The encoder 56 is used to generate the starting address of the parallel or sequential section of the firmware in block 1 when transferring control to this module.

 Multiplexer 57 is designed to generate the value of the interrogated logical condition.

 Register 61 is used to receive, store and issue the executive address of the next microcommand.

Register 62 is entered for preliminary recording of module initialization addresses (operation codes) and eliminates the need for long-term recording of information on the third and fourth information inputs of block 2 until the first clock pulse t ₁ appears at the output of generator 6.

 The OR 60 element is intended to modify the value of the least significant bit of the address of the next microcommand at the branch points of the firmware.

 Block 59 elements OR provides a combination of the initialization addresses of the module coming from the input 53 of the operation code of the module and the output of the encoder 56, and the transfer of addresses to the input of the register 62.

 Block 58 elements OR provides a combination of initialization addresses and the addresses of the next microcommands, respectively, received from the output of the register 62 and the third information input of block 2, and the transfer of addresses to the input of the register 61.

 The OR element 64 is used to generate a signal indicating the appearance of the initialization address at the output of the encoder 56 or the operation code at the input 53 of the module.

 The one-shot 63 is designed to generate a start pulse for the current module when an address appears on the output of the encoder 56 or an operation code at the input 53 of the module.

The operation of the proposed device (conventionally referred to as M _i ) will be considered by the example of the functioning of the MMS, consisting of many identical modules and implementing the microprogram of a complex parallel control algorithm.

 Initially, all the registers, triggers and counters (Fig. 1, 2), with the exception of counter 8, set to "11 ... 1", are in a state of logical zero, so the generators 6 and 14 are turned off, at all outputs of the decoder 9 samples there is a zero signal level, at the outputs of the polling decoder 10 there is a code "100 ... 0", and the elements of blocks 16.1-16.N-1 and 33 are in a high impedance state ("off") (initial setup circuit in Fig. 1 , 2 conditionally not shown). In the cells of block 1 with nonzero addresses, microcommands are written that make up the sections of microprograms assigned to the module under consideration. On buses 49 and 50 there is zero, and on line 51 - a single signal level.

The operation of the IMPS begins from the moment of input to the input 53 of one of its modules (for example, module M _i ) of the code of the operation to be performed (Fig. 1). The operation code (CPC), which is the start address of the corresponding firmware (address of the initial sequential section), from input 53 is supplied (Fig. 2) to the first inputs of the OR element 64 and the block of OR elements 59. Since the CPC contains at least one unit, the output of the element 64 there is a positive difference in signal level, which acts on the single-shot 63 and excites the pulse "Start" at its output. At the same time, the CPC passes through block 59, at the second input of which there is a zero code, due to the lack of information on the bus 49, and is installed on the information input of the register 62. The pulse from the output of the single-vibrator 63 is fed to the synchronization input of the register 62 and records a trailing edge (slice) in it Received CPC. The CPC from the output of the register 62 through the block of elements OR 58 (at the first input of which there is a zero code, due to the zero state of register 3) passes to the information input of the register 61 of the address of microcommands.

At the same time, the pulse from the output of the one-shot 63 is supplied (Fig. 1) to the input of the trigger 5 installation, and also through the OR element 27 to the input of the trigger 32 installation and switches these triggers to a single state. A single signal from the direct output of the trigger 32 opens the And 42 element, and a single signal from the direct output of the trigger 5 is fed to the control input of the generator 6 and allows the formation of pulse sequences t ₁ , t ₂ and t ₃ at its outputs.

Since the trigger 31 is in the initial (zero) state and the zero signal from its direct output blocks the elements AND 39.1, 39.2, the first pulses t ₁ and t ₂ from the first and second outputs of the generator 6, respectively, do not pass to the outputs of the elements 39.1 and 39.2. In turn, the pulse t ₃ from the third output of the generator 6 through the open element 42 is fed to the input of the installation of the trigger 31 and puts it in the state of the logical unit. A single signal from the direct output of the trigger 31 opens the elements 39.1 and 39.2, and a zero signal from the inverse output blocks the And 38 element, thereby preventing the operation of the one-shot 29. In addition, the pulse t ₃ from the output of the element 42 goes to the counting input of the trigger 32 and returns with a cut its in a state of logical zero.

At the same time, the pulse from the third output of the generator 6 is transmitted to the input of the delay element 47 and then to the second input of the AND element 22 and the input of the delay element 48. If at the first input of element 22 there is a single signal, then the pulse t ₃ enters the counting input of the counter 8 and switches it to the zero state, otherwise the transmission of the pulse t ₃ to the counting input of the counter does not occur and the state of the latter does not change. The pulse t ₃ from the output of the element 48 after a certain time arrives at the first input of the element And 43 and if the counter 8 is still in the state "11 ... 1" and at the N-th output of the decoder 10 there is a single signal, respectively, passes through the element 43 to the counter reset input 8 and puts it in the state "00 ... 0". Otherwise, the counter 8 is already set to "00 ... 0", at all outputs of the decoder 10 there is a zero signal level and the pulse does not pass through the element 43.

Thus, the first pulse t ₃ switches the counter 8 to the state "00 ... 0" and generates a zero signal level at the outputs of the decoder 10, thereby blocking the elements And 20.1-20.N.

The second clock pulse of the sequence t ₁ from the first output of the generator 6 through the open element And 39.1 is transmitted to the synchronization input of block 2 (Fig. 2) and, coming further to the synchronization input of register 61, the front captures the CPC previously installed on its information input, initiating the process of reading the first microcommand. At the same time, the pulse t ₁ enters the reset input of the register 62 and returns it to the zero state; at the output of register 62, a null code appears. The CPC from the output of the register 61 is fed to the address input of the BPMP 1 (Fig. 1) and forms at its output the first micro-command of the realized microprogram section (the initial sequential section of the realized microprogram). From the output of block 1, this microcommand is fed to the information input of register 3. The next clock pulse t ₂ passes through the open element 39.2 to the synchronization input of register 3 and fixes a micro-command read from block 1 in it.

 Further, depending on the format of the read micro command (Fig. 3), the device may function in one of the following modes; executing an operating micro-command (mode A), transferring control to other (different) similar devices of the system, or initializing parallel sections (mode B) and synchronizing the completion of parallel sections of the firmware (mode C).

 Consider the operation of the device in each of the listed modes.

Mode A. The operation of the device in mode A starts from the moment the microcommands of format A or Ak are fixed in register 3 (Fig. 3b, c). Initially, assume that the read micro-command has the format A (Fig. 3b). At the outputs 3.4-3.8 of register 3, logical zero signals are set; at outputs 3.1 and 3.2, the address of the next microcommand (A _sl ) and the code of the interrogated logical condition (LU) (which, in particular, can be zero) appear respectively, and at output 3.3, the operational part of the microcommand is formed containing information about the work initiated in this cycle microoperation devices.

 The operational part (OCH) of the microcommand from the output 3.3 of register 3 is transmitted to the output 54 of the module and initiates the required microoperations (MO). The zero signal from the output of 3.5 register 3 blocks the elements And 24 and 37; the zero signal from the output of 3.6 register 3 generates a zero signal level at the output of the And 38 element; the zero signal from the output of 3.7 register 3 blocks the element And 44, thereby preventing the zeroing of the trigger 31; a logic zero signal from the output 3.8 of register 3 blocks the element And 23, preventing the trigger 5 of the control.

 At the same time, the address of the next microcommand and the code of the interrogated logical condition from the outputs 3.1 and 3.2 of register 3, respectively, go to the third information and control inputs of block 2 (Fig. 2). The logical condition code is then fed to the control input of the multiplexer 57 and ensures the transmission of the value of the interrogated logical condition from the input 52 of the module to its output. The older part of the address of the next microcommand from the third information input of block 2 through the OR block 58, at the second input of which there is a zero code from the output of register 62, passes to the information input of register 61, and the least significant bit (which is modifiable and can change at the branch points of the firmware ) arrives at the first input of the OR element 60.

 If the interrogated logical condition is true, then at the output of the multiplexer 57 there is a single signal, which is fed to the second input of the OR element 60 and, passing to its output, changes the value of the least significant bit of the address to one. If the interrogated logical condition is false or the logical condition code is zero, the signal level 0 is stored at the output of multiplexer 57 and the initial value of the least significant bit of the address is transmitted to the output of element 60. The least significant bit of the address from the output of element 60 through the corresponding OR element of block 58 is transmitted to the information input of the register 61. Thus, at the information input of the register 61, the executive address of the next microcommand of the implemented firmware section appears, taking into account the value of the required logical condition.

The next clock pulse t ₁ (Fig. 1) passes through the And 39.1 element to the synchronization input of block 2 (Fig. 2) and, passing on to the synchronization input of the register 61, ensures reception of the executive address of the next microcommand. The same pulse confirms the zero state of the register 62. The address of the next microcommand from the output of the register 61 is supplied (Fig. 1) to the address input of block 1 and provides the reading of the next microcommand. The read micro command from the output of block 1 is fed to the information input of register 3 and is written to this register along the edge of the next pulse t ₂ coming through element 39.2 from the output of the generator 6. Next, the module proceeds to execute the read micro command. The progress of the next micro-command is similar to the progress of the implementation of the previous micro-command.

If the read micro-command has the format A _k (Fig. 3c), then at outputs 3.1-3.7 of register 3 a zero signal level is formed, and at output 3.8 a single signal appears - the end mark of the implemented firmware (M _kmp ). Label M _kmp enters the output 55 of the end of the module firmware and indicates the completion of the current operation and the readiness of the system to implement another. At the same time, the same label opens the element And 23. The pulse t ₃ from the third output of the generator 6 passes through the element And 23, the element OR 25 and is fed to the reset input of trigger 5, switching it to the zero state. The zero signal from the direct output of the trigger 5 blocks the operation of the generator 6; Thus, the current module (and the system as a whole) finishes executing the final sequential section of the microprogram and enters the standby state of the job for the implementation of the next microprogram (operation). Before starting the next operation, the elements of the device are reset to their initial state, after which the CPC is fed to the input 53 of the corresponding module and the system proceeds to implement the next microprogram. The transition of the module to the passive state can also be carried out by applying the Stop signal to the first input of the OR element 25.

Mode B. The transition of the device to operating mode B occurs after writing to the register 3 microcommands of format B (Fig. 3d). The current module M _i enters the initialization mode of the group P of parallel sections of the microprogram assigned to other similar modules of the control system. Logic zero signals appear at the outputs 3.6-3.8 of register 3, at the outputs 3.1 and 3.2 the address of the next microcommand and the code of the logical condition are generated, and at the output 3.3, either a zero code or a nonzero code that defines the microoperations being performed is generated.

The zero signal from the output 3.6 of register 3 blocks the And 38 element, preventing the operation of the single-shot 29; a zero signal from output 3.7 blocks element 44; zero signal output from the register 3.8 3 closes the AND gate 23. Simultaneously, the output register 3 3.5 unit signal is formed - the transfer of control or an initialization mark (M _ISP), and the output characteristic code installed 3.4 initialized portions firmware (CPU) _Example.

The CPU from the output 3.4 of register 3 is transmitted to the information inputs of the registers 4.1-4.N, and a single label M _{poo is} fed to the inputs of the elements I 24 and 37 and allows the passage of clock pulses that control the operation of the counter 7 of the sample. The code characterizing the current state of the registers 4.1-4.N and generated by the elements And 21.1-21.N, arrives at the third input of the element And 24. The pulse t ₂ from the output of the element And 39.2 through the element 46 goes to the second input of the element And 24 and, if the state of the registers 4.1-4.N is zero and, therefore, the code "11 ... 1" is present at the third input of element 24, passes through element 24 to the reset input of counter 7 and switches it to the zero state (confirms its initial state). The zero code from the output of the counter 7 is fed to the input of the decoder 9 and generates a zero signal level at its outputs, thereby providing blocking of the AND 19.1-19.N elements. If the state of at least one of the registers 4.1-4.N is different from zero, the "non-unity" code is set at the outputs of the elements AND 21.1-21.N and the state of the counter 7 does not change when the pulse t ₂ arrives.

The next pulse t ₃ from the third output of the generator 6 through the element And 37 passes to the counting input of the counter 7 and the front increases its content by one. The resulting code ("00 ... 01") from the output of the counter 7 is transmitted to the input of the decoder 9 and excites its k-th (first) output. A single signal from the k-th (first) output of the decoder 9 opens the element And 19.k (19.1). The pulse t ₃ passing through the delay element 47 is fed to the second input of the AND element 22, at the first input of which a signal is generated, determined by the state of the bus 49 and formed by the OR-NOT 18.N element. If there is no information on bus 49, then the zero code from bus 49 through the open block 17.N is fed to the inputs of element 18. N and generates a logical unit signal at its output. This signal is fed to the first input of the element And 22, the pulse t ₃ passes to the output of the element 22 and the front increases the contents of the counter 8 by one. The code from the output of the counter 8 is fed to the input of the decoder 10 and excites its i-th output. If the bus 49 is busy, then at the output of the element 18.N a zero signal is set, which blocks the element 22 and does not allow the passage of the pulse t ₃ to the counting input of the counter 8.

At the same time, the pulse t ₃ from the output of element 47, being delayed for a time sufficient to generate the next code at the outputs of counters 7 and 8, is fed to the inputs of the elements And 19.1-19.N, as well as to the input of element 48. Since the unit the signal is present only at the k-th (first) output of the decoder 9, the pulse t ₃ passes through the element 19.k (19.1) and the front fixes the code П _р in the register 4.k (4.1).

A single signal from the i-th output of the decoder 10 is fed to the first input of the element And 20.i and if the bus 49 is free and to the second input of the element 20. i a single signal from the output of the element 18.i is transmitted to the output of the element 20. i. A single signal from the output of element 20.i is supplied to the control inputs of blocks 16. i and 17.i and ensures the transfer of information (code of a feature indicator or a zero code) from the direct output of register 4.i (in the general case, i ≠ k) to bus 49 At the same time, the signal from the output of the element 20.i transfers the elements of the block 17.i to the high-impedance state, thereby disabling the second input of the element 20.i and causing the operation of this element in the unconditional transmission of the signal from its first input to the output. At the same time, a single signal from the output of the element 20.i goes to the input of the element 28.i, with a given time shift appears on its output and performs a reset of register 4. i. If i = N, i.e. the information was read from the register 4.N, then a single signal from the Nth output of the decoder 10 opens the element 43 and therefore the pulse t ₃ from the output of the element 48 passes through the element 43 to the reset input of the counter 8, transfers it to the zero state and thereby initiates the next cycle of polling registers 4.1-4.N.

Simultaneously with the issuance of the bus 49 _EXAMPLE code address of the next microinstruction code and outputs a logical condition 3.1 and 3.2 fed to the register 3 corresponding to the inputs 2 and similar to those previously discussed (mode A) ensuring the formation of the executive next microinstruction address. The device starts reading and executing the next microcommand of the area being sold. If, in accordance with the control algorithm, after the initialization of parallel sections, the current module should go into the standby state, then for the next micro instruction read from the BPMP 1, the format C ₁ or C ₂ should be used (Fig. 3d, f).

 The operation of the module in the mode of reception and analysis of codes codes for sections of firmware is as follows.

Codes of feature plots from the control transfer bus 49 are fed to the fourth information inputs of blocks 2 and are simultaneously analyzed by all modules of the system. The analysis of the code П _{s by the} module М _k is reduced to establishing the fact of the existence of a parallel (sequential) section of the microprogram assigned to this module and possessing the same feature П _s . The code П _s arrives (Fig. 2) at the input of the encoder 56 and, in the case of a section having the attribute П _s , forms the starting address A of the _{beginning of} this section in block 1 at the output of the encoder 56, otherwise a zero code is stored at the output of the encoder 56 .

Address A _starts with the output of the encoder 56 through the block of OR elements 59, at the first input of which a zero code is set, due to the absence of an operation code at the input 53 of the module, resembles the information input of the register 62. At the same time, the same address goes to the input of the OR element 64. If A _beginning = "00 ... 0", then at the output of the element 64 the signal level is kept at zero, otherwise the positive difference in the signal level that occurs at the output of the element 64 acts on the one-shot 63 and generates a pulse at its output. This pulse is transmitted to the synchronization input of the register 62 and fixes the generated address A _{beginning in it} .

The pulse from the output of the one-shot 63, in addition, is supplied (Fig. 1) to the input of the trigger 5 installation and through the OR element 27 to the input of the trigger 32 installation and confirms the single state of the trigger 5, at the same time switching the trigger 32 to the single state. Single the signal from the direct output of trigger 32 opens the And 42 element. The next pulse t ₃ , coming through the And 42 element to the trigger input 31 and the counting input of the trigger 32, switches the first to the state of the logical unit, and the second (cutoff) to the state of logical zero. The zero signal from the output of the trigger 32 blocks the element 42, and a single signal from the direct output of the trigger 31 opens the elements 39.1 and 39.2.

The next pulse t ₁ through the open element And 39.1 is fed to the synchronization input of block 2 and fixes the address A _beginning in register 61 (at the output of block 2). The address A _beginning with the output of block 2 is supplied to the address input of the BPMP 1 and provides the reading of the first microcommand of the initialized section. The module starts to execute a given section of the firmware and then functions similarly to the module when implementing the initial section of the firmware.

Mode C. The operation of the module M _i in mode C begins after fixing in register 3 microcommands of the format C ₁ or C ₂ (Fig. 3d, e). If the read micro-command has the format C ₁ (Fig. 3d), then the module receives the status of the master and proceeds to polling the status of the required parallel sections of the firmware, otherwise the module is considered slave and goes into the standby state, which is identical to the state of the device after transferring control to other similar devices.

Initially, assume that the read micro-command has the format C ₂ (Fig. 3e).

At outputs 3.5, 3.6, 3.8, 3.1-3.3 of register 3, a signal level of zero appears, at output 3.7 a unit mark of the end of the parallel section (M _ku ) is formed, and at output 3.4 a code of the synchronization point number (STC) T _{s is formed} , closing the realized parallel firmware section. Zero signals from the outputs 3.5, 3.6 and 3.8 of register 3 block the elements And 24, 37, the element And 38 and the element And 23, respectively; the zero code from output 3.3 goes to the output of 54 microoperations of the module; zero codes from outputs 3.1 and 3.2 are transmitted respectively to the third information and control inputs of block 2; the NTS code T _s is supplied to the first input of the comparison circuit 11, and a single mark M _ku opens the And 44 element. Zero codes received at the third information and control inputs of block 2 (Fig. 2) form a zero signal level at the outputs of multiplexer 57 and the element OR 64 and thereby prepare the current module for a possible subsequent reception of control from another device.

The pulse t ₂ previously received at the input of the delay element 46, through the open element And 44 is supplied to the counting input of the trigger 31 and cut it sets it to zero. The zero signal from the direct output of the trigger 31 blocks the elements 39.1 and 39.2, preventing the passage of clock pulses to their outputs. The selection of microcommands from BPMP 1 is terminated and the device goes into a passive state in which it remains until the transfer of control from another similar device.

Now suppose that the micro command read from block 1 has the format C ₁ (Fig. 3d).

In contrast to the above case, the output of the next microcommand and the code of the interrogated logical condition are generated respectively at outputs 3.1 and 3.2 of register 3, and at output 3.6, a single status signal is generated, which indicates that the current module for the synchronization point T _s is the leading one and controls the synchronization of the required parallel plots. Zero signals from outputs 3.5 and 3.8 of register 3 form a zero signal level at the outputs of elements I 24, 37 and element 23, respectively, and a single mark M _ku opens element I 44. The pulse t ₂ from the output of delay element 46 passes through element 44 and is cut off resets trigger 31 to a logical zero state. The zero signal from the direct output of the trigger 31 blocks the elements 39.1 and 39.2, and a single signal from the inverse output goes to the second input of the And 38 element, to the first input of which a single status signal is supplied, at the third and fourth inputs there are single signals from the inverse outputs of the triggers 32 and 13, respectively, and at the fifth input, a signal is output from the output of the OR-NOT 35 element, determined by the state of the synchronization bus 50 of parallel sections.

 Since the trigger 30 is in the zero state, a single signal from its inverse output is fed to the control input of block 34 and provides information from the bus 50 to its output. The code from the output of block 34 is fed to the inputs of element 35. If information is available on bus 50, the output of element 35 generates a logic zero potential, which blocks AND element 38 and prevents the occurrence of a signal level difference at the input of one-shot 29. As soon as bus 50 is released, the output of the element 35 is set to a signal of a logical unit. A single signal from the output of the element 35 is fed to the fifth input of the element 38 and changes the signal level at its output from zero to unity. The difference in signal level at the output of element 38 acts on a single-shot 29 and excites a pulse p at its output.

 The pulse p from the output of the one-shot 29 switches the trigger 30 to the state of the logical unit and, in addition, is fed to the input of the delay element 45. The zero signal from the inverse output of the trigger 30 goes to the control input of the block 34 and puts the elements of the block 34 into a high impedance state, and a single signal from the direct output of the trigger 30 opens the block 33. At the same time, the zero signal from the inverse output of the trigger 30 goes to the first input of the And NOT 36 and forms a single signal mask at its output. This signal is supplied to the first input of the OR element 26 and thereby blocks the passage of the signal from the output of circuit 11 to line 51. At the output of element 26, a signal of a logical unit is generated; thus, the current module does not affect the state of signal Z on line 51.

At the same time, the TCS code T _s is transmitted via a block 33 to the bus 50 and provides an interrogation of the status of the remaining modules of the system. The survey procedure is as follows.

The NTS code T _s from the bus 50 is fed to the information inputs of the blocks 34 of the IMPS modules and, since the triggers 30 of all the modules, except the trigger 30 of the module M _i , are set to a logical zero state (which is caused by the blocking of the possibility of several modules simultaneously accessing the bus 50) passes to the outputs of blocks 34 and provides the formation of state signals of the modules with respect to the synchronization point T _s . At the same time, the current module does not receive information from bus 50, since at the control input of its block 34 there is a inhibitory (zero) signal from the inverse output of trigger 30.

The formation of the state signal of the module M _u , u ≠ i, is as follows.

The STC code T _s from the output of block 34 is fed to the inputs of element 35, generates a logic zero signal at its output, and thus blocks element 38, preventing the possible start of the process of polling the state of parallel sections when a single status signal occurs at output 3.6 of register 3 (this the situation is not excluded if there are several simultaneously terminated groups of parallel sections). At the same time, the code T _s arrives at the second input of the comparison circuit 11 and is mapped to the NTS code T _p , which is generated at the output 3.4 of register 3 and is present at the first input of the circuit 11. In addition, the code T _s is supplied to the address input of the driver 12.

In the absence of sections of microprograms assigned to the module M _u and ending at the point T _s , a logic zero signal appears at the output of the former 12. This signal is fed to the second input of the AND-NOT 36 element and generates a logical unit signal at its output. A single signal from the output of the element 36 is supplied to the first input of the OR element 26 and sets the unit state signal S _u at its output.

If the current module M _{u is} assigned a parallel section of the microprogram ending in the synchronization point T _s (the state of this section can be arbitrary: “completed”, “started and is underway” or “not started”), then a single unit 12 is formed the signal is a sign of membership D. This signal (sign) is supplied to the second input of the element 36 and sets a logic zero signal at its output. At the first input of element 26, a zero signal level is formed and now the signal level at the output of element 26 (signal S _u ) is determined by the ratio of codes T _s and T _p , i.e. the signal level at the output of the comparison circuit 11.

If the codes T _p and T _{s are} different, i.e. The u-th module did not complete the execution of the microprogram section (in this case, T _p = 0) or performed a section that is not included in the subset of controlled parallel sections, then a zero signal is generated at the output of circuit 11. If the codes T _s and T _p coincide, i.e. Since the module M _u completed a section ending with the required synchronization point T _s , then a single signal is generated at the output of the circuit 11. The signal from the output of circuit 11 through the OR element 26 is transmitted to line 51 and, together with the signals similar in functionality from the outputs of the elements 26 of other IMPS modules, generates a generalized signal Z of the state of parallel sections on line 51 (this signal is generated as a result of the "mounting AND" operation over status signals from the outputs of elements 26 of the system modules).

If at least one of the interrogated parallel sections is not completed, that is, at the output of element 26 of the corresponding module there is a zero signal, the signal from the output of element 26 of the corresponding module is sent to line 51 and determines the zero value of signal Z; otherwise, i.e. when all the required parallel sections are satisfied and the logical unit signals are present at the outputs of the elements 26 of all modules, a logical unit signal is set on line 51 (Z = "1"). The state of the modules executing or completing sections of the firmware that are not included in the subset of sections specified by the code T _s does not affect the value of signal Z, since the outputs of the corresponding AND-NOT 36 elements, and therefore, the OR elements 26, contain a logical unit signal.

The master module M _i, after the time required to generate the state signal of parallel sections Z, polls the state of line 51 and either releases bus 50 and after a certain period of time T (in the presence of incomplete parallel sections and zero signal level Z) again polls the state of parallel sections, or exits the standby state (at the end of the required parallel sections and the presence of a single signal level on line 51) and resumes the execution of the firmware.

 The pulse p, previously generated by the single-shot 29 and delayed by the element 45 for a time dt, sufficient to establish the signal Z on line 51, from the output of the element 45 goes to the counting input of the trigger 30, as well as to the first inputs of the elements And 40.1, 40.2, at the second inputs of which Z signal from line 51 appears.

 1. If Z = "0", ie at least one of the controlled parallel sections is not completed, then the element 40.2 is closed, and the pulse p through the open element 40.1 passes to the input of the installation of the trigger 13 and puts it in the state of the logical unit, thereby initiating the countdown process T. The trigger 31, and accordingly, the trigger 32 remains in a state of logical zero, and the zero signal from the inverse output of the trigger 13 blocks the element 38 and does not allow the single-shot 29 to re-operate. At the same time, by cutting the pulse p from the output of the trigger element 45 Ger 30 is set to zero; the zero signal from the direct output of the trigger 30 puts the block 33 in a high impedance state - the current module releases the synchronization bus 50 of the parallel sections, and a single signal from the inverse output of the trigger 30 opens the element 36 and returns the block 34 to the active state.

 A single signal from the direct output of the trigger 13 includes a generator 14. The pulses from the output of the generator 14 begin to arrive at the counting input of the latency counter 15 and initiate the counting process from "00 ... 0" to "11 ... 1". The code from the output of the counter is fed to the inputs of the element And 41. The next pulse from the output of the generator 14 is supplied to the counting input of the counter 15 and cut it into the next state. If the code at the output of the counter is different from the one, then at the output of the element 41 the zero potential is stored and the counting process continues. When the counter enters the state "11 ... 1" at the output of element 41, a single signal "Timeout" occurs. This signal is fed to the reset inputs of the counter 15 and trigger 13 and puts them in their original (zero) state. Thus, the countdown of the required time interval T is completed. The zero signal from the direct output of the trigger 13 stops the generator 14, and a single signal from the inverse output opens the element And 38.

As soon as the signal at the output of the element 35 acquires a single value (which means the bus 50 is released), at the output of the element 38 a positive difference in the signal level occurs, which acts on the one-shot 29 and again excites the pulse p at its output. The current module M _i again issues on the bus 50 the NTS code T _s and again polls the status of the parallel sections. If after the implementation of this polling cycle the signal Z again assumes a zero value, then after the time T counted by the counter 15, the i-th module again polls the status of parallel sections, etc. The survey is performed until the signal Z takes a single value.

 2. If Z = "1", ie all the polled parallel sections are completed, then the element 40.1 is blocked, and the pulse p passes through the open element 40.2 and the OR element 27 to the input of the installation of the trigger 32 and puts the trigger 32 in a single state. A single signal from the direct output of the trigger 32 opens the And 42 element, and a zero signal from the inverse output blocks the element 38, preventing the single-shot 29 from reacting again. Another clock pulse from the third output of the generator 6 passes through the open element 42 to the installation input of the trigger 31 and switches it into the state of a logical unit.

 A single signal from the direct output of the trigger 31 allows the passage of clock pulses through the elements 39.1 and 39.2, and a zero signal from the inverse output confirms the blocking of the And 38 element. At the same time, the pulse from the output of the element 42 goes to the counting input of the trigger 32 and returns it to the original with a cut state. The zero signal from the direct output of the trigger 32 blocks the element 42. Since the element 38 is blocked by the zero signal from the inverse output of the trigger 31, the appearance of a single signal level at the inverse output of the trigger 32 does not cause a change in the signal level at the output of the element 38, which leads to blocking of the one-shot 29. At that the same time, by cutting off the pulse p from the output of element 45, trigger 30 is set to zero; the zero signal from the direct output of the trigger 30 puts the block 33 in a high impedance state - the current module frees the bus 50, and a single signal from the inverse output of the trigger 30 opens the element 36 and returns the block 34 to the active state.

The pulse t ₁ from the first output of the generator 6 through the open element 39.1 passes to the synchronization input of block 2 and ensures the recording of the executive address of the next microcommand, formed earlier using the contents of fields 3.1 and 3.2 of register 3, in the microcontroller address register 61 (Fig. 2). The formation of the executive address of the next microcommand occurs similarly to the previously considered (see mode A). The address from the output of the register 61 is transmitted to the address input of block 1 (Fig. 1), and the current module M _i resumes the execution of the microprogram, suspended for the duration of synchronization of parallel sections. At the output of block 1, the following microcommand appears. This microcommand arrives at the information input of register 3 and is fixed in register 3 at the moment of the appearance of the pulse front t ₂ at its synchronization input. Further, the operation of the device is no different from its functioning when performing the initial sequential portion of the firmware.

 Thus, the introduction of additional elements into the device and the relationships caused by them can significantly expand its functionality, and therefore the field of expedient application, providing the ability to build on its basis modular multicroprogram systems that implement complex complexes of parallel and serial microprograms, including microprograms, containing a significant number of parallelization and synchronization points of parallel sections. The use of the introduced hardware and algorithmic means for synchronizing parallel sections eliminates the simultaneous execution of incompatible microcommands (sections), which may occur when using the prototype. The maximum number of simultaneously executed and simultaneously initialized or synchronized (i.e. converging to a single synchronization point) sections of the firmware is limited only by the number of modules in the control system.

Claims (2)

 1. A multicomprogram system module containing a microprogram memory block, micro-command address generation block, micro-command register, N control transfer registers, control trigger, first clock pulse generator, sampling and polling counters, first trigger, sampling and polling decoders, comparison circuit, a group of N elements OR - NOT, the first and second groups of N elements AND, from the first to third elements AND, from the first to third elements OR, a group of N delay elements, one-shot, control transfer bus and synchronization bus parallel sections, with the direct output of the control trigger connected to the control input of the first clock pulse generator, the first and second information inputs of the micro-command address generation unit are respectively the inputs of logical conditions and the operation code of the module, the information output of the micro-command address generation unit is connected to the address input of the microprogram memory, the output of which is connected to the information input of the micro-command register, the outputs of the address and logical condition code of which are connected to the information and control inputs of the micro-command address generation unit, respectively, the output of micro-operations of the micro-command register is the output of the micro-operations of the module, the output of the sample counter is connected to the input of the sample decoder, the outputs from the first to the Nth of which are connected to the first inputs of the elements And of the first group from the first to N- respectively, the outputs of which are connected to the synchronization inputs of the control transfer registers from the first to the Nth, respectively, the output of the Nth element OR - NOT of the group is connected to the first input of the first element And, the output of which is connected to the counting input of the polling counter, the output of which is connected to the input of the polling decoder, the first to Nth outputs of which are connected to the first inputs of the And elements of the second group from the first to the Nth, respectively, whose outputs are connected to the inputs of the elements delays of the group from the first to the Nth, respectively, the outputs of which are connected to the reset inputs of the control transfer registers from the first to the Nth, respectively, the outputs of the elements OR - NOT the groups from the first to the Nth are connected to the second inputs of the elements of the second group from the first according to the Nth input, the first input, the second input and the output of the first OR element are connected to the control input of the module, the output of the second AND element and the reset trigger input, respectively, characterized in that the first and second groups of N blocks of tristable elements are introduced, a signifier accessories, a second clock generator, a timeout counter, second, third and fourth triggers, the first and second blocks of tristable elements, the third group of N elements AND, the OR element is NOT, the AND element is NOT, from the fourth o through the thirteenth AND elements, from the first to the fourth delay elements, the status line of parallel sections, the output of the control transfer / initialization register of the micro command register being connected to the first inputs of the third and fourth AND elements, the outputs of which are connected to the reset input and the counting input of the sample counter, respectively the output of the control information of the micro-command register is connected to the first input of the comparison circuit, the information input of the first block of tristable elements and the information inputs of the transfer registers first to Nth circuits, the inverse outputs of which are connected to the inputs of the And elements of the third group from the first to the Nth, respectively, the micro-command register status output is connected to the first input of the fifth And element, the output of which is connected to the input of the one-shot, the output of which is connected to the input the first delay element and the installation input of the second trigger, the inverse output of which is connected to the control input of the second block of tristable elements, the direct output of the second trigger is connected to the control input of the first block of tristable elements NTV, the output of which is connected to the synchronization bus of parallel sections, which is connected to the information input of the second block of tristable elements, the output of which is connected to the inputs of the element OR - NOT, the address input of the membership attribute generator and the second input of the comparison circuit, the first and second outputs of the first clock connected to the first inputs of the sixth and seventh elements And, the output of the sixth element And is connected to the synchronization input of the unit for generating the address of microcommands, the fourth information the stroke of which is connected to the control bus, the output of the seventh element And is connected to the synchronization input of the micro-command register and to the input of the second delay element, the output of which is connected to the second input of the third AND element, the inverse output of the second trigger is connected to the first input of the AND element - NOT, the second input which is connected to the output of the shaper of an attribute of ownership, the output of the AND element is NOT connected to the first input of the second OR element, the output of which is connected to the status line of parallel sections, the output of the first element the delay is connected to the counting input of the second trigger, as well as to the first inputs of the eighth and ninth AND elements, the second inputs of which are connected to the status line of parallel sections, the outputs of the eighth and ninth AND elements are connected respectively to the installation input of the first trigger and the first input of the third OR element, direct the output of the first trigger is connected to the control input of the second clock generator, the output of which is connected to the counting input of the timeout counter, the output of which is connected to the inputs of the tenth ment And, whose output is connected to the reset inputs of the first trigger and the timeout counter, the outputs of the elements of the third group from the first to the Nth are connected to the third input of the third element And, the third output of the first clock generator is connected to the second input of the fourth element And, the first the input of the eleventh element And and the input of the third delay element, the output of which is connected to the second inputs of the elements And of the first group from the first to the Nth, the second input of the first element And the input of the fourth delay element, the output of which is is dined with the first input of the twelfth element And, the second input and output of which is connected to the Nth output of the polling decoder and the reset input of the polling counter, respectively, the output of the mark of the end of the microcommand register section is connected to the first input of the thirteenth element And, the second input of which is connected to the output of the second element delays, the output of the thirteenth element And is connected to the counting input of the third trigger, the direct output of which is connected to the second inputs of the sixth and seventh elements And, the inverse output of the third trigger is connected to the second the fifth element AND, the third, fourth and fifth inputs of which are connected respectively to the inverse output of the fourth trigger, the inverse output of the first trigger and the output of the OR element - NOT, the output of the comparison circuit is connected to the second input of the second OR element, the output of the mark mark of the microprogram register of the microcommands is connected with the output of the end of the module firmware and the first input of the second AND element, the second input of which is connected to the third output of the first clock generator, the control output of the mic address generation unit the command is connected to the installation input of the control trigger and the second input of the third OR element, the output of which is connected to the installation input of the fourth trigger, the direct output of which is connected to the second input of the eleventh element And, the output of which is connected to the installation input of the third trigger and the counting input of the fourth trigger, direct outputs control transfer registers from the first to the Nth are connected to the information inputs of the blocks of tristable elements of the first group from the first to the Nth, respectively, the outputs of which are connected to the bus control transmission, which is connected to the information inputs of the blocks of tristable elements of the second group from the first to the Nth, the outputs of which are connected to the inputs of the elements OR are NOT the groups from the first to the Nth, respectively, the outputs of the elements of the second group from the first to the Nth are connected with control inputs of blocks of tristable elements of the first and second groups from the first to the Nth, respectively.  2. The module according to claim 1, characterized in that the micro-command address generating unit comprises a start address encoder, a multiplexer, first and second blocks of OR elements, a first and second OR elements, a register, a one-shot and a micro command address register, wherein the input of the start address encoder is the fourth information input of the micro-command address generation unit, the control and information inputs of the multiplexer are respectively the control and first information inputs of the micro-command address formation unit, n - 1 senior bits of the third information input of which (where n is the bit depth of the micro command address) are connected to n - 1 by the highest bits of the first input of the first block of OR elements, and the least significant bit is connected to the first input of the first OR element, the second input and output of which are connected respectively to the multiplexer output and the lower by the discharge of the first input of the first block of OR elements, the synchronization input of the micro-command address register is connected to the synchronization input of the micro-command address generation unit, and the output is the information output of the block the formation of the address of microcommands, the second information input of which is connected to the first input of the second OR element and the first input of the second block of OR elements, the output of which is connected to the information input of the register, the reset input of which is connected to the synchronization input of the formation of the address of the microcommands, and the output is connected to the second input of the first block of OR elements, the output of which is connected to the information input of the address register of microcommands, the output encoder of the initial address is connected to the second input of the second block of OR elements and the second input of the second OR element, the output of which is connected to the input of the one-shot, the output of which is connected to the register synchronization input and the control output of the micro-command address generating unit.

Images