KR100192050B1 - Interrupt circuit for measuring convergence of image process board - Google Patents

Abstract

The present invention uses the VME interrupt to measure convergence in an ITC semi-automatic system so that the 1D image processing board interrupts the central processing unit (CPU) as soon as the 1D camera measurement is completed so that the central processing unit can process data. Interrupt circuit for measuring convergence of an image processing board. In the conventional ITC semi-automated system, an interrupt circuit capable of processing priorities in processing images using a large number of cameras is not added. In order to solve the drawback of not being able to process the video signal in real time, the central processing unit issues a start signal to the LAP board 300 and issues a convergence measurement command. The convergence is measured on the processing unit 100 and the central processing unit 100. In the image processing board for convergence measurement having a LAP board 300 for interrupting the interrupt, an interrupt for giving priority to the interrupt for measuring the convergence in the LAP board 300 and input to the central processing unit 100 The circuit 200 may be further included to shorten the time for transmitting data to the central processing unit (CPU) in the ITC semi-automatic system, thereby processing an image signal in real time.

Description

Interrupt Circuit for Convergence Measurement of Image Processing Board

1 is a block diagram showing an image processing board for measurement of convergence according to the present invention.

2 is a circuit diagram showing in detail the interrupt circuit of FIG.

3 is a timing chart of each stage according to the present invention.

4 is a timing chart of the interrupt enable signal portion of FIG.

5 is a timing chart of an interrupt portion of FIG.

* Explanation of symbols for main parts of the drawings

100: central processing unit (CPU) 200: interrupt circuit

220: interrupt enable signal unit 222,230: counter

224,232,268,286: AND gate 226,228: D flip flop

240: interrupt unit 242: calculator

244,269: note gate 260: interrupt level portion

262,282: Dip Switch 264: Comparator

266: OR gate 280: Interrupt vector address setting unit

284: resistance

300: LAP Board (Linear Array Processor Board)

320: IRQ (Interrupt Requester) 340: Interrupt Vector

360: DTACK (Data Transfer Acknowledge)

380: PAL

The present invention is for the convergence measurement in the ITC semi-automatic system, in particular, as soon as one-dimensional camera measurement is completed using the VME interrupt, the one-dimensional image processing board interrupts the central processing unit (CPU) to process the data. An interrupt circuit for the convergence measurement of an image processing board to be able to do so.

More specifically, the VME interrupt method in the convergence 1D camera processing board in the ITC semi-automatic system implements an interrupt circuit for the system, and transmits the video signal to the central processing unit so that it can be processed according to the priority to enable real-time implementation. It is to.

In general, the ITC semi-automatic system uses a one-dimensional camera to measure the convergence.

However, the conventional ITC semi-automatic system does not have an interrupt circuit that can process priorities in processing images using a large number of cameras, so that the measurement processing time is lengthened, thereby transmitting data to the central processing unit (CPU). The longer the time is, the defect that cannot process the image signal processing in real time occurred.

The present invention has been made to solve the above-mentioned shortcomings, and for this purpose, it is possible to shorten the time for transferring data to the central processing unit (CPU) in the ITC semi-automatic system and to process the video signal in real time In providing an interrupt circuit.

In order to achieve the above object, the present invention provides a method for providing an interrupt vector in which an interrupt board stores a start address of an interrupt service routine, and an interrupt for measuring convergence in the LAP board 300. It is a well-known feature that the interrupt circuit 200 configured to give priority to the central processing unit 100 is further included.

This will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an image processing board for convergence measurement according to the present invention, and FIG. 2 is a circuit diagram showing the interrupt circuit of FIG. 1 in detail.

The LAP board 300 is provided with a central processing unit 100 which issues a start signal to the LAP board 300 and issues a convergence measurement command, and an LAP board 300 which issues an interrupt for measuring the convergence to the central processing unit 100. In the image processing board for convergence measurement, the LAP board 300 is configured to further include an interrupt circuit 200 which gives priority to the interrupt for measuring the convergence and inputs it to the central processing unit 100.

The LAP board 300 is driven by an interrupt handle of the central processing unit 100 to execute a stored convergence measurement program, and a clear signal and an interrupt request signal output from the PAL 380. An IRQ 320 that interrupts the interrupt handle, an interrupt vector 340 that interrupts the interrupt vector by the enable signal output from the PAL 380, and information on the dependent data bus during the write cycle. Afterwards, a DTACK 360 for applying a stack signal is provided.

The interrupt circuit 200 is an interrupt allow signal unit 220 for creating an allowable interval for interrupting by a system clock signal input from the central processing unit 100, and is output from the interrupt allow signal unit 220 A counter 230 for counting a convergence signal and outputting a measurement completion signal BA14, a measurement completion signal BA14 input from the counter 230, and an interrupt permission signal input from the interrupt permission signal unit 220 are logic. The AND gate 232 to multiply, the interrupt unit 240 which makes the interrupt signal multiplied by the AND gate 232 into an IACK signal, and the interrupt level unit which generates an INT-rev signal when the interrupt levels are equal to each other. 260 and an interrupt vector address setting unit 280 for setting an interrupt address vector by combining the INT-rev and the IACK signal generated by the interrupt level unit 260. The rain.

The interrupt permission signal unit 220 divides the system clock provided from the central processing unit 100 to output a camera input counter signal P-2 and a camera input signal, and the counter 222. The AND gate 224 for counting the camera input signal by logically multiplying the camera input counter signal (P-2) and the synchronization signal (SH) at, and the camera input signal and the camera input from the counter 222 is R, G, D flip-flops 226 and 228 for outputting a signal VENA indicating that B is being taken.

The interrupt unit 240 includes an operator 242 for calculating the interrupt permission signal multiplied by the AND gate 232, and a note gate 244 for inverting the signal calculated by the operator 242.

The interrupt level unit 260 determines whether the dip switch 262 for setting an interrupt level is equal to the interrupt level set by the dip switch 262 and the addresses A0 to A3 input from the CPU 100. If the comparison is the same, the comparator 264 outputting the INT-rev signal and the OR gate for activating the INT-rev signal output from the comparator 264 and the interrupt priority signal IRQ input through the note gate 269 ( 266, and an AND gate 268 that logically multiplies the priority signal activated by the OR gate 266 and the RESET signal to the operator 242 and the D flip-flop 228.

The interrupt vector address setting unit 280 sets a dip switch 282 for setting an interrupt vector address, an AND gate 286 for outputting an ID out signal by multiplying an INT-rev signal, and setting in the dip switch 282. And a buffer 288 for filtering the interrupt vector address and ID out output from the AND gate 286 to input the control signal to the CPU 100 through the data bus.

Hereinafter, the operation and effects according to the present invention will be described with reference to the accompanying drawings.

Initially, the convergence measurement board has a red beam on the CRT.

At this time, the central processing unit 100 gives the LAP board 300 a measurement start command, that is, a start signal for starting the convergence measurement board, and then gives a command for measuring the convergence.

Therefore, the counter for generating an address in the convergence measurement board is increased one by one in the counter 222 of the interrupt permission signal unit 220 of the interrupt circuit 200, and the data for the red signal is recognized one by one through the camera.

The signal counted by the counter 222 and recognized by the camera is output to its terminals P-2 and P-3, which outputs a signal indicating that the camera is photographing the convergence on the measurement board. ) Is input to the P-3, and the camera input signal is input to the D flip-flop 226 clock CLK terminal.

That is, the signal input to the AND gate 224 is logically multiplied with the synchronization signal SH to input a signal for convergence to the counter 230.

At this time, the D flip-flop 226 delays the camera input signal inputted to the club (CLK) terminal by a predetermined time signal VENA indicating that the camera is recording R, G, and B through the D flip-flop 228. Input to the AND gate 232.

On the other hand, since the interrupt enable signal input to the counter 230 does not need to be unconditionally high, create an allowable interval for interrupting, and when the BA14 (signal indicating that the camera has completed convergence measurement) appears in that state, the AND gate 232 is opened. The completion signal is input to the calculator 242 of the interrupter 240 through the controller 242.

The operator 242 of the interrupt unit 240 blocks the interrupt by making an allowance signal with an IACK signal without determining the IRQ signal of the current LAP board 300 by the AS signal of the central processing unit 100 during interrupt processing. By inverting through the note gate 244, the interrupt handle IRQ is applied to the OR gate 266 through the note gate 269 of the interrupt level unit 260.

At this time, the interrupt level set in the dip switch 262 and the address A0 to A3 signal input from the central processing unit 100 are compared by the comparator 264, and if the level is currently set on the board, the interrupt level is identical. The D flip-flop of the operator 242 and the interrupt enable signal 220 of the interrupt unit 240 is generated by multiplying the reset signal through the OR gate 266 and the AND gate 268 by generating the INT-rev signal. And input to an AND gate 286 of 228.

Therefore, the AND gate 286 operates the buffer 288 by inputting a signal IN out for an address vector address into an enable terminal of the buffer 288.

When the buffer 288 is operated, the interrupt vector address set in the dip switch 282 is transmitted to the CPU 100 via the data bus.

The CPU 100 receives the interrupt vector address through a data bus and calculates convergence by reading measurement data from a convergence measurement board.

As described above, the present invention provides an interrupt circuit for measuring convergence, thereby reducing the time for transferring data to a central processing unit (CPU) in an ITC semi-automatic system, thereby processing an image signal in real time.

Claims (1)

The LAP board 300 includes a central processing unit 100 which issues a start signal to the LAP board 300 and issues a convergence measurement command, and an LAP board 300 which issues an interrupt for measuring the convergence to the central processing unit 100. In the image processing board for measurement of convergence, the system clock provided from the central processing unit 100 is input to the LAP board 300 in order to give priority to the interrupt for measuring the convergence. A counter 222 which divides and outputs a camera input counter signal P-2 and a camera input signal, and the camera input is multiplied by the camera input counter signal P-2 and a synchronization signal SH at the counter 222. An AND gate 224 for counting signals, a D flip-flop 226 (228) for outputting a camera input signal input from the counter 222, and a signal VENA indicating that the camera is taking R, G, and B signals. An interrupt allow signal unit 220 for creating an allowable interval for interrupting by a system clock signal input from the CPU 100, and a convergence signal output from the interrupt enable signal unit 220. The counter 230 which counts and outputs the measurement completion signal BA14, and the AND signal by AND multiplying the measurement completion signal BA14 input by the count 230 and the interrupt permission signal input by the interrupt permission signal unit 220. 232, an operator 242 for calculating an interrupt allowance signal multiplied by the AND gate 232, and a note gate 244 for inverting the signal calculated by the operator 242. Interrupt unit 240, which makes the interrupt signal multiplied in step 232 into an IACK signal, compares the interrupt level with the interrupt level unit 260 that makes the INT-rev signal if the interrupt level is the same. A dip switch 282 for setting an interrupt vector address, an AND gate 286 for outputting an ID out signal by ANDing an INT-rev signal, and an interrupt vector address and end gate 286 set at the dip switch 282. And an interrupt circuit 200 formed of an interrupt vector address setting unit 280 that filters the ID out output from the control unit to a buffer 288 for inputting a control signal to the central processing unit 100 through a data bus. An interrupt circuit for measuring the convergence of an image processing board.