JPS59100926A - Timer circuit - Google Patents

Abstract

PURPOSE:To set exactly a short time value, as well by supplying a reference clock to a direct memory access (DMA) circuit at the time when a data transfer is not executed, making it execute a DMA operation, and obtaining an output showing a necessary elapsed time when a transfer operation of a prescribed byte number is ended. CONSTITUTION:A micro-processor (MPU) 13 sets an initial value of an address to an address generating circuit 22, and also sets a transfer byte number to a transfer byte number counter 21. When a time counting start signal is applied and a transfer request signal is received, a bus controlling circuit 23 sends a bus occupancy request signal to the MPU 13, and in accordance with a using state of a bus 16, an approval signal is received by the bus controlling circuit. A transfer address is set to a memory 14 and a data is transferred to the memory 14 from a peripheral circuit 15. When the data transfer is ended, the operation as a timer is ended. This data transfer is executed by a prescribed clock period, and a desired timer value can be set by setting a transfer byte number.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a timer circuit for setting timing necessary for processing in a processing device using a microprocessor.

Prior Art and Problems Processing devices using microprocessors often require various timers to set different timings depending on the content of the processing in order to carry out the processing. Generally, such a timer sets a predetermined timing by interrupting a microprocessor at regular intervals and using this as a time reference to count the number of interrupts using software. However, in this case, the interrupt time is often chosen to be a relatively large value that does not reduce the processing capacity of the microprocessor, for example, about several tens of m8, and therefore the time value obtained by such a timer is For example, it is limited to values such as seconds. Therefore, if you need a timer shorter than the above reference time, a timer that requires a time value that is not an integral multiple of the reference time, or a timer with a narrow tolerance range for the upper and lower limits of the time value, use this method of timer. cannot be used, and a separate hardware-based timer must be provided.

FIG. 1 shows the configuration of a conventionally used hardware timer circuit. In the figure, 1 is a reference clock source, and 2 is a counting circuit.

In FIG. 1, a counting circuit 2 counts a reference clock of a constant period from a reference clock source 1 in response to a counting start signal given from a microprocessor, and sets an open number end flag when a set count value is reached. Turn on and notify the microprocessor.

The count setting value may be set by software, and the microprocessor may be notified by interrupt.

The conventional timer circuit shown in Fig. 1 requires a counting circuit and an interface circuit between the counting circuit and the microprocessor to set the count value, and to notify the counting start and counting end instructions. However, it is inevitable that the hardware will become more complex and the scale will increase.

As described above, conventional timers, regardless of whether they are based on software or hardware, have many drawbacks.

OBJECT OF THE INVENTION The present invention attempts to solve the problems of the prior art, and its purpose is to provide accurate processing even for short time values in a processing device having a direct memory access (hereinafter abbreviated as DMA) transfer function. It is very flexible in setting different time values.
It is also an object of the present invention to provide a timer circuit that can minimize the increase in the amount of hardware that constitutes each timer circuit.

Embodiment of the Invention FIG. 2 shows the basic configuration of a timer circuit of the present invention, in which 5 is a DMA circuit, 6 is a changeover switch, 7 is a reference clock source,
8 is a peripheral circuit.

The DMA function is typically used to reduce the time required for data transfer by directly transferring data between peripheral circuitry and memory without going through registers within the microprocessor.

On the other hand, a timer required in a processing circuit using a microprocessor is usually used to specify the time between one process and the next, so if a timer is required, It is often in a state where the data transfer has been completed and the operation has stopped. Focusing on these points, the DM
The A circuit can be used to operate as a timer.

In FIG. 2, the selector switch 6 is normally one of the peripheral circuits 8.
I) HA circuit 5 is switched to peripheral circuit 8.
The transfer operation is performed in response to a transfer request signal sent from. When operating as a timer, for example, when a counting start signal is given from a microprocessor (not shown), the changeover switch 6 is switched to the board clock source 7 side, and the constant cycle (1) generated by the reference clock is switched. A transfer operation is performed byte by byte in response to a transfer request signal, and it is possible to know that a predetermined time has passed by completion of transfer of a predetermined number of bytes.

If the number of transfer bytes set in this platform and DMA circuit is N, then the time from the start of transfer to the end of transfer is Nt.
By arbitrarily setting the number N of transferred bytes, a timer circuit that can set an arbitrary time value can be realized. The period t of the transfer request signal is the time in which one byte of data can be transferred, and is usually a sufficiently short time.

In this way, according to the timer circuit shown in Fig. 2, a short time value can be set, a timer with great flexibility in setting the time value can be obtained, and there is only a slight increase in the amount of hardware required to configure the timer. It is. The reference clock source required at this time can be replaced by another clock in the processing device, or can be omitted.

FIG. 6 shows the configuration of one embodiment of the timer circuit of the present invention. In the figure, 11 is a DMA circuit, 12 is a switching gate, 16 is a microprocessor (MPIJ), 14 is a memory, 15 is a peripheral circuit, and 16 is a bus.

The DMA circuit 11 has a transfer byte number counter 21. It consists of an address generation circuit 22 and a bus control circuit 26.

In FIG. 3, prior to starting operation as a timer, a microprocessor 131d sets an initial value of an address in an address generation circuit 22, and sets the number of transferred bytes in a transferred byte number counter 21. When the time measurement start signal is given and the transfer request signal is received, the bus control circuit 23 sends a bus occupancy request signal to the microprocessor 16, and the microprocessor 131d sends a permission signal to the bus control circuit according to the usage state of the bus 16. Return it to 26. The bus control circuit 26 responds to the transfer request signal from the reference clock source.
controls the gate 12, whereby a transfer address is set from the address generation circuit 22 to the memory 14, and data is transferred from the peripheral circuit 15 to the memory 14. Transfer byte number counter 21 reduces acidity for each byte transfer.
At the same time, the address generation circuit 22 sequentially changes the address in the memory 14 by adding up every byte transferred, and in this way, data is transferred for the set number of bytes. When the setting value of the byte number setting counter 21 becomes 0, a signal No. 11 indicating the end of time measurement is generated, thereby ending the data transfer operation and the operation as a timer.

Note that data may be transferred from the memory 14 to the peripheral circuit 15.

Such data transfer is performed by a clock having a predetermined period, and therefore, a desired timer value can be set upon completion of transfer of the number of bytes set in the transfer byte number counter. As a method of notifying the microprocessor 16 of the completion of the transfer, the bus control circuit 26 may issue an interrupt to the microprocessor 13, or set a flag in the transfer byte number counter indicating that the set value has become 0. The microprocessor 16 may learn this by periodically reading it. Note that since the purpose of data transfer in the above-described operation is to operate the counter in the DMA circuit, it goes without saying that it is not necessarily necessary to transfer actual data.

According to the timer circuit of the present invention as described in detail, the DMA
In a processing device with a transfer function, when data is not transferred, a reference clock is supplied to the DMA circuit to perform DMA processing.
As a result, it is possible to obtain an output indicating the elapse of 10J at the required time when the transfer operation of a predetermined number of bytes is completed, so even a short time value can be set accurately, and various different times 110- It provides great flexibility in setting the timer and minimizes the increase in hardware required for existing circuitry to configure the timer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional timer circuit, FIG. 2 is a diagram showing the principle configuration of the timer circuit of the present invention, and FIG. 6 is a diagram showing the configuration of an embodiment of the timer circuit of the present invention. be. 1... Reference clock source, 2... Counting circuit, 5...
Direct memory access (DMA) circuit, 6... Reference clock source, 7... Peripheral circuit, 11... Direct memory access (DMA) circuit, 12... Switching gate, 13... Microprocessor CMPU) , 14
...Memory, 15...Peripheral circuit, 16...Bus,
21...transfer pie)? Counter, 22... Address generation circuit, 23... Bus control circuit. Patent applicant Fujitsu Limited agent Patent attorney Gobe Tamamushi (5 others)

Claims (1)

[Claims] A DMA that has a transfer byte counter that counts the number of transfer bytes and transfers a preset number of bytes of data to the transfer byte counter one byte at a time in response to a transfer request signal.
In a processing device equipped with a circuit, when the DMA circuit is given a clock start signal, it performs a 1-byte transfer operation for each transfer request signal created by the reference clock, and transfers the byte set in the transfer byte number counter. 1. A timer circuit characterized in that it operates as a timer by generating a signal indicating the end of a clock time transfer.