JPH03188514A - Counting circuit - Google Patents

Abstract

PURPOSE:To read out an exact counted value at an arbitrary time without correcting the momently changing counted value of a counting circuit by providing plural cascaded counting circuits except the lowest-order counting circuit with buffer registers. CONSTITUTION:A device consists of a lower-order counting circuit 10, a higher- order counting circuit 11, a buffer register 12 connected to the higher-order counting circuit 11, a carry propagating circuit 13, a general register 14, a control circuit 16, and a data bus 15 which connects them in common. The general register 14 and the buffer register 12 are connected to the control circuit 16 through the data bus 15, and the control circuit 16 controls the operation of data stored in the register 14 and the procedures. That is, higher-order counting circuits other than the lowest-order counting circuit are provided with buffer registers, and host counted values are simultaneously transferred to buffer registers at the time of reading out the lowest-order counted value. Thus, the exact counted value is read out at an arbitrary time without correcting the momently changing counted value of the counting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a long word length hardware counting circuit that is used in a control logic circuit such as a microprocessor and is composed of a plurality of counting circuits. [Prior Art] Conventionally, in control logic circuits such as process control,
Event counters or timers configured with dedicated hardware are widely used. Considering the ease of processing in the control logic circuit, the word length of counting circuits such as event counters and timers is usually set to match the IM length of the microprocessor used in the control logic circuit. Designed. However, as the field of application of control logic circuits expands with one word length, the counting accuracy or counting range is often insufficient. - As an example, regarding a device logic circuit consisting of a hardware-configured counting circuit (timer) that counts the total number of days since installation of the process device with a counting precision of milliseconds, and a 2-bit microprocessor. , explained below. If one day is calculated in milliseconds, it is 86,40o,oo
o milliseconds (60 x 60 x 24 x 1000). Furthermore, if this is expressed in binary, 1010010101001011010000ooo
o. So, the total is 27 bits. In a microprocessor with a word length of 32 bits, if 27 bits are used for the total millisecond count to represent elapsed time, only 32-27=5 bits are allocated to other displays. In the case of 5 bits, 2°=32, so the counting range is only one month when totaled in units of one day, that is, when displayed with one bit per day. Therefore, in order to count using only 32 bits and one word length, it is necessary to change the counting unit from milliseconds to seconds, for example, to lower the accuracy of timekeeping. In this way, one word length of 32 bits is insufficient to measure the total number of days since the device was installed with millisecond accuracy over several years, and multiple words are required to obtain a sufficient time measurement range. A counting circuit is required. As described above, by providing a hardware counting circuit in a microprocessor or the like, necessary counting accuracy and counting range can be ensured. however,
Since the hardware counting circuit performs counting independently of the control logic circuit even while reading the count value, it is necessary to deal with changes in the count value during readout. FIG. 6 is a block diagram showing a first example of a conventional hardware counting circuit, in which a control logic circuit includes a hardware counting circuit in which two counting circuits are connected in cascade to ensure a time measurement range. It shows. In FIG. 6, numerals 61 and 62 are addition and counting circuits connected in series by a carry propagation circuit 63, and numeral 64 is a counting circuit 61.
62 is a general-purpose register connected to the data bus 65; 66 is an operation for data stored in the general-purpose register 64;
Alternatively, it is a control circuit that controls procedures such as reading count values from the counting circuits 61 and 62 to the general-purpose register 64. Counting circuits 61 and 62 count time in synchronization with counting clock 68. Further, the control circuit 66 operates in synchronization with the machine clock 67 in order to control data calculations, procedures, and the like. First, the machine clock 67 and counting clock 68 will be described. Each count value of the counting circuits 61 and 62 is calculated by the control circuit 6.
6 is read out to the general-purpose register 64 and used, so even if the frequency f of the counting clock 68 is set to a higher frequency than the frequency f of the machine clock 67, accuracy higher than frequency 11 cannot be obtained. , and the frequency f
, and the frequency f are set to be equal or approximately the same, in order to take advantage of the accuracy of the counting clock 68, the control circuit 66 is forced to frequently read and judge the contents of the counting circuits 61 and 62. As a result, the control circuit 66:
There is also a possibility that it will no longer be able to function as a control circuit for the entire logic circuit. Therefore, the frequency f of the counting clock 68 is
The frequency f of the machine clock 67 is generally set to be less than 1
Set it an order of magnitude lower. In the following explanation, in order to facilitate understanding of the operation of the counting circuit and the operation of the control circuit, it is assumed that the counting clock 68 and the machine clock 67 have the same frequency and a phase difference of 180''. 61 is the lower order, counting circuit 6
Addition and counting circuits are connected in cascade so that 2 is at the top. FIG. 7 is an operation time chart in FIG. 6. When there is a count read command, the control circuit 66 first reads the value of the lower counting circuit 61 whose counting frequency is higher than that of the upper one, and transfers the value to the general-purpose register 64 via the data bus 65. Next, the value of the upper counting circuit 62 whose counting frequency is lower than that of the lower one is read out, and this value is transferred to the general-purpose register 64 via the data bus 65. Based on the count value transferred to the general-purpose register 64, the control circuit 66 performs processing such as comparing the count value with a predetermined initial value. As shown in FIG. 7, the counting circuit 61 is at time K. The clock 68 is counted, and a carry is generated at the count value B. At read time T, the count value B of the counting circuit 61
, is transferred to the general-purpose register 64. Since a carry has occurred in the counting circuit 61, the counting clock 68 is counted at the time, and the carry is transferred to the counting circuit 62 via the carry propagation circuit 63.
The count value of the counting circuit 62 is A. Advance to +1. Therefore, the lower data B of the counting circuit 61 is read out at the read time T, but the upper data of the counting circuit 62, which is subsequently read out at the time T1, differs from the value A at the read time T, and is incremented. The value A, +1 will be read out. Therefore, the control circuit 66 that controls the counting circuit 61 and the counting circuit 62 controls the lower counting circuit 6 during the reading period of the counted value.
The state of occurrence of a carry to the higher-order counting circuit 62 is monitored during the reading period of the count value, and if a carry is generated, the higher-order count value is subtracted after the readout to perform correction. Conventionally, in order to eliminate the need for such correction processing,
Hardware counting circuits for long word lengths consisting of multiple words have also been proposed. FIG. 8 is a block diagram showing a second example of a conventional hardware counting circuit, which is a control logic circuit equipped with a two-word counting circuit that does not require correction of changes in count values during readout. An example is shown. 8 differs from the configuration in FIG. 7 in that buffer registers 81 and 83 are inserted between counting circuits 80 and 82 and data bus 86, respectively. The entire control circuit 87 operates in synchronization with a machine clock 88, and the counting circuits 80 and 82 perform counting operations in synchronization with a counting clock 89. Counting circuits 80 and 82 are addition counting circuits connected in cascade through a carry propagation circuit 84, with counting circuit 80 counting the lower value and counting circuit 82 counting the upper value. The read buffer registers 81 and 83 are both connected to a control circuit 87 via a data bus 86, and the control circuit 87 controls the operation and procedure of data stored in the general-purpose register 85. FIG. 9 is an operation time chart in FIG. 8. In FIG. 8, a count value fetch instruction and a data read instruction from the buffer register are required to read the count value from the counting circuit without correcting for changes in the count value that may occur during reading. The count value fetch command causes the count value B0 and count value A of the count circuit 80 and the count circuit 82 to be fetched into the buffer registers 81 and 83 at the same time. In response to the command to read the buffer register 81,
The count value B is sent to the general-purpose register 85 via the data bus 86.
will be forwarded to. Further, in response to a read command from the buffer register 83, the count value A is transferred to the general-purpose register 85 via the data bus 86. In other words, the 91st! As shown in I, the counting circuit 80 is
At time T, the clock 89 is counted and the count value B is obtained. At time 0 T, when a carry is generated, the count value B of the counting circuit 80 and the counting circuit 82 is changed by the count value fetch instruction.
and count value A are fetched into buffer registers 81 and 83. Since a carry has occurred in the counting circuit 80, the count value of the counting circuit 82 increments to A,+1 at time T. However, at time T, the count value B is stored in the general-purpose register 85 by the read command of the buffer register 8 at time T.
, the count value A is read out from the buffer register 83. are read out respectively. In addition, as this type of conventional literature, for example. FNEC Microprocessor/Peripheral Data Book Jl
1989 pp. 118-139. [Problem to be solved by the invention Ill] In the first example of the conventional hardware counting circuit (Fig. 6), that is, in the long word length hardware counting circuit in which counting circuits for multiple words are simply connected in cascade, the control circuit is In addition to reading the count value from the hardware counting circuit, it also detects the carry generation state of the counting circuit during the reading period of the count value, and if a carry occurs, subtracts the upper count value after the readout is completed. , it was necessary to perform correction procedures using software. In this way, the processing overhead when reading the count value has been a factor in reducing the efficiency of the control logic circuit. In addition, in the second example shown in Fig. 8, that is, in a hardware counting circuit in which each counting circuit is provided with a buffer register, even if a change in the count value occurs during the reading period of the count value, the count value does not change after the reading is finished. However, since it requires the same number of buffer registers as counting circuits, the amount of hardware increases, and reading the count value requires a count value fetch instruction in addition to the data read instruction from the buffer register. , the problem is that the number of instructions increases. The purpose of the present invention is to solve these conventional problems, and to eliminate the need for correction of the counted value even if the counted value changes as the counting progresses during the period of transmitting the counted value to the outside, and to reduce the amount of hardware. An object of the present invention is to provide a counting circuit that can reduce the number of instructions compared to the conventional one. [Means for Solving the Problems] In order to achieve the above object, the counting circuit of the present invention is connected to m cascade-connected counting circuits and all counting circuits except the lowest counting circuit. It is equipped with m-1 buffer registers and an output circuit connected to the output terminal of the lowest counting circuit and the output terminal of the buffer register. At the same time as outputting the numerical value, the count values of all the counting circuits except the lowest counting circuit are transferred to the m-1 buffer registers, and the output circuit transfers the counted values of all the counting circuits except the lowest counting circuit and the m-1 buffer registers. The feature is that the transferred count value is output to the read request source in each case. [Function J] In the present invention, in a counting circuit composed of a plurality of words in order to obtain high counting accuracy or a wide counting range, a counting circuit composed of a plurality of cascaded words is provided with an upper counting circuit other than restarting. A buffer register is provided at the top, and by simultaneously transferring the upper count value to the buffer register when reading the lowest count value, accurate count values can be obtained arbitrarily without having to correct the count values of the counting circuit that change from time to time. It can be read out at the time of [Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a counting circuit showing a first embodiment of the present invention, and shows a control logic circuit equipped with a two-word hardware counting circuit. The control logic circuit in FIG. 1 includes a lower-order counting circuit 10, an upper-order counting circuit 11, a buffer register 12 connected to the upper-order counting circuit 11, a carry propagation circuit 13, a general-purpose register 14, and a control circuit 16. and a data bus 15 that connects these in common. The entire control circuit 16 operates in synchronization with a machine clock 17, and the counting circuits 10 and 11 perform counting in synchronization with a counting clock 18. Counting circuits 10 and 11 are addition counting circuits connected in cascade through a carry propagation circuit 13, with counting circuit 10 counting the lower order and counting circuit 11 counting the upper order. The input terminal of the read buffer register 12 is connected to the output terminal of the counting circuit 11, and the output terminal of the buffer register 12 is connected to the data bus 15. Both the general-purpose register 14 and the buffer register 12 are connected to a control circuit 16 via a data bus 15, and the control circuit 16 controls operations and procedures for data stored in the general-purpose register 14. FIG. 2 is an operation timing chart of FIG. 1. In FIG. 1, when there is a command to read a count value from the control circuit 16, the count value B of the counting circuit 10 is read. is read out to the data bus 15, and the count value A of the counting circuit 11 is read out to the buffer register 12 at the same time. That is, among the cascade-connected counting circuits, a read instruction to the counting circuit 10 that does not include a buffer register is also used as a fetch instruction for the count value of the counting circuit 11 that includes the buffer register 12 to the buffer register 12. ing. Then, the count value A is transferred to the general-purpose register 14 via the data bus 15 in response to a count read instruction from the counting circuit 11 . As shown in FIG. 2, the counting circuit IO is at time K. The clock 18 is counted and a carry is generated at the count value B. At read time T, the count value B of the counting circuit 10
, is transferred to the general-purpose register 14, and at the same time the counting circuit 11
The count value A, is transferred to the buffer register 12. Since a carry has occurred in the counting circuit IO, the count clock 18 is counted at time 1 and the carry is transferred to the counting circuit 11 via the carry propagation circuit 13, so that the count value of the counting circuit 11 becomes A, step to +1. However, time T
. Since the count value A of the counting circuit 11 is transferred to the buffer register 12 at time T1, the count value A of the counting circuit 11 is transferred to the buffer register 12 at time T1.
By reading , it is possible to read the value A of time T. In this way, in the two embodiments, when reading the lowest count value, all the upper count values are transferred to the buffer register at the same time, so the count value of the counting circuit that changes from moment to moment can be accurately read without having to correct the count value. Count values can be read out at any time. FIG. 3 is a configuration diagram of a counting circuit showing a second embodiment of the present invention, and shows a control logic circuit equipped with a hardware timer circuit having a two-step configuration that does not match the word length of the control circuit. ing. In many cases, the word length of the hardware clock circuit and the processing unit word length of the control circuit do not necessarily match. In FIG. 3, the control logic circuit includes a clock circuit 30, a clock circuit 31, a buffer register 32, and a carry propagation circuit 33.
, a general-purpose register 34 , a data bus 35 , and a control circuit 36 . The entire control circuit 36 operates in synchronization with a machine clock 37, and the time measurement circuit 30 and time measurement circuit 31 perform time measurement operations in synchronization with a time measurement clock 38. The general-purpose register 34, data bus 35, and control circuit 36 are
The microprocessor has a 32-bit word length, and the entire control logic circuit also has a word length of 32 bits. The timekeeping circuit 30 is a timekeeping circuit that counts the whole day in units of milliseconds, and the timekeeping circuit 31 is a timekeeping circuit that counts the whole 10 years in units of one day. The clock circuit 30 and the clock circuit 31 operate as a clock circuit connected in cascade through a carry propagation circuit 33. 4 is a bit configuration diagram of the clock circuit in FIG. 3, in which FIG. 4(a) shows the configuration of the clock circuit 30,
) shows the configuration of the clock circuit 31. As shown in Figure 4, one day consists of 86400 milliseconds.
000 milliseconds (60 x 60 x 24 x 1000
), and is displayed in the following 27 bits in binary. 1010010101001011010000ooo
o. Here, the clock circuit 30 does not use the upper 5 bits of the 32 bits and always sets them to 0. In addition, 10 years has 3650 days (365X
10), and is expressed in the following 12 bits in binary. 111001000010 Here, the clock circuit 31 selects the top 20 of the 32 bits.
The bit is not used and is always set to 0. FIG. 5 is a diagram showing a method of matching the buffer register in FIG. 3 with the data bus of the control circuit. Here, a 27-bit clock circuit 30 and a 12-bit buffer register 32 are connected to a 32-bit data bus 3.
5 is shown. The output terminal of the 27-bit (bits 5 to 31) clock circuit 30 is connected to the input terminals of 27 bus drive circuits 35-1 of the data bus 35. In addition, the input terminal of the 12-bit (bits 20 to 31) buffer register 32 is
It is connected to the output terminal of the 2-bit clock circuit 31. The output terminal of the 12-bit buffer register 32 is
It is connected to the input terminals of 12 bus drive circuits 35-1 inside the data bus 35. No register is placed in the unused upper bits of the 32 bits, and a potential circuit (VSS) corresponding to the logical value 0 is used.
is placed in the bus drive circuit 35-1 connected to the input terminal. Here, the logical value O is the ground potential. In this way, a connection is made between the timer circuit and the control circuit, which do not match the processing unit word length of the control circuit 36. Note that both the general-purpose register 34 and the buffer register 32 are connected to a control circuit 36 via a data bus 35.
Control circuit 36 controls operations and procedures for data stored in general-purpose register 34. Since the operation timing is the same as in the first embodiment, the explanation will be omitted. In this way, in the counting circuit of this embodiment, if a counting operation occurs during the readout period, it is no longer necessary to correct the counted value using the system M valve software after the readout is completed. In the embodiment, only the case where two counting circuits are connected in cascade has been explained, but when three or more counting circuits are connected in cascade, buffer registers are installed in the counting circuits except the lowest one in exactly the same way. At the same time, when reading the lowest counted value, all words of the higher counted value are transferred to the buffer register at the same time, and from the next timing onwards, they are sequentially transferred from the buffer register to the general-purpose register via the data bus. [Effects of the Invention] As explained above, according to the present invention, in order to achieve high counting precision or a wide counting range, counting circuits excluding the lowest among a plurality of cascade-connected counting circuits Since the circuit consists of a hardware counting circuit with a buffer register, when reading the lowest count value, all the upper count values are transferred to the buffer register at the same time, and the count value of the counting circuit that changes from moment to moment is corrected. It becomes possible to read out accurate count values at any time without having to do so, and the processor can be used with high efficiency.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a counting circuit showing a first embodiment of the present invention, Fig. 2 is an operation time chart in Fig. 1, and Fig. 3 is a diagram showing a second embodiment of the present invention. Block diagram of a counting circuit showing an example, No. 4
The figure is a bit configuration diagram of the clock circuit in Figure 3, Figure 5 is a diagram showing the matching method of the clock circuit, buffer register, and data bus in Figure 3, and Figure 6 is a diagram showing the first example of the conventional counting circuit. FIG. 7 is an operation time chart of FIG. 6, FIG. 8 is a configuration diagram of a second example of a conventional counting circuit, and FIG. 9 is an operation time chart of FIG. 10111: Counting circuit, 12, 32: Buffer register, 14, 34: General-purpose register, 16.36: Control circuit, 15, 35: Data buffer, 130°3 clock circuit, 17.37: Machine clock, 18.38 : Counting clock. Enter V C+) Q'/ゝ1 Fig. 8

Claims (1)

[Claims] (1) m counting circuits connected in cascade and m-1 each connected to all counting circuits except the lowest counting circuit
buffer registers, an output terminal of the lowest counting circuit, and an output circuit connected to the output terminal of the buffer register, and when reading the count value of the lowest counting circuit, At the same time as outputting the count value,
The count values of all counting circuits except the lowest counting circuit are m-
The count value is transferred to one of the buffer registers, and the output circuit is configured to output the transferred count value to the read request source for each of the lowest counting circuit and m-1 buffer registers. A counting circuit with