JPH0240754A - Dma unit - Google Patents

Abstract

PURPOSE:To improve the use efficiency of an in-chip device as compared with a case wherein timer circuits are provided individually by adding a transfer controller to the DMA unit and decreasing idle combinations of devices. CONSTITUTION:A CPU 11 outputs a D/T signal 12 to a timer/DMA controller 2, which operates as a DMA controller when the D/T signal 12 is at high level, but functions as a timer when at low level. For DMA service, the number of times of transfer is set in a counting register 3 and decreased in synchronism with the DMA transfer. When the controller 2 selects timer operation, the value obtained by dividing a time to be closed by the period of a clock is set in the register 3, whose contents are decreased in synchronism with the clock. This operation is repeated and when the value in the register 3 becomes minus, a borrow signal 6 is inputted to the controller 6 and the completion of determined-frequency DMA transfer is detected. Here, a terminal count signal 8 is outputted to indicate the transfer end to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a DMA unit. More specifically, the present invention relates to the configuration of a new MA unit with a timer function added.

Prior Art FIG. 3 is a diagram showing a typical configuration of a conventional DMA unit.

That is, the DMA unit 16 includes a count register 3, a count decrementer 4, and a DMA controller 17.
These are interconnected via an internal bus 5.

The MA unit thus operates as follows.

First, a DMA transfer request is manually input from the peripheral device 13 to the DMA controller in response to the DMARQ signal 9. Upon receiving this, the DMA controller sends HLD to CP Ull.
It sends an AK signal 18 to request release of the right to use the data bus.

When the CPU receives a request for bus usage rights, the CPU
A K signal 19 is returned to the DMA controller to notify that the right to use the data bus has been transferred to the DMA unit. Furthermore,
The DMA unit indicates that DMA transfer is possible.
Peripheral devices are notified by MAAK signal 10.

Furthermore, when DMA transfer becomes possible, the DMA unit itself sets the number of transfers in a count register, and a count decrementer decrements the value of the count register by 1 each time a DMA transfer is performed. When this is repeated and the value of the count register becomes negative, a borrow signal 6 is input from the count decrementer to the DMA controller, and it is detected that a predetermined number of DMA transfers have been processed. The DMA controller then ends the DMA transfer and outputs the terminal count signal 8 to inform the outside of the end of the DMA transfer.

Problems to be Solved by the Invention The conventional DMA controller described above is in a complete standby state when DMA transfer is not used, and in an actual system where DM, A transfer is not used, it is difficult to use hardware resources efficiently. The disadvantage is that it is bad.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art and provide a DMA with a true configuration that can effectively utilize the hardware resources of a DMA controller unit in the case of processing that does not use DMA transfer. Our goal is to provide a controller unit.

Means for solving the problem, that is, according to the present invention, is provided with two functions, a DMA transfer control function and a timer function, and is capable of selectively operating one of the two functions according to a control signal. A DMA unit is provided.

Effect The inventor of the present invention has determined that hardware resources can be used effectively by configuring the DMA unit so that it can also be used as a timer.

Specifically, by making it possible to select between DMA transfer synchronization and clock synchronization as the method of decrementing the value of the register, and configuring either of the synchronous decrement methods to be selectable by a control signal, the DMA A timer function can be easily added to the unit.

The present invention will be described in more detail below with reference to the drawings, but the following disclosure is only one example of the present invention and does not limit the technical scope of the present invention in any way.

Example FIG. 1 is a block diagram of one embodiment of the present invention.

The timer/DMA unit 1 mainly includes a timer/DMA controller 2, a count register 3, and a count decrementer 4.

The timer/DMA controller and the count register and the count register and count decrementer are connected via an internal bus 5, respectively.

Therefore, a borrow signal 6 is sent from the count decrementer to the timer/DMA controller, a DMARQ signal 9 is sent from the peripheral device 13 to the timer/DMA controller, a DMAAK signal 10 is sent from the timer/DMA controller to the peripheral device, and a DMAAK signal 10 is sent from the clock generator 19 to the timer/DMA controller. DM
The A controller lock 7 receives the terminal count signal 8 from the timer/DMA controller, and the CP
The configuration is such that the D/T signal 12 and HLDAK signal 19 are input from the Ull to the timer/DMA controller, and the HLDRQ signal 18 is input to the timer/DMA controller CPU.

The operation of the apparatus shown in FIG. 1 will be explained.

First, the CPU II outputs the D/T signal, and the timer/
Input to DMA controller. Here, if the D/T signal is at a high level, the timer/DMA unit operates as a DMA controller, and if the D/T signal is at a low level, it is configured to perform a timer function. .

The operation when performing DMA service is characterized by setting the number of transfers in a count register and decrementing the value of the count register in synchronization with the DMA transfer, which is similar to the operation of the conventional DMA unit shown in Figure 3. Perform similar processing.

On the other hand, when the timer/DMA unit is selected to operate as a timer, the value obtained by dividing the time to be measured by the clock cycle is set in the count register, and the value of the count register is decremented in synchronization with the clock. When the value in the register becomes negative, a terminal count signal 8 is output, indicating that a predetermined time has elapsed.

Example 2 FIG. 2 is a diagram showing the configuration of another embodiment of the present invention.

The device of this embodiment has the same basic configuration as the previous embodiment, but is characterized in that the D/T signal is controlled from an external terminal.

That is, since the timer/DMA unit can be controlled from the outside, when another system performs processing that uses a timer, it becomes possible to utilize the timer function of this device, further increasing the usage efficiency of the unit.

As described in detail, according to the present invention, by adding a timer function to the DMA unit, the number of idle combinations of units is reduced, and the efficiency of using the entire chip is improved. Compared to the case where they are installed individually, the chip area can be reduced when the CPU, DMA unit, and timer unit are installed in a single chip, and the number of chips can be reduced when the CPU, DMA unit, and timer unit are installed in a multi-chip configuration. can be reduced.

As described above, in the information processing device equipped with the DMA unit according to the present invention, the usage efficiency of the unit within the chip can be kept high for various uses, and the cost of the entire system can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a configuration example of a DMA unit configured according to the present invention, FIG. 2 is a diagram showing another configuration example of a DMA unit configured according to the present invention, and FIG. , is a diagram showing the configuration of a conventional DMA unit. [Main reference numbers] 1...Timer/DMA unit, 2...Timer/DMA controller, 3...Count register, 4...Count decrementer, 5...Internal Bus, 6...Borrow signal,
7...Clock, 8...Terminal count signal, 9...DMARQ signal, 10...DMAAK signal, 11...CPU (central processing unit), 12...
D/T signal, 13...peripheral device, 14...
Clock generator, 15...external terminal, 16...DMA unit,
17...DMA controller, 18...HLDRQ signal, 19...HLDAK signal

Claims (1)

[Claims] A DMA unit comprising two functions, a DMA transfer control function and a timer function, and selectively performing one of the two functions in response to a control signal.