JP2826244B2 - DMA unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA unit having a timer function in a microcomputer.

[0002]

2. Description of the Related Art Conventionally, to transfer a large amount of data between a memory and an I / O device at high speed, a DMA (Direct M
There is a microcomputer that has a memory access unit. Also, as disclosed in Japanese Patent Application Laid-Open No. 2-40754, the DM when the DMA transfer is not used.
DM with timer function for effective use of A unit
There is an A unit.

FIG. 2 shows a conventional DMA having a timer function.
2 shows a unit and other configurations. That is, the CPU 31, D
The DMA unit 32 mainly includes an MA unit 32 and a clock generator 33. The DMA unit 32 includes a DMA control unit 34, a DMA / timer switching register 35, a count register 36, and a count decrementer 37. The CPU 31 and the DMA unit 32 are connected to a bus including an address bus 41, a data bus 42, and a control bus 43.

The operation of the conventional DMA unit having a timer function will be described.

First, a DMA unit 32 is sent from a CPU 31.
By inputting data to the DMA / timer switching register 35 in the above, it is selected whether to perform the DMA operation or the timer operation. Here, the DMA / timer switching register 35
It is configured to perform a DMA operation when the input to the LM is high level, and to perform a timer operation when the input is low level.

When the DMA unit selects the DMA operation, the DMA unit 32 sends a HOLDR to the CPU 31.
It outputs a Q signal 44 requesting that the right to use the bus be surrendered. When the HOLDRQ signal 44 is input, the CPU 31 outputs a HOLDAK signal 45 to notify that the right to use the bus has been transferred to the DMA unit 32. As a result, the I / O device (not shown) is notified that the DMA transfer is enabled, and the DMA operation is started. When DMA transfer becomes possible, the value set as the number of transfers in the count register 36 of the DMA unit 32 is decremented by one each time the count decrementer 37 performs one DMA transfer. When the value of the count register 36 becomes negative by repeating this, the borrow signal 46 is input from the count decrementer 37 to the DMA control unit 34 to notify that a predetermined number of DMA transfers have been processed.

On the other hand, when the DMA unit selects the timer operation, the value to be measured is set in the count register 36 of the DMA unit, and the clock generator 3
3, the value of the count register 36 is reduced in synchronization with the timer clock 47 input from the
When the value of 6 becomes negative, a count end signal 49 is output to notify that a predetermined time has elapsed.

[0008]

In the above-described conventional DMA block having a timer function, the timer operation is completed only once and cannot be repeated continuously. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a more powerful timer function by sharing an existing circuit and enabling repeated continuous timekeeping without causing a significant increase in the circuit. This provides a DMA unit that has been used.

[0010]

According to the present invention, in a DMA unit having a timer function, a transfer source address count register and a transfer destination address count register during a DMA transfer are replaced by a timer count register during a timer operation, and The transfer destination address count register is used as a timer count register during timer operation and a timer count setting value storage register, and the contents of the timer count setting value storage register based on the detection output of the timer operation end detection means and the detection means Is transferred to the timer count register.

[0011]

According to the present invention, it is possible to provide a DMA unit having a relatively powerful and high-performance timer function with a relatively simple configuration without significantly adding a dedicated circuit.

[0012]

FIG. 1 shows an embodiment of a DMA unit according to the present invention. That is, it is mainly composed of a CPU 1, a DMA unit 2, and a clock generator 3. The DMA unit 2 has a configuration including a DMA control unit 4, a DMA / timer switching register 5, a count register 6, and a count decrementer 7. Further, the DMA control unit 4 is configured to include a transfer source address count register 8, a transfer destination address count register 9, and an overflow detection unit 10. CPU 1 and DMA unit 2
Are the address bus 11, the data bus 12, and
Reference numeral 14 denotes a HOLDRQ signal, 15 denotes a HOLDAK signal, 16 denotes a borrow signal, 17 denotes a timer clock signal, and 18 denotes a timer overflow signal.

In this embodiment, the transfer address count register 8 at the time of the DMA operation is replaced with a timer modulo register (a timer count set value storage register for setting a desired time count number at the time of the timer operation; hereinafter, referred to as a "timer modulo register"). .), And the transfer destination address count register 9 during the DMA operation is used as a timer count register that performs actual counting during the timer operation. Further, the overflow detection unit 10 is provided as a dedicated circuit at the time of the timer operation, and does not operate at the time of the DMA operation. The DMA operation and the timer operation are selected such that the DMA operation is performed when the input level of the DMA / timer switching register 5 is high, and the timer operation is performed when the input level is low.

The operation of the embodiment of the present invention will be described below.

When the DMA unit selects the DMA operation, a process similar to the process described in the prior art is performed. At this time, the transfer source address count register 8 operates as a register for specifying an address as a data transfer source,
Every time the MA transfer is performed once, the designated address is counted up. Similarly, the transfer destination address count register 9 operates as a register for specifying an address to be a data transfer destination, and counts up the specified address every time DMA transfer is performed once.

When the DMA unit selects the timer operation, the transfer source address count register 8 (timer modulo register) and the transfer destination address count register 9
(Timer count register) is set to a desired count value, and the value of the timer count register is counted up in synchronization with the timer clock signal 17 input from the clock generator 3. When the value of the timer count register overflows, the overflow detection unit 10
A timer overflow signal 18 is output outside the DMA unit to notify that a predetermined time has elapsed. The timer overflow signal 18 is also input to the timer modulo register, and the count value set in the timer modulo register is loaded into the timer count register, and the count register counts up again in synchronization with the timer clock. I do. Hereinafter, similarly, each time an overflow signal is generated, the fact that a predetermined time has elapsed is notified to the outside of the DMA unit,
Repeat the timer operation. The timer operation ends when the DMA operation is started again or when a stop instruction by the start / stop function of the timer is input.

In FIG. 1, during the timer operation, the transfer source address count register may be used as a timer count register and the transfer destination address count register may be used as a timer modulo register. Not done.

[0018]

As described above, according to the present invention, time can be measured repeatedly and continuously, and the hardware can be effectively used while suppressing an increase in the chip area.
A more powerful and high performance DMA unit having a timer function can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a DMA unit and another configuration according to an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional DMA unit and another configuration.

[Explanation of symbols]

1 CPU (Central Processing Unit) 2 DMA Unit 3 Clock Generator 4 DMA Control Unit 5 DMA / Timer Switching Register 6 Count Register 7 Count Decrementer 8 Source Address Count Register (Timer Modulo Register) 9 Destination Address Count Register (Timer) Count register) 10 Overflow detector

Claims (1)

(57) [Claims] In a DMA unit having a timer function, a transfer source address count register and a transfer destination address count register during a DMA transfer are shared as a timer count register during a timer operation and a timer count setting value storage register. And a means for detecting the end of the timer operation and a means for transferring the contents of the clock count set value storage register to the timer count register based on the detection output of the detection means.