JP2002024160A - Dma transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read data out of a memory device and to send the read data to a serial interface within a little number of times of DMA transfer. SOLUTION: This device is provided with buses 4 and 5, microprocessor 1, memory device 3, DMA transfer control means 2 for performing a DMA transfer interruption to the microprocessor 1 corresponding to a DMA transfer request signal, performing the DMA transfer of data from the memory device 3 to a serial interface A6 when the microprocessor 1 releases the bus, outputting a pulse signal each time data are sent out just for a prescribed data size, stopping DMA transfer when a DMA transfer stop signal is inputted in the middle of series of DMA transfer and recovering the stopped DMA transfer when the microprocessor 1 uses the bus 5 in the state of stopping, and divided counter for outputting the DMA transfer stop signal to the DMA transfer control means 2 when the input time value of the pulse signal is matched with a count stop value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for transferring data between serial interfaces in a device including a microprocessor, a memory device, and a serial interface.
Partially relates to a DMA transfer device controlled by hardware.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional serial DMA transfer device. In FIG. 3, 1 is a microprocessor, 2 is a DMA controller, 3 is a memory device, 4 is an address bus, 5 is a data bus, 6 is a serial interface A, and 7 is a serial interface B.

The conventional serial D constructed as described above
The operation of the MA transfer device will be described below. FIG. 4 is a timing chart for explaining the operation of the conventional serial DMA transfer device. Here, the data in the memory device 3 is transferred to the data bus 5 under the control of the DMA controller 2.
DMA controller 2, serial interface A6
A case will be described in which a DMA transfer is performed to the serial interface B7 via the interface.

[0004] First, a transfer request signal for requesting the start of DMA transfer is input to the DMA controller 2.

[0005] Upon receiving the transfer request signal, the DMA controller 2 outputs a bus release request signal to the microprocessor 1.

Next, in response to the bus release request signal, the microprocessor 1 releases both the address bus 4 and the data bus 5. At the same time, the bus unused signal is DM
Output to A controller 2.

Then, while the bus is open, the data in the memory device 3 is acquired by the DMA controller 2 and transferred to the serial interface B7 via the serial interface A6. During this transfer period, the transfer is continuously performed until the transfer of the transfer data is completed.

[0008]

However, in the above-described conventional configuration, when a predetermined amount of data is transferred from the memory device 3 to the serial interface B7 by repeating the DMA transfer a plurality of times, every time the DMA transfer is performed. In addition, various data are set in the DMA controller 2, and a load such as interrupt processing is applied to the microprocessor 1. Therefore, there is a problem that high-speed data transfer cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a serial DMA device which can transfer continuous data at arbitrary intervals without imposing a burden on a microprocessor.

[0010]

According to a first aspect of the present invention, there is provided a DMA transfer device, comprising: a bus for transmitting data; and a microprocessor connected to the bus for processing the data. And connected to the bus,
A memory means for writing and reading the data transmitted on the bus, and a DMA transfer interrupt to the microprocessor connected to the bus by a DMA transfer request signal, and the microprocessor opens the bus if the microprocessor releases the bus. DMA transfer the data from the memory means to the serial interface, and output a pulse signal each time the data is transmitted by a predetermined data size; and
If a DMA transfer stop signal is input during the series of DMA transfers, the DMA transfer is stopped. If the microprocessor is not using the bus in the stopped state, the DMA transfer is stopped. DAM transfer control means capable of restoring data, and counting the number of times the pulse signal is input, and the counter value defines how many times the data having the predetermined data size is transmitted before stopping the DMA transfer. The count value is compared with the count stop value, and if they match, the DMA transfer stop signal is generated.
A division counter for outputting an MA transfer stop signal to the DMA transfer control means.

According to another aspect of the present invention, there is provided a DMA transfer apparatus, comprising: a bus for transmitting data; a microprocessor connected to the bus for processing the data; And a memory means connected to the bus for writing and reading the data transmitted through the bus, and a DMA transfer interrupt to the microprocessor by a DMA transfer request signal, whereby the microprocessor releases the bus. Then, the data is DMA-transferred from the memory means to the serial interface, and a pulse signal is output each time the data is transmitted by a predetermined data size, and a DMA transfer stop signal is generated during the series of DMA transfers. When input, the DMA transfer is stopped, and in the stopped state, the DMA transfer request signal is DAM transfer control means capable of restoring the DMA transfer which has been stopped if the input is further input, counts the number of times the pulse signal is input, and determines whether the counter value indicates the data of the predetermined data size. Is compared with a count stop value that specifies whether to stop the DMA transfer at the time of transmission.
A division counter for generating an A transfer stop signal and outputting the DMA transfer stop signal to the DMA transfer control means.

According to another aspect of the present invention, there is provided a DMA transfer apparatus, comprising:
In the DMA transfer device described above, the division counter can set a plurality of values as the count stop value.

In order to solve the above-mentioned problems, a DMA transfer device according to a fourth aspect of the present invention provides a DMA transfer device according to the first to third aspects.
In the DMA transfer device described above, the DMA control means DMA-transfers predetermined data from the memory means and repeats the DMA transfer of the predetermined data.

That is, in the case where a predetermined amount of data is divided into arbitrary data sizes and the divided data is transferred a plurality of times, a microprocessor is conventionally interrupted every time each divided data is transferred. DMA transfer
According to the above-described configuration, by setting the value of the division counter, the first data of the predetermined amount of data is started to be transferred. The DMA transfer can be interrupted every time the transfer of an arbitrary data size is completed, and the interrupted DMA transfer can be restored at an arbitrary timing, and can be executed by one DMA transfer until all the data has been transferred. . Therefore, since a predetermined amount of data can be DMA-transferred by reducing the number of DMA transfers, the load on the microprocessor can be reduced, and high-speed data transfer can be realized.

[0015]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a serial DM in this embodiment.
FIG. 2 is a block diagram of the A transfer device, and FIG. 2 is a timing chart of its operation.

In FIG. 1, 1 is a microprocessor,
2 is a DMA controller, 3 is a memory device, 4 is an address bus, 5 is a data bus, 6 is a serial interface A, 7 is a serial interface B, and 8 is a division counter.

Here, when the DMA transfer starts, data of a predetermined number of bits is transferred a plurality of times, and one DMA transfer is completed. Each time data of a predetermined number of bits is transferred, the DMA controller 2 generates a pulse signal, and the division counter 8 counts the pulse signal.

The operation of the serial DMA transfer device configured as described above will be described below.

First, one DMA transfer is divided into a plurality,
The data size of the data to be transmitted by one divided transfer is set in the division counter 8.

A transfer request signal is input to the DMA controller 2.

When the DMA controller 2 receives the transfer request signal, the DMA controller 2 outputs a bus release request signal to the microprocessor 1. The microprocessor 1 receives the bus release request signal and receives an address bus 4 and a data bus. The bus is released at a timing when neither of them is used, and a bus unused signal is output.

Waiting for the bus unused signal to be input to the DMA controller 2, the DMA transfer is started after the input, and the DMA controller 2 acquires the data of the memory device 3 during the bus unused signal period. Then, the acquired data is transferred to the serial interface B7 via the serial interface A6.

When the transfer of the data size set by the division counter 8 is completed during this transfer period, the division counter 8 inputs a transfer interruption signal to the DMA controller 2 and the DMA
The transfer is interrupted. Each control state when interrupted is DMA
The controller 2 holds the information.

Thereafter, when a transfer request signal is input to the DMA controller 2, the state held by the DMA controller 2 immediately before the interruption of the transfer is restored, and the interrupted DMA transfer is performed without passing through the microprocessor 1. Start again.

As described above, according to the present embodiment, by providing the division counter, continuous data can be transferred at an arbitrary interval, and since the controlling device is a counter, the size of the data to be divided and It is possible to realize an excellent serial DMA transfer device in which the interval until transfer can be freely set.

[0027]

As described above, according to the present embodiment, by providing a division counter, continuous data can be transferred at an arbitrary interval, and the size of the data to be divided can be increased by using a control device as a counter. There is an extraordinary effect that an excellent serial DMA transfer device can be realized in which the interval until re-transfer can be freely set.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial DMA transfer device according to an embodiment of the present invention.

FIG. 2 is a timing chart when the apparatus operates.

FIG. 3 is a block diagram of a conventional serial DMA transfer device.

FIG. 4 is a timing chart when the apparatus operates.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Microprocessor 2 DMA controller 3 Memory device 4 Address bus 5 Data bus 6 Serial interface A 7 Serial interface B 8 Division counter

Claims (4)

[Claims] A bus for transmitting data; a microprocessor connected to the bus for processing the data; a memory connected to the bus for writing and reading the data transmitted on the bus; The microprocessor is connected to a bus and issues a DMA transfer interrupt to the microprocessor in response to a DMA transfer request signal. When the microprocessor releases the bus, data is transferred from the memory means to the serial interface.
A, and outputs a pulse signal each time data is transmitted by a predetermined data size, and stops the DMA transfer if a DMA transfer stop signal is input during the series of DMA transfers. DAM transfer control means capable of restoring the DMA transfer which has been stopped if the microprocessor is not using the bus in the stopped state; and a counter for counting the number of times the pulse signal has been inputted; The value is compared with a count stop value that defines how many times the data of the predetermined data size is transmitted before stopping the DMA transfer, and when they match, the DMA transfer stop signal is generated, and the DMA transfer stop signal is generated. And a division counter for outputting to the DMA transfer control means. 2. A bus for transmitting data; a microprocessor connected to the bus for processing the data; a memory connected to the bus for writing and reading the data transmitted on the bus; The microprocessor is connected to a bus and issues a DMA transfer interrupt to the microprocessor in response to a DMA transfer request signal. When the microprocessor releases the bus, data is transferred from the memory means to the serial interface.
A, and outputs a pulse signal each time data is transmitted by a predetermined data size, and stops the DMA transfer if a DMA transfer stop signal is input during the series of DMA transfers. DAM transfer control means capable of restoring the stopped DMA transfer if the DMA transfer request signal is further input in the stopped state, counting the number of times the pulse signal is input, and A count stop value that defines the number of times the data having the predetermined data size is transmitted and the number of times the DMA transfer is stopped, and if they match, the DMA transfer stop signal is generated. A DMA transfer device comprising: a division counter that outputs to a DMA transfer control unit. 3. The DMA transfer device according to claim 1, wherein the division counter sets a plurality of values as count stop values. 4. The DMA transfer device according to claim 1, wherein said DMA control means DMA-transfers predetermined data from said memory means and repeats said DMA transfer of said predetermined data. .