JPH01219942A - Buffer control system - Google Patents

Abstract

PURPOSE:To quickly transfer processing to another I/O data bus by providing a DMA controller with a data transfer temporary stop function and a dummy sending function for data forcible transfer. CONSTITUTION:A processor instructs the DMA controller to start data transfer and starts data transfer. A buffer A and a flag FA are set by a transfer request signal of data A from an I/O data bus. A response signal to the transfer request is sent back. These operations are performed for a transfer request of data B in the same manner. Since plural I/O data busses are controlled by one DMA controller, the processor instructs the DMA controller to interrupt transfer if data transfer is not terminated within a certain time. The processor reads out flag information to perform the recovery processing for next transfer.

Description

[Detailed Description of the Invention] [Summary] Regarding a buffer control method for controlling data transfer of a data buffer in an adapter, processing of DMA control is achieved by shortening the processing time for data transmission processing in a microprocessor in the adapter. For the purpose of improving efficiency, in a data processing system in which memory, adapters, etc. are connected under a central processing unit via a system bus, and multiple input/output devices are connected via the adapter, In the buffer control method for controlling the data transfer of the data buffer, the DMA controller in the adapter includes a control means for forcibly temporarily suspending the data transfer to the memory, and the data in the data buffer is transferred to the boundary of the memory. and an instruction means for forcibly sending the data to the memory after correction according to the conditions and setting dummy data, and in the configuration in which the data buffer is shared by a plurality of I/O data buses, I/
The configuration is such that processing is forcibly transferred to the O data bus after a certain period of time.

[Field of Industrial Application] The present invention relates to a buffer control method for forcing data transfer of a data buffer in an adapter connected to a central processing unit via a system bus in a data processing system, and in particular, the present invention relates to a buffer control method for forcing data transfer of a data buffer in an adapter connected to a central processing unit via a system bus. The present invention relates to a buffer control method effective for data buffer switching control 11 when a data buffer including a controller is shared by a plurality of human output data blocks.

[Prior art and problems to be solved by the invention] Part 4
The figure is a configuration diagram of a data processing system including an adapter.

As shown in the figure, a memory (MEM) and an adapter (ADP) are connected under the central processing unit (CPtl) via a system bus (SB), and an input/output device (I/O device) is connected via the adapter.
/O) is connected. The adapter has a control function for smoothly performing data transfer between the CPU and 1/O and DMA transfer between memory and I/O. The inside of the adapter is usually
D? connected to the microprocessor (MPU) via the internal bus (rn). lA controller (DMA-C
NT) and a data buffer (DB) that temporarily stores data.
U) and multiple I/O control units (I/O) connected to each I/O.
lo-CNT).

In such a configuration, the DMA controller sets buffer monitoring flags FA,
FB, FC, and FD are provided, and the processor monitors the states of these flags via an internal bus.

Normally, data transfer is performed when A, B, C, and D of the data buffer are full, but if they are not full for some reason, dummy data "0" is input to make the buffer appear full and data transfer is performed. Let's do it. -On the other hand, when using multiple I/O data buses (DB, ~DB,, etc.) in a time-sharing manner, if one I/O data bus is monopolized for a long time, the bus will be forcibly used by a command from the processor. was stopped. For example, when transferring data that was not transferred and remained in the data buffer because it does not match the memory boundary to memory, the processor transfers dummy data to an empty area in the data buffer, for example, as described above. C,D
Count and set the number of data, fill the data buffer, and transfer. In this case, if there is less remaining data, the amount of dummy data will increase, and the processor will take more time to process it. Therefore, it takes a lot of time to transfer processing to another I/O data bus, causing a problem of processing delays when connecting a plurality of I/O data buses.

An object of the present invention is to provide a data transfer temporary stop function and a dummy sending function for forced data transfer in a DMA controller, so that processing can be quickly transferred to another I/O data bus, and data The purpose is to improve the efficiency of transfer processing.

[Means and operations for solving the problems] FIG. 1 is a diagram showing the basic configuration of the present invention. As shown in the figure, according to the present invention, a system bus (S
Memory (MEM), adapter (ADP), etc. are connected through B), and multiple input/output devices (Il) are connected through the adapter.
o) in a buffer control method for controlling data transfer of a data buffer (DBU) in the adapter in a data processing system to which a DM in the adapter is connected;
Control means (A) for forcing the A controller (DMA-CNT) to temporarily suspend data transfer to the memory;
and instruction means (B) for forcibly sending the data to the memory after correcting the data in the data buffer according to the boundary condition of the memory and setting dummy data. multiple I/O
In a configuration in which data buses are shared, processing is forcibly transferred to another I/O data bus after a certain period of time.

〔Example〕

FIG. 2 shows the DM for buffer control according to the present invention.
This is a transfer control circuit provided in the A controller. As shown in the figure, the transfer control circuit T is a flip-flop circuit F.
It is composed of F, ~FF3 and an AND circuit.

In such a configuration, the human output signal to each flip-flop has the following function. Note that the * mark indicates an inverted signal. That is, *Round - MS-STR, data is being transferred to memory BP-WRK, DMA controller is transferring a series of data to data buffer, 5TP-BP-5ET-PF, setting dummy to data buffer * IIF- FL, data buffer storage status 0F-S
TR-FLG, data transfer start flag BP-5TP-
FLG indicates a data transfer stop instruction flag. Note that the signal BP-WRK is turned off after the stop instruction is completed, and the signal BP-STR-FLG becomes a forced data retrieval activation flag due to the off instruction when the signal BP-5TP-PF is on. Further, 5ET-BP-CNT is a set pulse for the bath sofa control register.

FF+ output signal to AND circuit* BF-5TR-F
LGSPF! Output signal of BF-5TP-FLG, FF
3 output signal *5TP-11F-SF! T-FF, etc. are input manually, and furthermore, a signal is sent from the buffer monitoring register * BF
-PL is input. The AND circuit activates FF3 to set dummy data only when these signals match, and F1?3 outputs a dummy set signal *5TP-BF-SET-FF to the data buffer.

FIG. 3 is a signal time chart according to the present invention.

(1) Starting data transfer The processor instructs the DMA controller to start data transfer. Signal 5ET-B from processor
P-CNTO is issued, and signal BF-3TR-FLG is turned on to start data transfer.

(2) Start data transfer A data transfer request signal (RE) from the I/O data bus
) sets the A buffer and FA flag. Then, a response signal (ACK) to the transfer request is returned. These operations are similarly performed for the next B data transfer request.

(3) Interruption of data transfer Since multiple I/O data buses are handled by one DMA controller, it is necessary to transfer data in a time-sharing manner. Therefore, in operation (2), when the data transfer is not completed within a certain period of time, the processor instructs the DMA controller to interrupt the transfer. In this case, the signal 5ET-BP-CNTI is generated from the processor and the signal BP-STP-FLG is turned on.

(4) Recovery processing after transfer interruption The processor reads flag information from the DMA controller and performs recovery processing for the next transfer.

(5) Instructing the processor to forcefully transmit data in the data buffer to the memory After the recovery process, the signal BP-5TR-FLG is turned off in order to transfer the buffer internal data to the memory.

(6) Since it is necessary to set dummy data to the data buffer and transfer data to the memory, it is necessary to perform boundary control to the memory address, so the signal BP-5TR-FLG is off and the signal BP-5TR-FLG is off.
By combining the condition that 5TP-FLG is on and the condition that the buffer is not full, the signal 5TP-BP-5ET-
1iF is turned on and dummy data/flag is set.

Note that when the buffer becomes full after repeated execution, the data is sent to the memory and the series of processing ends.

[Effects of the Invention] As described above, according to the present invention, the microprocessor in the adapter performs data transmission processing, that is, forced transmission of data in the data buffer to memory, and setting of dummy data to the data buffer and memory. The time required to perform processing such as data transfer to is significantly reduced, effective MA control and buffer use become possible, and a multiple I/O data control adapter with improved processing efficiency can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention; FIG. 2 is a diagram showing the main parts of a DMA controller according to the present invention; FIG. 3 is a signal timing chart of the present invention; and FIG. 4 is a system diagram including an adapter. It is. (Explanation of symbols) cpu...Central processing unit MEM...Memory SR...System bus ADP...Adapter MPU...Microprocessor DMA-CNT...DMA Controller DBU...
・Data buffer 18...Internal bus Ilo...Input/output device Fig. 1: Principle configuration diagram of the present invention

Claims (1)

[Claims] 1. A system bus (S) under the central processing unit (CPU)
Memory (MEM), adapter (ADP), etc. are connected through B), and multiple input/output devices (I/O) are connected through the adapter.
O) in a buffer control method for controlling data transfer of a data buffer (DBU) in the adapter in a data processing system to which a DM in the adapter is connected.
A control means (A) for forcing the A controller (DMA-CNT) to temporarily suspend data transfer to the memory; After setting,
instruction means for forcibly sending data to the memory (
B), in a configuration in which the data buffer is shared by a plurality of I/O data buses, the buffer control is characterized in that processing is forcibly transferred to another I/O data bus after a certain period of time. method.