JPH0540728A - Bus control method - Google Patents

Abstract

PURPOSE:To enable initializing an I/O adapter and incorporating an I/O adapter into an I/O bus by using less numbers of signal wires. CONSTITUTION:An I/O bus 1 for data transfer which connects an input/output processing device 6 with plural I/O adapters 11, 12,..., 1n and a command bus 3 including a data bus 32 which has a width of plural bits and which transfers a state control command of the I/O adapter are incorporated. Within the input/ output device 6, a command bus controller 64 which sends out a control command and a reception register 65 which receives operation enable notice signals from respective I/O adapters for each I/O adapter are provided. Within each I/O adapter, a reception register 114 which receives control commands, a decoder 116 which, in response to it, at least sends out a control signal for initializing the I/O adapter and separating I/O bus and a flip-flop 117 which sends out the operation enable notice signal are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a bus control method in an information processing device in which input / output processing devices of an O adapter are connected by a bus.

[0002]

2. Description of the Related Art In the area of small computers, an I / O adapter for controlling an input / output processing unit (hereinafter referred to as IOP) and peripheral devices are often connected by a bus.
Using this bus, synchronization control between IOP-I / O adapters, CCE delivery, and actual data transfer are performed.

[0003]

In this conventional bus control system, since the bus is used for communication, if the logic relating to the control of the bus of a certain I / O adapter fails, the subsequent I / O adapter will be used. Not only is it impossible to operate, but there is also the problem that it may adversely affect other I / O adapters that have not failed.

In order to solve this, there is a method of individually providing a status control line from the IOP to each I / O adapter, but there is a problem that the signal line is excessively increased in a small computer due to its structure.

[0005]

According to the bus control method of the present invention, information having an input / output processing device for controlling data transfer between an I / O device and a main memory and an I / O adapter for controlling the I / O device is provided. In a bus control method in a processing device, a first bus for data transfer connecting between the input / output processing device and the plurality of I / O adapters, and data having a plurality of bit widths for transferring a state control command of the I / O adapter A second bus including a bus, means for sending the control command into the input / output processing device, and means for receiving an operable notification signal from each I / O adapter for each I / O adapter And means for receiving the control command in the I / O adapter and transmitting a signal for controlling at least the initialization of the I / O adapter and the disconnecting unit of the first bus in accordance with the command. Characterized in that a means for delivering the work notification signal.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 shows an information processing apparatus according to the first embodiment of the present invention.

This information processing apparatus has a system bus 1 and I / O.
It has a bus 2, a command bus 3 and three types of buses.

The system bus 1 is an arithmetic processing unit (hereinafter referred to as EP
An abbreviated U) 4, a main memory unit (hereinafter referred to as MMU) 5, and an input / output processing unit (hereinafter referred to as IOP) 6 are connected to perform data transfer of each device.

The I / O bus 2 connects the IOP 6 and a plurality of I / O adapters 11, 12, ..., 1n, and performs data transfer between the peripheral device and the IOP (actually, passing through the IOP 6 and the MMU 5).

The command bus 3 similarly connects the IOP 6 and the I / O adapters 11, 12, ..., 1n, but is used only for transferring the command from the IOP 6.

The system bus 1 and the I / O bus 2 have a plurality of byte widths (for example, 4 bytes) and a plurality of control lines, but the command bus 3 has a BOP signal 31 for notifying the start of the bus operation and 4-bit data. I have only bus 32.

The IOP 6 has a processor 61 for executing micro-instructions and controlling input / output operations, a system bus controller 62 for controlling the system bus 1, an I / O bus controller 63 for controlling the I / O bus, and a command. Bus 3
Command bus controller 64 for controlling the above, and a reception register 65 for receiving the OPI signal which is the operation enable notification signal from each I / O adapter 11, 12, ..., 1n.
The I / O bus controller 63 is provided for each I / O adapter 11,
It also has a function of accepting a bus request signal from 12, ..., 1n and giving a right to use the bus.

Next, I / O adapters 11, 12, ..., 1n
The internal structure will be described. Each I / O adapter 11, 12,
..., 1n have the same structure, so here 11 I / Os
Only the adapter will be explained.

The I / O adapter 11 includes a processor 111 for executing microinstructions and controlling peripheral devices, and an I / O adapter 11.
I / O bus controller 112 for controlling the I / O bus 2
, A device controller 113 for controlling the interface of peripheral devices, a reception register 114 for receiving data from the command bus 3, an adapter number sent via the command bus 3, and each I / O adapter 11, 1.
2, ..., 1n unique adapter number (I
"1" is added to the / O adapter 11)
And a decoder 116 that receives the coincidence signal from the comparator 115, analyzes the command command transmitted in the cycle next to the adapter number, and transmits the command signal.
And the flip-flop 117 set by the processor 11 and the tri-state (Tri S) of the I / O bus.
state) driver 118, receiver 119, and AND gate 11A for sending a bus request.

The decoder 116 sends an RST signal for initialization based on a command command and a signal OPO indicating whether the IOP 6 can service the I / O adapter.
The tristate driver 118 enters the tristate state when the OPO signal is "0". Also, AND gate 11A
Similarly, when the OPO is "0", the output is fixed to "0". As a result, neither request nor data can be output from the I / O adapter 11, and the I / O adapter 11 is disconnected from the I / O bus. Table 1 shows the command command patterns in binary and hexadecimal.

[0017]

[Table 1]

FIG. 2 is a time chart of the operation of the command bus 3.

An operation example for initialization will be described with reference to FIG.

In bus cycle T ¹ , IOP 6 sends command bus 3
The ID number (here, "1") of the target I / O adapter is put on the data bus 32 of the above, and the BOP signal 31 is set to "1". All I / O adapters 11, 12, ..., 1n
Has the BOP of "1", the next bus cycle T ²
Then, the data of the data bus 32 is taken in, and the comparison with the ID number given in advance is performed by the comparator 115.

The I / O adapter (here, the I / O adapter 11) having the same ID number is bus cycle T ³
Then, the command command received in the bus cycle T ² is decoded. When instruction command to indicate initialization "3" is transmitted, decoded 116, OP bus cycle T ⁴
The O signal is set, and the RST signal is sent for 1T to initialize the inside of the I / O adapter 11. In the bus cycle T ^{x in} which the initialization is completed, the processor 111 sets the flip-flop 1
17 is set to "1" to notify the IOP 6 that it is operable.

By sending the command command "0" to reset the OPO signal in the same bus sequence, it is possible to send the command command "1" to set the OPO.
It is possible to control the incorporation / disconnection of the I / O adapter 11 from the OP6 to the I / O bus 2.

FIG. 3 is a block diagram of the second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 except for the data bus 32 of the command bus 3 have the same functions, so that the description thereof will be omitted and only different portions will be described.

The data bus 32 of the command bus 3 is 1 in this example.
An ID code and a command command are serially transmitted from the IOP 6 through a signal line having a bit width. The parallel-serial converter 66 in the IOP 6 is controlled by the command bus controller 64.
In response to the bit ID number and the command command, the BOP signal 31 is serially sent to the data bus 32 bit by bit from the cycle in which it becomes "1".

Silipara converter 1 in the I / O adapter 11
1B sequentially takes in the contents of the data bus 32 from the cycle when the BOP signal 31 becomes "1", converts the contents into a 4-dot code, and sends the data to the reception register 114.

FIG. 4 is an operation time chart of the embodiment shown in FIG. Next, an operation example of this embodiment will be described with reference to FIG. Note that the operation is an example of initialization similar to FIG.

At the bus cycle T ¹ , the BOP signal 31 becomes "1", and the ID number is sent to the data bus 32 bit by bit until the bus cycle T ⁴ . ID parallelized from the serial-parallel converter 11B in the bus cycle T ⁵
Number "1" is taken into the receiving register 114 in cycle T ⁶ is sent to the receiving register 114. The fetched ID number is compared with the ID number assigned to each I / O adapter, and if they match, the comparator 115
To “1” value is output to the decoder 116.

In the bus cycle T ⁹ , the command command "3" sent after the ID number is converted into parallel,
The serial-parallel converter 11B sends it to the receiving register 114, and the receiving register 114 takes in this value at the bus cycle T ¹⁰ and sends it to the decoder 116. The decoder 116 decodes and sends the RST signal for initialization and sets the OPO signal in the next bus cycle T ¹¹ . Processor 1
Reference numeral 11 sets the flip-flop 117 of the OPI signal in the bus cycle T ^{x in} which the initialization is completed, and communicates to the IOP 6 that it is ready to operate.

In the second embodiment, the command bus can be constructed with a smaller number of signal lines by providing serial command converters 66 and 11B in the command bus transmitter 1 of the IOP and the receiver in the I / O adapter, respectively. There is an effect.

FIG. 5 is a block diagram of a third embodiment of the present invention. In the figure, blocks having the same numbers as those in FIGS. 1 and 3 have the same function, but the following points are different.

First, the command bus 3 comprises four signals, a first BOP signal 31, a data bus 32, a second BOP signal 33 and an OPI bus 34. Of these, the first BOP signal 31 and the data bus 32 have the same functions as the BOP signal 31 and the data bus 32 in the second embodiment. The second BOP signal 33 is a signal requesting that the OPI state of each I / O adapter be sequentially sent to the OPI bus 34 from the next bus cycle.
Wired and connected to the / O adapter. OP
The I bus 34 is similarly wired and connected to each I / O adapter.

Unlike in the first and second embodiments, the OPI reception register 65 in the IOP 6 is a serial-in / parallel-out 15-bit shift register, and the second BOP signal 33 becomes valid next. The value of the OPI bus signal 34 is sequentially fetched from the next bus cycle of 1 with the polarity reversed for 15 bits.

The OPI bus controller 11C in the I / O adapter 11 outputs the second BOP signal 33 of the command bus 3 for 1T through the oven collector type inverter 11D in the vice cycle in which the processor 111 sets the OPI in the flip-flop 117. Then, the number of bus cycles is counted from the next bus cycle, and the enable signal for outputting the value of the flip-flip 117 to the OPI bus 34 is transmitted in the bus cycle in which the count value becomes equal to the ID number. For example, the ID number is "1"
If the ID number is “8” in the next bus cycle when the second BOP signal 33 becomes active,
The enable signal is transmitted in the bus cycle after 8T.

The NAND gate 11E is an open collector type NAND gate, and has an enable signal from the OPI bus controller 11C and a flip-flop 117.
The input signal of the output signal is input to drive the OPI bus 34.
Only when the enable signal is valid, the inverted value of the value of the flip-flop 117 is output to the OPI bus 34.

FIG. 6 is an operation time chart of the embodiment shown in FIG. Next, the initialization operation of this embodiment will be described with reference to FIG.

In FIG. 6, the operation of the command bus 3 for initialization is started in the bus cycle T ^1. However, the sending of the RST signal and the setting of the OPO signal are the same as those in FIG. The bus cycle T ^x in which the initialization is completed and the initialization is completed will be described.

Processor 11 in bus cycle T ^x
1 sets the flip-flop 117 and sets O
The PI bus controller 11C is instructed to notify the IOP6, and the OPI bus controller 11C sends the second BOP signal 33 for 1T. Since the ID number of the I / O adapter 11 is "1", it is OP in the bus cycle T ^{x + 1} .
The I-bus controller 11C sends an enable signal for 1T, and the value of the flip-flop 117 is inverted and output to the OPI bus 34 by the NAND gate 11E. Since "1" is set in the flip-flop 7,
The PI bus signal 34 becomes "0".

In the bus cycle T ^{x + 2} , the bus cycle T ^x
The I / O adapter 12 of ID number "2", which has recognized the bus activation due to the transmission of the second BOP signal 33 at, outputs the inverted value of the flip-flop 7 to the OPI bus 34 for 1T, and at the same time, the reception register 65 of IOP6. Takes in the inverted value of the value on the OPI bus 34 in the previous bus cycle. (In this embodiment, I / O other than the I / O adapter 11
The OPI of the O adapter is "0". ) Bus cycle T
^{For x + 3} , I / O of ID number "3" is added to OPI bus 34.
The OPI information of the O adapter is loaded and the reception register 65 is set to 1
OPI with ID number "2" shifted left by one bit
Capture information.

In this way, O of the I / O adapter which can be connected (maximum 15 units in this embodiment) in the bus cycle T ^{x + 16} after 15 bus cycles from the bus cycle T ^{x + 1.}
All PI information is taken into the reception register 65.

In the third embodiment, since the OPI signal of each I / O adapter can be serialized and notified to the IOP, there is an effect that the same function can be configured with a smaller number of signal lines as a whole.

[0041]

As described above, according to the present invention, a command bus is provided between the IOP and the I / O adapter in addition to the I / O bus that controls data transfer, and this is used to initialize the I / O adapter (RST). Since the I / O bus is configured to be attached to or detached from the I / O bus by sending or receiving) or OPO signals, the above control can be performed with a small number of signal lines without providing RST signals and OPO signals for each I / O adapter. It has the effect of being independent.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

2 is an operation time chart of the embodiment shown in FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

4 is an operation time chart of the embodiment shown in FIG.

FIG. 5 is a block diagram of a third embodiment of the present invention.

FIG. 6 is an operation time chart of the embodiment shown in FIG.

[Explanation of symbols]

 1 System Bus 2 I / O Bus 3 Command Bus 4 EPU 5 MMU 6 IOP 11, 21, 1n I / O Adapter 61 Processor 62 System Bus Controller 63 I / O Bus Controller 64 Command Bus Controller 65 Receive Register 66 Parasili Converter 111 Processor 112 I / O bus controller 113 Device controller 114 Reception register 115 Comparator 116 Decoder 117 Flip-flop 118 Driver 119 Receiver 11A AND gate 11B Silipara converter 11C OPI bus controller 11D Inverter 11E NAND gate

Claims (3)

[Claims] 1. A bus control method in an information processing apparatus having an input / output processing device for controlling data transfer between an I / O device and a main memory, and an I / O adapter for controlling an I / O device, comprising: A first bus for data transfer connecting between the device and the plurality of I / O adapters, and a second bus including a data bus having a plurality of bit widths for transferring a state control command of the I / O adapter; A means for sending the control command to the entry output processing device and an operation enable notification signal from each of the I / O adapters.
Means for receiving each I / O adapter, and receiving the control command in the I / O adapter,
According to the command, at least a means for sending a signal for controlling the initialization of the I / O adapter and a means for disconnecting the first bus and a means for sending an operable notification signal are provided. 2. A data bus in the second bus has a single bit width, and a parallel-serial converter for serially outputting the output of the control command sending means to the second bus in the input device. 2. The bus control system according to claim 1, further comprising a serial-parallel converter for converting data on the second bus into a plurality of bits in the I / O adapter. 3. A single wired signal line of each I / O adapter is provided as a part of the second bus,
The input / output processing device has a shift register that sequentially takes in the output of the signal line, and an operation enable notification signal in the I / O adapter is provided at a predetermined timing for each I / O adapter. 3. The bus control system according to claim 1 or 2, further comprising means for sending the data to a line.