JPH0474747B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This invention relates to a DMA controller device that controls data transfer of a data buffer in an adapter, by shortening the processing time for data transmission processing in a microprocessor in the adapter.
The purpose is to improve the processing efficiency of DMA control, and it is used in data processing systems in which memory, adapters, etc. are connected under the central processing unit via a system bus, and multiple input/output devices are connected via the adapters. In the DMA controller device that controls data transfer of a data buffer in the adapter, the DMA controller in the adapter includes a control unit for forcibly temporarily suspending data transfer to the memory; and an instruction means for forcibly sending data to the memory after correcting it according to the boundary condition of the I/O data bus and setting dummy data, the data buffer being shared by a plurality of I/O data buses. The configuration is such that processing is forcibly transferred to the I/O data bus after a certain period of time.

[Industrial application field]

The present invention forces data transfer in a data buffer in an adapter connected to a central processing unit via a system bus in a data processing system.
Regarding DMA controller devices, this is particularly effective for data buffer switching control when a data buffer including a DMA controller is shared by multiple input/output data buses within an adapter.
Relating to a DMA controller device.

[Problems to be solved by conventional technology and invention]

FIG. 4 is a configuration diagram of a data processing system including an adapter. As shown in the figure, a memory MEM and an adapter ADP are connected under a central processing unit (CPU) via a system bus SB, and an input/output device I/O is connected via the adapter. The adapter is
Data transfer between CPU and I/O, memory and I/O
It has a control function to smoothly perform DMA transfer between The internals of the adapter are usually connected to the microprocessor MPU via the internal bus IB.
It is composed of a DMA controller DMA-CNT, a data buffer DBU for temporarily storing data, and a plurality of I/O control units I/O-CNT connected to each I/O.

In such a configuration, the DMA controller provides buffer monitoring flags FA, FB, FC, and FD in the registers to monitor the data storage status of small areas A, B, C, and D of the data buffer, and communicates with the processor via the internal bus. monitors the state of these flags. Usually, data buffer A, B, C, D
If it is satisfied, data transfer is performed, but if it is not satisfied for some reason, dummy data "0" is input and data transfer is performed with the data being apparently satisfied. On the other hand, multiple I/O data buses DB ₁ ~
When using DB _o in time division, one I/O
When the O data bus is occupied for a long time, bus use is forcibly stopped by a command from the processor. Also, for example, when transferring data that was not transferred and remained in the data buffer because it does not match the memory boundary to the memory, the processor transfers dummy data to an empty area in the data buffer, such as C, D, as described above. The number of data is counted and set, the data buffer is filled, and the data is transferred. In this case, if the remaining data is small, the amount of dummy data will increase, and the processor will take more time to process it. Therefore, other I/O
It takes a lot of time to transfer the processing to the data bus, causing a problem of processing delays when connecting a plurality of I/O data buses.

An object of the present invention is to provide a DMA controller with a data transfer temporary stop function and a dummy sending function for forced data transfer, so that other I/O
The object of the present invention is to make it possible to quickly transfer processing to the O data bus and to improve the efficiency of data transfer processing.

[Means and actions for solving the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. As shown in the figure, according to the present invention, a memory MEM and an adapter ADP are connected under a central processing unit CPU via a system bus SB, and the adapter has a DMA controller device and a data buffer, and a plurality of data buffers are connected to each other. In a data processing system in which input/output devices I/O are shared, the DMA controller device monitors the data storage state of each of the small areas A, B, C, and D in the data buffer. When data transfer from the data buffer to the memory is not completed within a certain period of time because there is free space in either the register holding the flags FA, FB, FC, or FD, or in the small area, the data transfer is stopped. A control means A forcibly suspends the operation, reads the flag held in the register, sets dummy data in a small vacant area, cancels the suspension, and transfers data from the data buffer to the memory. and an instruction means B for instructing forced retransfer of the information.

〔Example〕

FIG. 2 shows a transfer control circuit provided within the DMA controller to perform buffer control according to the present invention. As shown in the figure, the transfer control circuit T is composed of flip-flop circuits FF ₁ to FF ₃ and an AND circuit.

In such a configuration, the input/output signals to each flip-flop have the following functions. still,*
The mark indicates an inverted signal. That is, *WRK-MS-STR; Transferring data to memory BF-WRK; DMA controller transferring a series of data to data buffer STP-BF-SET-FF; Setting dummy to data buffer *BF-FL; Data buffer storage state BF-STR-FLG; data transfer start flag BF-STP-FLG; indicates a data transfer stop instruction flag. Note that the signal BF-WRK turns off after the stop instruction is completed, and the signal BF-STR-FLG turns off.
When BF-STP-FF is on, it becomes a forced data capture start flag due to an off instruction. Also,
SET-BF-CNT is the buffer control register set pulse. To the AND circuit
FF ₁ output signal *BF-STR-FLG, FF ₂ output signal BF-STP-FLG, FF ₃ output signal *STP-
BF-SET-FF, etc. are input, and a signal *BF-FL is input from the buffer monitoring register.
The AND circuit activates FF ₃ to set dummy data only when these signals match, and FF ₃ sends the dummy set signal* to the data buffer.
Outputs STP-BF-SET-FF.

FIG. 3 is a signal time chart according to the present invention.

(1) Starting data transfer The processor instructs the DMA controller to start data transfer. The signal SET−BF−CNTO is issued from the processor, and the signal BF−
STR-FLG turns on and data transfer starts.

(2) Start of data transfer The A buffer and FA flag are set by the A data transfer request signal (REQ) from the I/O data bus. Then, a response signal ACK to the transfer request is sent back. These operations are the following B
The same process is performed for data transfer requests.

(3) Interruption during data transfer Because multiple I/O data buses are handled by one DMA controller, data must be transferred in a time-sharing manner. Therefore, in operation (2), if the data transfer is not completed within a certain period of time, the processor instructs the DMA controller to interrupt the transfer. In this case, the signal from the processor
SET−BF−CNT1 is generated, and the signal BF−STP−
FLG turns on.

(4) Recovery processing after transfer interruption The processor reads flag information from the DMA controller and performs retransfer processing for the next transfer, that is, cancels the interrupted data transfer and retransfers from the data buffer to memory.

(5) Instructions for forced transmission of data in the data buffer to memory In order to transfer the buffer internal data to memory after recovery processing, the processor sends a signal BF-STR-
Turn off FLG.

(6) Setting dummy data to the data buffer and transferring data to the memory Since it is necessary to perform boundary control to the memory address, the signals BF-STR-FLG are off.
The signal BF-STP-FLG is
STP-BF-SET-FF is turned on and dummy data/flags are set. Note that when the buffer becomes full after repeated execution, the data is sent to the memory and the series of processing ends.

〔Effect of the invention〕

As explained above, according to the present invention, the microprocessor in the adapter performs data transmission processing, that is, forced transmission of data in the data buffer to memory, setting of dummy data to the data buffer, and data transfer to memory. The time required for processing is significantly reduced, effective DMA control and buffer use become possible, and a multiple I/O data control adapter with improved processing efficiency can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing the main parts of a DMA controller according to the present invention, FIG. 3 is a signal timing chart of the present invention, and FIG. 4 is a system configuration diagram including an adapter. It is. Explanation of symbols, CPU...central processing unit, MEM...memory, SB...system bus, ADP...adapter,
MPU...Microprocessor, DMA-CNT...
DMA controller, DBU...data buffer,
IB...internal bus, I/O...input/output device.

Claims (1)

[Claims] 1. A system bus SB under the central processing unit CPU.
A data processing system in which a memory MEM and an adapter ADP are connected via a DMA controller device, the adapter has a DMA controller device and a data buffer, and the data buffer is shared by a plurality of input/output devices I/O, wherein the DMA controller device is , small areas A, B, C, D in the data buffer
registers that hold flags FA, FB, FC, and FD for each corresponding small area to monitor the data storage status of each area, and data transfer from the data buffer to the memory because there is free space in any of the small areas. control means A forcibly suspending the data transfer when the data transfer is not completed within a certain period of time; and a control means A that reads the flag held in the register and sets dummy data in a vacant small area. The present invention is characterized by comprising instruction means B for canceling the interruption and instructing forced retransfer of data from the data buffer to the memory.
DMA controller device.