JPH02120961A - Inter-memory data transfer system - Google Patents

Abstract

PURPOSE:To rapidly execute inter-memory data transfer between arithmetic units by separating a hand shaking function in a DMA controller independently of an inter-memory data transfer function and adding a function for controlling another DMA controller. CONSTITUTION:Respective DMA controllers 13, 23 to 93 in respective arithmetic units 1 to 9 are provided with a function for acquiring/canceling bus using right from respective processors 11, 21 to 91 in the arithmetic units 1 to 9, a function for reading/writing data from/in a memory through a bus, a function for applying an instruction to a DMA controller in another arithmetic unit, a function for receiving an instruction from a DMA controller in another arithmetic unit, a function for executing an instruction from a DMA controller in another arithmetic unit, a function for reading/writing data from a memory in another arithmetic unit, etc., and these functions can be separatively and independently operated. Consequently, inter-memory data transfer between plural arithmetic units in a parallel information processor can be rapidly executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an inter-memory data transfer method in a parallel information processing device, and more specifically, to a data transfer method between mutually communicable arithmetic units provided in the parallel information processing device. This invention relates to a method for speeding up data transfer between memories.

[Conventional technology]

In recent years, two or more arithmetic units are connected by an interconnection path (hereinafter referred to as a bus), and the arithmetic units l-
Parallel information processing devices that transfer data between computers and perform processing in parallel are being widely used. In this type of parallel information processing device, when transferring the contents of a memory (Jl local memory) in a certain arithmetic unit to a memory (local memory) in another arithmetic unit, conventionally each operation is It has been common practice to provide a shared memory for data relay on the bus to be coupled, and to perform data relaying via the shared memory.

FIG. 5 shows a configuration example of a data transfer method between memories in a conventional parallel information processing device. In FIG. 5, a plurality of arithmetic units l-1, 2, . There is. The calculation unit 1 is a central processing unit (C
1)U)11. It consists of a local memory (MEM) 12 and a bus interface circuit (BIF) 15, and is interconnected by one local bus 14. The configurations of the other arithmetic units 2 to 9 are also similar. The bus 104 also includes a shared memory (MEM) that each processing unit 1 to 9 uses for data relay.
For example, when transferring data in the memory 12 in the arithmetic unit 1-1 to the memory 22 in the arithmetic unit 2, the CPUIL in the arithmetic unit 1 transfers the data in the memory 12 to the bus interface circuit 15. , bus 1
04 to the shared memory 10, and instructs the arithmetic unit 2 to access the shared memory 10. ? A.

In response to instructions from the processing unit 1, the CPtJ2L in the processing unit 1-2 extracts data from the shared memory 10 and stores it in the memory 22 via the bus 104 and the bus interface circuit 25. Note that, instead of the shared memory 10, a buffer in a bus interface circuit in the arithmetic units 1 to 1 may be used.

On the other hand, in information processing devices consisting of a single arithmetic unit, memory has traditionally been
Where the concubine accesses d stomach direct memory access.
controller (DMA controller) is used. FIG. 6 shows an example of the configuration, in which a CPU L1, a memory 12, and a DMA controller (DMAC) 13 are connected to a local bus 14.

Regarding the DMA controller, a typical concept has been established, for example, in the LSI (product number 8237A) manufactured by Intel Corporation in the United States, and it performs a series of first-order processing operations. Once it has acquired the right, it sequentially generates memory addresses for both the transmitter and the receiver according to a preprogrammed sequence.
Data is continuously transferred from a specific address in the memory 12 to another specific address in the memory 12, and when a series of data transfers is completed, the right to use the bus is relinquished.

[Problem to be solved by the invention]

In the conventional technology, in a system that uses a shared memory for relaying, a CPU in a certain processing unit once transfers the contents of the memory to the shared memory, and the CPUs in other processing units that know this transfer the contents from the shared memory. A two-step process of retransferring to the memory was required. Of course, such a method has the obvious disadvantages of requiring time for transfer and the need to provide shared memory for relaying, but there are also other drawbacks such as the fact that the shared memory during relaying transfer is It is necessary to arbitrate the right to use the bus to prevent it from being used by an unrelated arithmetic unit, the control circuit for this is complicated, and the bus usage efficiency is reduced. Defects are recognized.

On the other hand, the method using a DMA controller is an effective method for transferring data between memories at high speed without going through the CPU.
(local bus). For this reason, a parallel information processing device having a plurality of operations has the disadvantage that it cannot be used as is.

It is an object of the present invention to be effective in a single arithmetic unit.
An object of the present invention is to provide a method for expanding the functions of the A controller and speeding up data transfer between memories across a plurality of arithmetic units of a parallel information processing device.

[Means to solve the problem]

In order to achieve the above object, in the present invention, a plurality of arithmetic units in which at least a processor, a memory, and a DMA controller are connected by a local bus are connected by an interconnection path, and a DMA controller in each arithmetic unit is connected by an interconnection path. The functions include a function to acquire the right to use the bus from the processor in the processing unit, a function to relinquish the right to use the bus,
A function to read and write memory using the bus, a function to give instructions to a DMA controller of another arithmetic unit,
It has a function of receiving instructions from the DMA controller of the other arithmetic unit, a function of executing instructions from the DMA controller of the other arithmetic unit, a function of reading and writing the memory of the other arithmetic unit, and the like. It is assumed that the functions of can operate separately and independently.

[For production]

The most important feature of the present invention is to obtain bus usage rights from the CPU included in the functions of the DMA controllers 1 to 1 in order to realize inter-memory data transfer across multiple arithmetic units, which conventional DMA controllers could not handle. The handshake function for data acquisition and the data transfer function between memories have been separated, and a function for sending, receiving, and executing commands between other DMA controllers has been added, and these functions can be used alone or in combination. There is a particular thing. As a result, in the past, once a CPU was held, a series of inter-memory data transfers had to be performed within the local bus of that CPU, but now separate and independent unit functions can be transferred as appropriate. By using the combination, it becomes possible to extend the DMA transfer of the entire parallel information processing device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of the present invention. In FIG. 1, a plurality of arithmetic units 1.2. ...
9 are interconnected by an interconnection path (bus) 104. The arithmetic unit 1 includes a CPU 11, a local memory (ME
M)12. It consists of a DMA controller (DMAC) 13 and a bus interface circuit (BIl?) 15, which are interconnected by a local bus 14. The configurations of the other arithmetic units 2 to 9 are also similar. Although FIG. 1 shows a parallel information processing device having nine arithmetic units, generally the number of arithmetic units may be any number as long as it is two or more.

FIG. 2 shows an embodiment of the internal configuration of the DMA controller that is the core of the present invention. For convenience, FIG. 2 shows the DMA controller 13 in the arithmetic unit 1, but The same applies to the controller. 2N, the DMA controller 13 has an internal control register group 130 . CPU hold control circuit 131
, an inter-memory data transfer control circuit 132, an inter-CPU control signal transmission/reception circuit 133, a system bus right acquisition control circuit 134. DMA reception consists of a circuit 135 and an instruction execution control circuit 136.

Below, the DMA controller 13 of the arithmetic unit 1 is the DM
The DMA controller 23 of the arithmetic unit 2 is the side that issues the A transfer request (hereinafter referred to as the requester) and the side that receives it (hereinafter referred to as the target), as shown in FIGS. 1 and 2.
The operation shown in the figure will also be explained.

DMA controller of calculation unit 1! ~Roller 13 is CI)
From ULL to software I-software internal control register group 13
It is assumed that the DMA request is accepted in the form of writing to 0 (in the following explanation, the DMA request is written to circuit 1
This is also common when accepting a DMA request via 35).
When a DMA request is received, first the CPU hold control circuit 1
31 issues a hold request signal to the CPU 11.

In response, the CPU 11 relinquishes the right to use the local bus 14 and at the same time returns a hold permission signal.Next, the system bus right acquisition control circuit 134 passes through the system bus interface circuit 15, omitted in FIG. The system bus arbitration circuit (so-called arbiter; ARB) issues a bus usage right request (R number) for the system bus 104, and the system bus arbitration circuit receives a bus usage permission signal.Up to this point.

The DMA controller 13 of the arithmetic unit 1 is connected to the local bus 1
4 and the right to use the system bus 104.

Next, the DMA controller 13 of the arithmetic unit 1
A control signal is sent from the inter-PU control signal transmission/reception circuit 133 to the arithmetic unit 2. It is assumed that there is one or more types of control signals, and that they are given by setting CPtJl,1 in the internal control register group 130. Here it is.

It is assumed that the control signal is a control command that instructs the DMA controller 23 of the arithmetic unit 2 to acquire the right to use the local bus 24 of the arithmetic unit 2.

Target side DMA controller 23 of arithmetic unit 2
The other CPtJ control signal transmission/reception circuit 233 in
After receiving the control signal, the instruction execution control circuit 23 interprets the control signal and executes the DMA.
The related circuits within the controller 23 are activated. Now, since the control signal is a hold request from the CPU 21,
The CPU hold control circuit 231 issues a hold request signal to the CPU 21. In response, the CPU 21 relinquishes the right to use the local bus 24 and at the same time returns a hold permission signal. , notifies that the execution of the control command by the control signal is completed. In the process up to this point, the local bus 14. system bus 10
4. All local buses 24 become available for use by the DMA controller 13 of the arithmetic unit 1.

Next, the memory-to-memory data transfer control circuit 132 in the DMA controller 13 of the arithmetic unit 1 transfers the requester-side memory address, target-side memory address, address increments, and total number of bytes transferred in the internal control register group 130. Memory addresses for both transmission and reception are generated one after another according to data such as , transfer direction, etc., and data is continuously transferred from a specific address in the memory 12 to another specific address in the memory 22, for example.

After a series of data transfers are completed, the control signal transmission/reception circuit 133 between the requester side DMA controller 13 and other CPUs is transmitted to the target side DMA controller 23 and other CPUs.
DM for the inter-PU control signal transmission/reception circuit 233
A controller 23 issues a control signal commanding local bus 24 to be abandoned. As a result, the instruction execution control circuit 236. The CPU hold control circuit 231 and the like operate, the DMA controller 23 abandons the local bus 24, and the CPU 2L becomes in a state where it can resume the process that was being executed before being held.

Similarly, the DMA controller 23 indicates that the abandonment has been completed.
The DMA controller 13 is notified from the DMA controller 13. The DMA controller 13 further includes a system bus acquisition control circuit 1
34 relinquish the right to use the system bus 104, and subsequently relinquish the right to use the local bus 14, completing the operation.

The above operation sequence is summarized as shown in FIG. 3.

Note that the operation when the DMA controller 13 becomes the receiving side of a DMA transfer request, that is, the target, can be considered by interchanging the relationship between the DMA controllers 13 and 23 in the above explanation, and does not require any special explanation.

In addition, in the above operation description, the DM of the arithmetic unit 1
It has been explained that the control signal sent from the A controller 13 is received only by the DMA controller 23 of the arithmetic unit 2;
3 implies that signals for selecting the arithmetic unit 2 are simultaneously sent out. If you choose the signal or all the processing units,
The inter-CPU control signal transmission/reception circuits of all the arithmetic units except arithmetic unit 1 operate, and the DMA controller of each arithmetic unit acquires the right to use the local bus of all the arithmetic units. ,
For example, if the operation unit number is used in the operation unit selection signal, it is possible to simultaneously write the same data from the memory 12 of operation unit 1 to the memories in all other operation units (referred to as broadcasting). In this case, such data can be broadcast by using one of the unused arithmetic unit numbers as an all arithmetic unit selection signal.

FIG. 4 shows the system configuration of another embodiment of the present invention. That is, this is an example of a configuration in which arithmetic units 1 to 5 are connected to a network. The configuration of each arithmetic unit 1 to 5 is as follows:
It is basically the same as the figure, except that the system bus interface circuit is replaced with a network interface circuit. Even in such m connections between arithmetic units, it is possible to perform inter-memory transfer across arithmetic units in the same manner as the bus connection in FIG.

In the explanations so far, the present invention has been explained as relating to data transfer in the memory address space.
This is similarly effective even when the I10 address space or memory address space and the I10 address space, which are often handled by the controller, coexist. That is, when considering the I10 address space, the I10 address space is
The device is connected and the DMA request from the I10 device is
It may be assumed that the reception is issued to the circuit 135.

〔Effect of the invention〕

As explained above, according to the present invention, CI) U.

A plurality of arithmetic units each having a memory and a DMA controller connected by a local bus are connected by an interconnection path, and the DMA controller of each arithmetic unit has the function of acquiring or relinquishing the right to use the bus from the CPU, and data between memories. By separating the transfer function and adding a function to control other DMA controllers, it is possible to perform high-speed inter-memory data transfer across arithmetic units. In addition, by appropriately combining unit functions such as various bus requests and transfers, data transfer inside and outside the processing unit can be
Flexible, can be realized. Furthermore, by adding types of control signals between arithmetic units, it is also possible to perform more complicated MA transfer control.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, and FIG.
A diagram showing a detailed configuration example of the DMA controller in the diagram,
FIG. 3 is a diagram showing an example of the operation sequence in accordance with FIGS. 1 and 2, FIG. 4 is a schematic configuration diagram of another embodiment of the present invention,
FIG. 5 is a diagram showing an example of the configuration of an information processing apparatus using a conventional memory-to-memory transfer method, and FIG. 6 is a diagram showing an example of the configuration of an information processing apparatus equipped with a conventional DMA controller. L, 2.9...Arithmetic unit, 11.21,91...CPU (central processing unit), 1
2.22.92...Memory, 13.23.93...DMA controller, 14.2
4,94...Local bus, 15.25.95...System bus interface circuit 104...System bus, 130...Internal control register group. 131...CPU hold control circuit. 132...Memory data transfer control circuit, 33...
Controller signal transmission/reception circuit between other CPUs, 34...System bus right acquisition control circuit, 35...DMA reception circuit, 36...Instruction execution control circuit.

Claims (2)

[Claims] (1) In an information processing device in which a plurality of arithmetic units in which at least a processor, a memory, and a DMA controller are connected by a local bus are connected by an interconnection path, the DMA controller in the arithmetic unit includes at least the following:
A function to acquire the right to use the bus from a processor in the processing unit, a function to relinquish the right to use the bus, a function to read and write memory using the bus, and a function to issue instructions to the DMA controller of other processing units. The function of giving
It has a function of receiving instructions from a DMA controller of the other arithmetic unit, a function of executing an instruction from the DMA controller of the other arithmetic unit, and a function of reading and writing the memory of the other arithmetic unit, and ,
These functions can operate separately and independently, and the DMA controller in the first arithmetic unit separates the processor in the first arithmetic unit and the processor in the second arithmetic unit from their respective buses. memory-to-memory data, characterized in that data is read and written between the memory in the first arithmetic unit and the memory in the second arithmetic unit via an interconnection path in the state Transfer method. (2) The memory according to claim (1), wherein the DMA controller in the arithmetic unit has a broadcasting function for writing the same data from the memory in the arithmetic unit to the memories in a plurality of other arithmetic units. data transfer method.