JPH039497B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a multiprocessor system, and more particularly to a storage controller for controlling access to a main storage in which a plurality of processors exist and mutually transmit data.

Prior Art and Problems As shown in Figure 1, there are multiple storage controllers MCU, MCU0 and MCU1 in this example, and each storage controller has multiple access generators (central processing units) CPU0 and MCU1. CPU1 and CPU2
CPU3, main storage MSU0, MSU1, MSU2
and MSU3 are connected, and MCU0 and MCU1 are connected to each other to create a complex system in which data can be transmitted. However, in such a system, if the CPU accesses its own MSU, for example,
When accessing the MSU, it is the same as usual (same as in the case of a single system), but when the CPU accesses the MSU of another system, for example, when CPU0 accesses MSU2 and reads data, it must be controlled as follows. No.

Send access from CPU0 to MCU0 Send access from MCU0 to MCU1 Send access from MCU1 to MSU2 Send data from MSU2 to MCU1 Send data from MCU1 to MCU0 Send data from MCU0 to CPU0 Store this control as pipeline control Part control device
If I were to talk about the MCU, it would be as follows. Figure 2 shows an example of the configuration of an MCU that can perform such control.
P is port, S is selector, PL is pipeline,
DC is the control unit. The subscripts 1, 2, . . . are used to distinguish them from each other, and the ports are essentially registers. To explain the above control using FIG. 2, MCU0 accepts access from CPU0 to interface register P1.

The received access is selected by an access selection circuit (remote MCU priority circuit) S2 for selecting the access to be sent to the MCU1, and is sent to the MCU1 via the port P6. MCU1 accepts the access to interface register P13.

The MCU1 selects the received access using an access selection circuit (MSU priority circuit) S11 for selecting the access to be sent to the main memory, and sends it to the MSU2 via the port P14.
Input to pipeline PL11. Upon receiving this, the MSU2 is activated, enters a read operation, and inputs the read data to the selector S13.

The MCU1 activates the MSU2 through the port P14 as described above, and sends this to the MCU0 via the port P14 and port P4 to notify the MCU0 that it has accessed the MSU2. Selector S1 accepts access to port P4 with the highest priority and inputs it to pipeline PL1. This is to prepare for the data sent from MSU2. When the MSU 2 reads data, it sends it to the selector 13, but the timing is captured by the access stored in the pipeline PL11 and causes the selector S13 to select the data on the MSU 2 side via the control unit DC2. This is the route for ports P18 and P8
Sent to MCU0.

The above access input to pipeline PL1 also captures this timing, and the control unit
The data of port P8 is made to be selected by selector S4 via DC1.

MCU0 sends this data from MCU1 to CPU0 via port P9. MCU1 to MCU
Return access to 0 and from MCU1
It takes a predetermined time to send the read data to MCU0, but since they are both the same, they are mutually exclusive, and there is no problem with timing control by pipeline PL1.

By the way, with this control, MCU0 also sends data from MCU1 to CPU0.
uses a pipeline to send data from MSU2 to MCU0. This means that if you discriminate between your own system and other systems, you will end up using your own pipeline for the other system. Self-system access is as usual as mentioned above, but briefly, for example,
When CPU0 accesses MSU1, the access is passed to P1, and when selected by S1, MSU1 is activated through P5, and the access is passed to PL1.
When the data read by MSU1 is input to S3, DC1 controls S3 to take it in, and passes it to CPU0 via P7, S4, and P9. Pipeline PL1 is used for self-system access, so if it is also used for other-system access, in the case of this other-system access, that access has already been selected and memory access has started, so it must be processed with the highest priority. Therefore, if there is a conflict, access to the own system is forced to wait at selector S1 or S11. For example, in the case of a block fetch request, the CPU requests 64 bytes of data, which cannot be processed in one access, so it is divided into 8 times (issues 8 accesses), etc. Conflicting requests will be forced to wait during this process. In such a complex system, accesses of the own system, which should originally be able to operate independently, are affected by accesses of other systems.

Purpose of the Invention The present invention improves these points and prevents own system access from being affected by other system access, for example.
Access to MSU0 and MSU1 by CPU0 and CPU1 is accessed by MSU0 and MSU1 by CPU2 and CPU3.
This is intended to avoid being affected by access to 1.

Configuration of the Invention The present invention has a basic configuration of a central processing unit, a storage device, and a storage control device connected between them to process memory access requests from the central processing unit, and a plurality of sets of the basic configuration are used for storage control. In a multiprocessor system in which devices are connected, each storage control device determines whether a memory access request from its own central processing unit is directed to its own storage device or to another system's storage device. , when the request is for a storage device in another system, the memory access request is transferred to the storage control device in the other system, and the memory access request is transferred from the central processing unit in the own system and the storage control device in the other system to the storage device in the own system. It is characterized by processing memory access requests, which will be explained next with reference to embodiments.

Embodiment of the Invention FIG. 3 shows an embodiment of the invention, in which the same parts as in FIG. 2 are given the same reference numerals. As is clear from a comparison with FIG. 2, in the present invention, a separate pipeline is provided for processing access to other systems. PL2, PL12
That is it. Also, along with this, selector S
4, S14, ports P9 and P19 are each provided twice.
In addition, ports P4 and P14 are connected to selectors S1 and S11.
Pipeline PL for accessing other systems by separating it from
2. Connect directly to PL12. Next, the operation of this circuit will be described for the case where CPU0 accesses MSU2 to read data.MCU0 accepts access from CPU0 to interface register P1.

The access selection circuit 52 for selecting the access to be sent to the MCU 1 selects the received access and sends it to the MCU 1 via the port P6.
MCU1 accepts the access to interface register P13.

The MCU1 selects the received access using the access selection circuit S11 for selecting the access to be sent to the main memory, and sends it to the main memory MSU2 via the port P14, and also sends it to the main memory MSU2 via the pipeline PL.
11. It also notifies MCU0 via ports P14 and P4.

MCU0 inputs the report (access) from MCU1 on port P4 to pipeline PL2,
Prepare for data sent from MCU1.
When MSU2 is accessed as described above, it is activated, moves to a read operation, and inputs the read data to selector S13. At this time, the input access of the pipeline PL11 operates the selector S13 via the control unit DC2 to take in the read data.

MCU1 sends data from port P18 to port P8 of MCU0.

When read data from MSU2 is sent to port P8, the storage access of pipeline PL2 operates control unit DC1, and data from port P8 is sent to selector S4a from port P9a.
Send it to CPU0 via

In this way, in this circuit, accesses to other systems are processed by the pipelines PL2 and PL12, so accesses to the own system are not obstructed. In this way, in order to completely separate the own system access and the other system access, the selectors S4, S14, etc. are separated for each CPU. As is clear from the above explanation, self-system access refers to access between the CPU and MSU connected to the MCU, and other-system access refers to access between the CPUs and MSUs connected to the MCU.
A device that accesses an MSU connected to it via a CPU, thus taking a route of CPU-MCU-MCU-MSU.

Further, in the embodiment, there are two MCUs, but the present invention can also be applied to a large-scale complex system in which a larger number (n) of MCUs are interconnected. In this case, the pipeline for other systems excludes the own system (n-
1) If one is provided, it will be exclusive to each system, and this will be used for other systems.
This is effective for monitoring the operation of the MCU. That is, accesses by MCUs of other systems to the MSUs of the relevant system enter the (n-1) pipelines for other systems, so the status of the MCUs of other systems can be known by looking at this. As is clear from the above explanation, the pipeline for the own system, for example L1, is the main memory of the own system. In this example, it is the one that processes accesses from the CPU to MSU0 and MSU1, regardless of whether they are in the own system or other systems. , the pipeline for other systems is the MSU issued by the own CPU and connected to the other system MCU.
refers to something that processes access to.

Effects of the Invention As explained above, according to the present invention, the pipeline is divided into one for the own system and one for the other system.
Because the CPU accessed the other system, the other system's
The CPU is no longer forced to wait for access, and the overall processing capacity of the complex system can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system to which the present invention is applied, FIG. 2 is a block diagram showing an example of a storage controller, and FIG. 3 is a block diagram showing an embodiment of the present invention. In the drawing, MCU is the storage controller, CPU is the access generator, MSU is the main memory, PL1, PL
11 is a pipeline for the own system, and PL2 and PL12 are pipelines for other systems.

Claims (1)

[Claims] 1. A basic configuration consisting of a central processing unit, a storage device, and a storage control device connected between them and processing memory access requests from the central processing unit, and a plurality of sets of the basic configuration are used for storage control. In a multiprocessor system in which devices are connected, each storage control device determines whether a memory access request from its own central processing unit is directed to its own storage device or to another system's storage device. , when the request is for a storage device in another system, the memory access request is transferred to the storage control device in the other system, and the memory access request is transferred from the central processing unit in the own system and the storage control device in the other system to the storage device in the own system. A multiprocessor system characterized by processing memory access requests. 2. The multiprocessor system according to claim 1, wherein the plurality of storage control devices operate synchronously using a common clock signal. 3. The memory access request transferred to the storage control device of the other system is held in the storage control device of the own system in synchronization with the storage control device of the other system, and used for waiting control for responses from the other system. A multiprocessor system according to claim 2, characterized in that: 4. Each of the storage control devices described above includes a pipeline control unit that processes memory access requests for its own storage device, and a pipeline control unit that holds memory access requests transferred to storage control devices of other systems. A multiprocessor system according to claim 3, characterized in that: