JPH0150927B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a timer circuit for setting timing necessary for processing in a processing device using a microprocessor.

Prior Art and Problems Processing devices using microprocessors often require various timers to set different timings depending on the processing content in order to carry out the processing. Generally, such a timer sets a predetermined timing by interrupting the microprocessor at regular intervals and using this as a time reference to count the number of interrupts using software. ing. However, in this case, the interrupt time is often chosen to be a relatively large value that does not reduce the processing capacity of the microprocessor, for example, several tens of milliseconds, and therefore the time value obtained by such a timer is For example, it is limited to values such as seconds. Therefore, if you need a timer that is shorter than the above reference time, a timer that requires a time value that is not an integral multiple of the reference time, or a timer that has a narrow tolerance range for the upper and lower limits of the time value, use this method of timer. cannot be used,
A separate timer configured by hardware must be provided.

FIG. 1 shows the configuration of a conventionally used hardware timer circuit. In the figure, 1 is a reference clock source and 2 is a counting circuit.

In FIG. 1, a counting circuit 2 counts the constant cycle reference clock of a reference clock source 1 in response to a counting start signal given from a microprocessor, and sets a counting end flag when a set count value is reached. Turn on and notify the microprocessor.
The count setting value may be settable by software, and notification to the microprocessor may be made by interrupt.

The conventional timer circuit shown in Fig. 1 includes a counting circuit and an interface circuit between the counting circuit and the microprocessor for setting the count value, instructing and notifying the start and end of counting, etc. This is necessary and inevitably increases the complexity and scale of the hardware.

As described above, conventional timers, whether they are based on software or hardware, have many drawbacks.

Purpose of the Invention The present invention is intended to solve the problems of the prior art, and its purpose is to provide accurate processing even for short time values in a processing device having a direct memory access (hereinafter abbreviated as DMA) transfer function. To provide a timer circuit which can be set to various time values, has great flexibility in setting various different time values, and can minimize the increase in hardware for configuring the timer. It is in.

Embodiments of the Invention FIG. 2 shows the basic configuration of a timer circuit of the present invention, in which 5 is a DMM circuit, 6 is a changeover switch, 7 is a reference clock source, and 8 is a peripheral circuit.

The DMA function is generally used to reduce the time required for data transfer by directly transferring data between peripheral circuits and memory without going through registers within the microprocessor. On the other hand, timers required in processing circuits using microprocessors are usually used to specify the time between one process and the next, so when a timer is needed, often has finished data transfer and is in a stopped state. Focusing on this point, the DMA circuit can be used to operate as a timer during a period when the DMA circuit is not transferring data.

In FIG. 2, the changeover switch 6 is normally switched to the peripheral circuit 8 side, and the DMA circuit 5 performs a transfer operation in response to a transfer request signal sent from the peripheral circuit 8. When operating as a timer, for example, when a clock start signal is given from a microprocessor (not shown), the changeover switch 6
is switched to the board clock source 7 side, and performs a transfer operation byte by byte in response to a transfer request signal of a fixed period (t) generated by the reference clock, and when the transfer of a predetermined number of bytes is completed, a predetermined transfer operation is performed. You can know the passage of time.

In this case, if the number of transfer bytes set in the DMA circuit is N, the time from the start of transfer to the end of transfer is Nt, and any time value can be set by arbitrarily setting the number of transfer bytes N. A timer circuit can be realized. Also, the period t of the transfer request signal is 1
This is the time in which a byte of data can be transferred, and is usually a sufficiently short time.

In this way, according to the timer circuit shown in Fig. 2, a short time value can be set, a timer with great flexibility in setting the time value can be obtained, and there is only a slight increase in the hardware required to configure the timer. be. The reference clock source required at this time can be replaced by another clock in the processing device, or can be omitted.

FIG. 3 shows the configuration of an embodiment of the timer circuit of the present invention. In the figure, 11 is a DMA circuit;
12 is a switching gate, 13 is a microprocessor (MPU), 14 is a memory, 15 is a peripheral circuit, 16
is a bus. The DMA circuit 11 consists of a transfer byte number counter 21, an address generation circuit 22, and a bus control circuit 23.

In FIG. 3, prior to starting operation as a timer, the microprocessor 13 sets an initial address value in the address generation circuit 22, and
The number of transferred bytes is set in the transferred byte number counter 21. When the clock start signal is given and the transfer request signal is received, the bus control circuit 23 sends a bus occupancy request signal to the microprocessor 13, and the microprocessor 13 sends a permission signal to the bus control circuit according to the usage status of the bus 16. It is sent back to the circuit 23. The bus control circuit 23 controls the gate 12 in response to a transfer request signal from the reference clock source, thereby setting a transfer address from the address generation circuit 22 to the memory 14, and transmitting data from the peripheral circuit 15 to the memory 14. is transferred. Transfer bytes counter 2
1 is subtracted every time 1 byte is transferred, and at the same time, the address generation circuit 22 adds it every time 1 byte is transferred to sequentially change the address in the memory 14. In this way, data is transferred for the set number of bytes. When the setting value of the byte number setting counter 21 becomes 0,
A signal indicating the end of time measurement is generated, thereby ending the data transfer operation and the operation as a timer. Note that data may be transferred from the memory 14 to the peripheral circuit 15.

Such data transfer is performed by a clock having a predetermined cycle, and therefore, a desired timer value can be set upon completion of transfer of the number of bytes set in the transfer byte number counter. The method of notifying the microprocessor 13 of the completion of transfer is as follows.
The bus control circuit 23 may issue an interrupt to the microprocessor 13, or a flag may be set in the transfer byte number counter indicating that the set value has become 0, and the microprocessor 13 may periodically read this. It may also be known by Note that the purpose of the data transfer in the above operation is to operate the counter in the DMA circuit, so it goes without saying that it is not necessarily necessary to transfer actual data.

Effects of the Invention As explained above, according to the timer circuit of the present invention, in a processing device having a DMA transfer function, a reference clock is supplied to the DMA circuit to perform a DMA operation when no data transfer is performed, and the timer circuit performs a predetermined DMA operation. Since it is now possible to obtain an output indicating the required time elapsed upon completion of the transfer operation of the number of bytes, it is possible to accurately set even short time values, and it also provides flexibility in setting various different time values. It is highly versatile and can minimize the increase in hardware required for existing circuitry to configure the timer.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional timer circuit, FIG. 2 is a diagram showing the principle configuration of the timer circuit of the present invention, and FIG. 3 is a diagram showing the configuration of an embodiment of the timer circuit of the present invention. be. DESCRIPTION OF SYMBOLS 1... Reference clock source, 2... Counting circuit, 5... Direct memory access (DMA) circuit, 6... Reference clock source, 7... Peripheral circuit, 11... Direct memory access (DMA) circuit, 12... Switching gate, 13... Micro Processor CMPU), 14...
Memory, 15... Peripheral circuit, 16... Bus, 21... Transfer byte number counter, 22... Address generation circuit,
23...Bus control circuit.

Claims (1)

[Claims] 1. In a processing device including a transfer byte number counter that counts the number of transferred bytes and a DMA circuit that transfers a preset number of bytes of data to the transfer byte number counter one byte at a time in response to a transfer request signal, When the DMA circuit is given a clock start signal, it performs a 1-byte transfer operation for each transfer request signal generated from the reference clock, and a signal indicating the end of the clock time when the number of bytes set in the transfer byte number counter is completed. A timer circuit that operates as a timer by generating .