JPS59224927A - Time division multiplex digital counter circuit - Google Patents

Abstract

PURPOSE:To optimize the titled circuit for a device requiring lots of independent counter circuits having prescribed time by providing a specific counter, a means for discriminating a count time, a means for setting the count time, a specific counter operation commanding means, a specific counter re-operating means, and a specific counter count end informing means. CONSTITUTION:A counter 11 is driven by a clock phi2 and used to designate a counter number. A switching device 12 is used to switch an output of the counter 11 and an output of a numeral entry device 22 for designating counter. A storage device 13 holds a count value of each counter at that time. A count number of a counter having a counter number designated by the counter 11 is extracted in a numeral entry device 14 for temporary storage. An adder 15 increments this extracted count value by one step and a comparator 17 discriminates whether or not the said count value reaches a designated value in advance. A storage device 18 holds its designating value. Further, a storage device 30 stores whether or not each counter is in operation. Switching devices 19, 31 are the switching devices similar to the said switching device 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is designed to improve the reliability of information transmission by retransmitting a response signal for a certain period of time when a response signal to transmitted information is not returned even after a certain period of time. This relates to a counting circuit.

Conventional devices requiring this fixed-time counting circuit were sufficient to have at most two or three independent counting circuits. Therefore, it was sufficient to arrange 2.3 simple counters, registers, etc.

In recent equipment, the number of independent counting circuits required for °C is no more than two or three, as seen in the control of n-to-n multiplex communication, and some equipment requires as many as 256 independent counting circuits. It is not desirable to use 256 conventional counting circuits in such a device in terms of the hardware configuration.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and provide a time-division multiplexed digital counting circuit that is optimal for a device that requires a large number of independent constant-time counting circuits.

The time division multiplexed digital counting circuit of the present invention has a counting means for a specific counter specified from the outside, a means for determining the counting time specified from the outside, and a means for setting the counting time. The present invention is characterized by comprising a specific counter operation instruction means, a specific counter stop means, a specific counter reactivation means, and a specific counter counting end notification means.

In FIG. 1 showing an embodiment of the present invention, 11 is a counter driven by a clock φ= and used to specify a counter number, and 12 is an output of the counter 11 and a position for specifying the counter. A switch 13 is used to switch the output of the counter 22, and a storage device 13 is a storage device for holding the current count value of each counter. Each counter is configured on the storage device 13. ),
The count value of the counter number designated by the counter 11 is taken out to the temporary holding digitizer 14. 15 is an adder for increasing the extracted count value by one step.

A comparator 17 determines whether the count value has reached a predetermined value. 18 is a storage device for holding the specified value. 19 is a switch similar to switch 12; 30 is a storage device that stores whether each counter is in operation; 31 is a switch similar to switch 19;

When the operating counter reaches a predetermined value, if the output of the storage device 30 is "1", a timing pulse 39 is generated.
passes through the gate circuit 27 and sets the flip-flop 28, thereby being notified to the outside as a time-up signal (UR,).

To start each counter, first clock pulse C
At P1, the specified value on the path line B1 is held in the digitizer 21, then the counter number is held in the digitizer 22, and later the mode specified value is held in the digitizer 23. It is possible to operate the device. 24 is a decoder for determining the mode specified by the contents of the register 23.

42, 43, and 44 are control signals indicating start mode, stop mode, and restart mode, respectively. 25.2
6 is a flip-flop for synchronizing external signals. Reference numeral 32 is a digitizer that outputs a time-up signal when the counter in operation reaches a specified value, and notifies the outside of which counter the signal comes from. 35,
36, 37°, 40, 41, and 46 are timing pulses that will be explained in the detailed description of the operation.

Next, the details of the operation will be explained in FIG.

φ2 is a clock obtained by dividing φ1 by two. Counter 11 is counted and its output 100 designates an individual counter number. Reference numeral 101 is an output signal from the storage device 3°, which indicates whether or not the counter designated by the counter 11 is in operation. 102
is an output signal of the storage device 13, which indicates the current count value of the counter specified by the counter 11. 103 is an output signal of the storage device 18 and is a constant set in the counter specified by the counter 11. As shown in the output 104 of the storage device 13, the signal is held in the digitizer 14 by the timing pulse 36.

The current count value is compared with a constant value, and if they match, the timing pulse 39 is passed through the gate circuit 27 to become a time-up notification pulse 106, and at the same time, the counter number n is held in the digitizer 32. If the counter is in operation and does not match the constant value, the current count value is incremented by +1 in the +1 adder 15 and its output 109 is written to the storage device 13 by a pulse 109.

Figure 3 shows how to operate this time division multiplex timer 5- This shows the timing relationship of the external signals required.

According to the present invention, it is possible to reduce the size and cost of a device that requires a large number of counting circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are time charts showing the operation of FIG. 1. 1]...Counter, 12...Switcher, 1
3...Storage device, 14...Number register, 1
5...Adder, 16...Switcher, 17
...Comparator, 18...Storage device, 19
...Switching L21, 22, 23... Digitizer, 24... Decoder, 25, 26...
・Flip-flop, 27... Gate circuit, 2
8.°° flip-flop, 29...-switcher,
30...Storage device, 31...Switching device,
32...Numerizer. 6- Figure 2 3? Figure 3 P3 P3

Claims (1)

[Claims] A counting means for a specific counter specified from the outside, a means for determining the counting time specified from the outside, a means for setting the counting time, a specific counter operation instruction means, and a specific counter stop. 1. A time division multiplexed digital counting circuit comprising: a means for reactivating a specific counter; and a means for notifying completion of counting of a specific counter.