JPS6378267A - Run away detecting circuit for multiprocessor - Google Patents

Abstract

PURPOSE:To detect run away by simple constitution by resetting an FF according to a control signal from the last processor and if resetting is not made within a specified time, judging it as the state of run away. CONSTITUTION:Plural subprocessors 1-1-1-n are connected to transfer control signals successively. When a control signal is applied to the processor 1-1 that makes give and take of data first between a master processor 2, an FF 3 is set by the control signal. When the control signal transferred successively by completion of processing is outputted from the processor 1-n that makes transfer of data last, the FF 3 is reset by the control signal. When it is discriminated by a processor 2 that FF 3 is not reset after setting of FF 3, sending of the control signal is stopped. Thereby, a counter section 4 is not cleared, and accordingly, the content of count becomes large, and when it exceeds a specified value, a run away detection signal is outputted.

Description

[Detailed Description of the Invention] [Summary] A flip-flop is set by a control signal from a master processor, this control signal is sequentially transferred to a plurality of sub-processors, and the flip-flop is reset by a control signal from the last sub-processor. However, if it is not reset within a predetermined period, it is determined that a runaway state has occurred, and runaway of a multiprocessor can be detected with a simple configuration.

[Industrial application field]

The present invention relates to a runaway detection circuit for a multiprocessor including a master processor and a plurality of subprocessors.

In a multiprocessor in which a plurality of subprocessors each control a plurality of devices, and the subprocessors are controlled by a master processor, it is desired to be able to detect runaway with a simple configuration.

[Conventional technology]

Conventionally, as a method for monitoring whether the control state by the processor is normal or not, for example, when it is detected that the access address is not within a predetermined range of the program memory, it is determined that the program has runaway and an alarm signal is sent. If the soft clock generated by the interrupt processing is compared with the hard clock, and the soft clock is not generated for the hard clock,
There are methods such as determining that there is an abnormality and outputting an alarm signal.

Therefore, even in a multiprocessor, runaway detection can be performed by providing the above-mentioned monitoring means for each processor.

[Problem that the invention seeks to solve]

As a runaway detection means for a multiprocessor, if a runaway detection means is provided for a processor as described above, it will be possible to detect which processor has runaway. If the number increases, a correspondingly large number of runaway detection means must be provided, which has the drawback of increasing the size and cost of the device.

An object of the present invention is to enable runaway detection with a simple configuration in a multiprocessor consisting of a master processor and a plurality of subprocessors.

[Means for solving problems]

The multiprocessor runaway detection circuit of the present invention utilizes the fact that control signals from a master processor are sequentially transferred to subprocessors to exchange data, and will be explained with reference to FIG.

A plurality of sub-processors 1-1 to 1-n each control a plurality of devices (not shown), and process information common to these sub-processors 1-1 to 1-n. In a multiprocessor including a master processor 2 that sequentially controls each of the processors 1-1 to 1-n, a control signal to the sub-processor 1-1 that first exchanges data with the master processor 2. The flip-flop 3 is set by the control signal from the sub-processor 1-n which finally receives and receives data, and the flip-flop 3 counts signals of a predetermined period from the timer section 5 and the like, and receives the control signal from the master processor 2. The counter section 4 is cleared by the counter section 4.

When the master processor 2 identifies that the flip-flop 3 is not reset within a predetermined period after being set, it stops sending out the control signal. As a result, the counter section 4 is not cleared, so the count becomes equal to or greater than a predetermined value, and a runaway detection signal is output.The runaway detection signal resets, for example, the flip-flop 6, and its d terminal output signal becomes "1". This is applied to the master processor 2 as an interrupt signal for detection of runaway. Note that the runaway detection signal from the counter section 4 can also be applied to the master processor 2 as an interrupt signal for detecting runaway.

[Effect]

The plurality of sub-processors 1-1 to l-n are connected to sequentially transfer control signals, and the sub-processor 1 first exchanges data with the master processor 2.
-1, when a control signal is applied to the flip-flop 3, the flip-flop 3 is set by the control signal, and when the control signal that is sequentially transferred upon completion of processing is finally output from the subprocessor 1-n that transfers data, the flip-flop 3 is set by the control signal. The flip-flop 3 is reset by the control signal.

If the master processor 2 identifies that the flip-flop 3 will be reset and then cleared after a predetermined period of time has elapsed after being set, it will send out the next control signal, but if it determines that it will not be reset even after the predetermined period of time has elapsed, the next control signal will be sent. Stop sending control signals. As a result, the counter section 4 is not cleared, and when the count increases and exceeds a predetermined value, a runaway detection signal is output. Accordingly, an interrupt signal is applied to the master processor 2, and, for example, a system reset is performed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention.
1l-n is a sub-processor (SPU), 12 is a master processor (MPU), 13 is a flip-flop, 14
is the decoder (DEC), 15 is the watchdog timer circuit (WDT), 16 is the main memory (MM),
17 is a random access memory (RAM), 18 is a main bus, 19 is a sub-bus, 20 is an inverter, 21-
24 is a gate circuit, 25 is a driver, 26 is a light emitting diode, 27 is a current limiting resistor, and ■ is a power supply voltage.

The sub-processors 11-1 to 11-n correspond to the sub-processors 1-1 to 1-n in FIG. 1, the master processor 12 corresponds to the master processor 2 in FIG. It corresponds to the flip-flop 3 in FIG.
2 corresponds to the timer section 5 in FIG. 1, and the watchdog timer circuit 15 and master processor 12 realize the functions of the counter section 4 and flip-flop 6 in FIG.

The sub-processors 11-1 to 11-n control and monitor a plurality of devices (not shown), and control each device based on monitoring information, or transfer monitoring information to the master processor 12. , and controls each device according to control information from the master processor 12.

Various information is transferred between the sub-processors 11-1 to 11-n and the master processor 12 via the random access memory 17.

The master processor 12 outputs a specific address for forming a control signal to the main bus 18 at regular intervals, and the specific address is decoded by the decoder 14. When the decoded output is "1", the gate circuit 21.22 is opened, and its rising edge is used as an interrupt signal for the master processor 12. When the decode output is "O", it becomes a control signal to the first sub-processor 11-1 via the inverter 20, and the gate circuits 23 and 24 are opened.

The sub-processor 11-1 operates using the rise of this control signal as an interrupt signal, and reads the control information written from the master processor 12 into a predetermined area of the random access memory 17 from the gate circuit 24 via the sub-bus 19. ,
Also, monitoring information and the like are written from the sub-bus 19 to a predetermined area of the random access memory 170 via the gate circuit 23, and when the processing is completed, a control signal is transferred to the next sub-processor 11-2 as an interrupt signal.

This sub-processor 11-2, as in the above case,
It reads control information written in a predetermined area of the random access memory 17, writes monitoring information, etc., and upon completion of the processing, transfers the control signal to the next sub-processor 11-3.

The control signal is sequentially transferred to the sub-processors, and information is exchanged with the master processor 12. When the last sub-processor 11-n finishes exchanging information with the master processor 12, the control signal is transferred to the sub-processors. flip flop 1
It is applied to the reset terminal R of No. 3. Therefore, even when a large number of sub-processors are provided to perform distributed control, desired information can be smoothly exchanged with the master processor 12 via the random access memory 17.

In addition, the flip-flop 13 receives a control signal from the set terminal S for the sub-processor 11-1 which initially sends and receives information.
A control signal from one sub-processor 1f-n that sends and receives information is added to the reset terminal R.
is added to and reset, and the state of its output terminal Q is
It is read by the master processor 12 via the main bus 18.

In this case, if it is normal, the sub-processors 11-1 to 11-n would sequentially exchange information within a predetermined period, so the flip-flop 13 would be reset, but the sub-processors 11-1 to 11-n would If any one of them is in a runaway state, the control signal will not be applied to the subsequent sub-processors (therefore, the last sub-processor 11-n will not output the control signal, and the flip-flop 13 will be reset. Therefore, the set flip-flop 13 becomes dusty after a predetermined period of time.

If not set, subprocessors 11-1 to 11
It can be determined that one of -n has gone out of control.

In addition, the inverter 2 is connected to the output terminal Q of the flip-flop 13.
A light emitting diode 26 is connected to the light emitting diode 26 through a terminal 5, and when the output terminal Q becomes "1", a current flows through the light emitting diode 26 due to the voltage of +■, and it emits light. Sub processor 11
When -1 to 11-n are normal, the output terminal Q of the flip-flop 13 becomes "1" and "0" at a constant cycle, and when abnormal, it continues to be "1". In addition, if the master processor 12 is abnormal, the control 'B (fi signal is not sent out, so the light emitting diode 2
6 makes it possible to display whether or not it is normal.

Also, the watchdog timer circuit 15 is connected to the sub-processor 1.
When all 1-1 to 11-n are operating normally, the master processor 12 resets it via the main bus 18 based on the rise of the output signal of the decoder 14. If this reset is not performed, , after a predetermined period of time has elapsed,
An interrupt signal is applied to the master processor 12 as a runaway detection, and the operation corresponds to the configuration consisting of the counter section 4 and flip-flop 6 in FIG. 1.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, in which (a) shows the control signal for the decoded output of the decoder 14, (b) shows the operating period of the master processor 12, and (C1 to (e) shows the sub-processor 11). -1.11-2.11-H operation period, (
f) to (h) show the states of the output terminal Q of the flip-flop 13, (f) is normal, and (g) is the state of the sub-processor 1.
When any one of 1-1 to 11-n is abnormal, (h) indicates a case where the master processor 12 is abnormal.

The control signal is the master processor 1 as shown in (al).
Depending on the specific address from 2, the period T1 of “1” and “O
The control signal can be easily generated by providing the decoder 14 with, for example, a launch function and using a specific address for switching between the periods TI and T2. During the period TI, the gate circuits 21 and 22 are opened, and the rise of the gate circuits serves as an interrupt signal to the master processor 12, so the master processor 12 interrupts each of the sub-processors 11-1 to 11-n.
The control information for the sub-processors 11-1 to 11-n is written to the corresponding sub-processors 11-1 to 11-n of the random access memory 17 via the gate circuit 21.
Read information from n from random access memory 17. The period T1 of the control signal is set to be slightly longer than the operating period Tm of the master processor 12.

In the next period T2, the "0° control signal" is inverted by the inverter 20 and becomes "1", and its rising edge becomes an interrupt signal to the first sub-processor 11-1. 24 is opened and the flip-flop 13 is set.Then, the sub-processor 11-1 reads control information from the master processor 12 from the random access memory 17, writes monitoring information, etc. to the random access memory 17, and executes the processing. Upon completion of the subprocessor 11-2, the control signal is transferred to the next subprocessor 11-2.

Therefore, the sub-processors 11-1 to 11-n (C1
~ (operates sequentially as shown in Ql, so that all access operations to the random access memory 17 can be completed,
A period T2 is set.

The flip-flop 13 is connected to the first sub-processor 11-
1 is set at the rising edge of the control signal applied to the subprocessor 11-n, and during normal operation, it is reset when the last sub-processor 11-n completes its operation, so its output terminal Q (like fl,
After being set, it is repeatedly reset within a predetermined period of time. In addition, the master processor 12 reads the state of this output terminal Q, and when it determines that it is normal, outputs a specific address for the next control signal, which is decoded by the decoder 14 and becomes a control signal, and the rising edge of the decoded output At this timing, the watchdog timer circuit 15 is reset from the master processor 12 via the main bus 18.

After the flip-flop 13 is set, if it is not reset after a predetermined period of time as shown in (g), the master processor 12 sets the sub-processors 11-1 to 11-.
It is determined that any one of n is out of control, and a specific address for switching from period T1 to period T2 is not output.

In other words, sending out the control signal is stopped. Therefore, the timing of the rise of the control signal is
As a result, the watchdog timer circuit 15 will not be reset.

The watchdog timer circuit 15 is connected to the master processor 1.
2, when the period T3 (T3>T1+T2) has elapsed, an interrupt signal is applied to the master processor 12 to cause the system to be reset.

In addition, if the master processor 12 goes out of control, the control signal with a constant period is not output, so the flip-flop 13 remains in the reset state for m consecutive times, so its output terminal Q becomes (h).
“0” continues as shown in FIG. In this case as well, after the period T3 (T3>T1+T2) has elapsed, an interrupt signal is applied from the watchdog timer circuit 15 to the master processor 12 to cause the system to be reset.

As described above, it is possible to distinguish between a case where any of the sub-processors 11-1 to 11-n goes out of control and a case where the master processor 12 goes out of control.

FIG. 4 is a block diagram of an embodiment applied to an exchange according to the present invention, in which the same reference numerals as in FIG. 2 indicate the same parts, and 31.3
2 is a gate circuit, 33 is a speech path control circuit (SPC), 3
4 is the communication network (NW), 35 is the subscriber circuit (1, C,), and 36 is the various trunks ('T'RK).
), 37 is a runaway detection circuit.

Each of the sub-processors 11-1 to 11-1 controls and monitors a plurality of subscriber circuits 35, and information on detecting calls, responses, etc. from subscribers is sequentially added, including information on their accommodation locations. According to the control signal, sub-bus 19.
The data is written into a predetermined area of the random access memory 17 via the gate circuit 32. Also random access memory 17
The subscriber circuit 35 is controlled according to the control information read from the subscriber circuit 35.

Further, each of the sub-processors 11-j to 11-n controls and monitors a plurality of trunks 36, and the called party response information, incoming call information, etc. are sent to the sub-bus 19 according to control signals.
．． Random access memory 17 via gate circuit 32
is written in a predetermined area of the random access memory 1.
The trunk 36 is controlled according to the control information read from the trunk 36.

Master processor 12 includes gate circuits 31 . Information in the areas corresponding to sub-processors 11-1 to 11-n is sequentially read from the random access memory 17 via the main bus 18, and control information is written accordingly. The master processor 12 also adds control information such as setting a communication path and opening a communication path to the communication path control device 33 based on the calling information, called party information, etc.
The channel control device 33 controls the channel network 34 according to the control information, and controls the subscriber circuit 35 and the trunk 36.
Set up or open a communication path between the two parties.

A control signal for switching between the operation of the master processor 12 and the operation of the sub-processor is output from the decoder 14, and when a 1'' control signal is applied to the first sub-processor 11-1, the control signal is sent to the gate circuit 32. and the runaway detection circuit 37, and the last sub-processor 11-
The control signal from n is sent to the reset terminal R of the runaway detection circuit 37.
(corresponding to the reset terminal R of the flip-flop 3.13 in FIG. 1 or 2).

Therefore, as explained with reference to FIG.
When no control signal is output from n, or for a predetermined period or more,
When no control signal is applied to the first sub-processor 11-1, a runaway detection signal is output, and an interrupt signal is applied to the master processor 12 via the main bus 19 to cause the system to be reset.

〔Effect of the invention〕

As described above, in the present invention, a plurality of sub-processors 1-1 to l-n sequentially transfer control signals, and the sub-processors that have received the control signals exchange data with the master processor 2. In a multiprocessor, a flip-flop 3 is first set by a control signal applied to the subprocessor 1-1 that transfers data, and is finally reset by a control signal from the subprocessor 1-n that transfers data. When the master processor 2 determines that the flip-flop 3 is not reset even after a predetermined period of time has passed after being set, it stops sending out the control signal, so the watchdog timer circuit 15 is reset by this control signal. etc., the count content of the counting unit 4 exceeds a predetermined value,
A runaway detection signal is output. Therefore, runaway in the plurality of subprocessors 1-1 to 1-n can be detected with a simple configuration. Further, even if the master processor 2 goes out of control, the reset state of the flip-flop 3 continues, so there is an advantage that it can be easily detected.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of the embodiment of the invention, and Fig. 4 is an implementation applied to an exchange of the invention. FIG. 2 is an example block diagram. 1-1 to 1-n, 11-1 to 11-n are sub processors (SPU), 2.12 is master processor (MPU)
, 3.13 is a flip-flop, 4 is a counter section, 5
is a timer section, 6 is a flip-flop, and 14 is a decoder (
DEC), 15 is a watchdog timer circuit (WDT).
), 16 is main memory (MM), 17 is random access memory (RAM), 18 is main bus, 1
9 is a sub-bus, 20 is an inverter, and 21-24 are gate circuits.

Claims (1)

[Claims] A plurality of sub-processors (1-1 to 1-n) each controlling a plurality of devices;
- a master processor (2) that processes common information of the subprocessors (1 to 1-n) and sequentially controls each of the plurality of subprocessors (1-1 to 1-n); , is set by a control signal applied to the sub-processor (1-1) that first transfers data to and from the master processor (2), and is controlled by the sub-processor (1-n) that transfers data last. A flip-flop (3) that is reset by a signal, and a flip-flop (3) that counts signals of a predetermined period and is connected to the master processor (3).
2) and a counter section (4) that is cleared by the control signal applied to the sub-processor (1-1) that first transfers data to and from the sub-processor (1-1); When the master processor (2) identifies that it is not reset after a predetermined period of time after being read and set;
The present invention is characterized in that the transmission of the control signal is stopped, and when the count section (4) is not cleared due to the stoppage of the transmission of the control signal, and the content of the count exceeds a predetermined value, a runaway detection signal is output. Multiprocessor runaway detection circuit.