JPH07168723A - External event detecting method for computer system - Google Patents

Abstract

PURPOSE:To reduce overhead caused by the detection processing of an external event such as an input/output at a computer system. CONSTITUTION:Generated external events 1-n are held by an external event holding circuit 21, and an event generation report signal S1 corresponding to each event is transmitted to a delay circuit 22. The delay circuit 22 delays an interrupt signal S2 to be transmitted to a CPU 1 for fixed time and receives the plural events during that time. The CPU 1, which receives the interrupt signal S2, successively processes the received plural events and when the processing is completed, the CPU transmits a reset instruction S3 to a reset circuit 23 and resets the external event holding circuit 21 and the delay circuit 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external event detecting method for a computer system, and more particularly to an external event detecting method for a computer system for detecting a large number of events.

[0002]

2. Description of the Related Art Conventionally, the external event detection method of this type of computer system is an interrupt method that interrupts a central processing unit (hereinafter referred to as "CPU") for each external event that occurs, such as "August 1992 As shown in "Basic Technology of Exchange Control Program P.862 to P.869" of the Institute of Information and Communication Engineers, Vol.
There is a look-in method in which the PU periodically detects whether or not an external event has occurred.

[0003]

In the conventional interrupt method of the external event detection method, an interrupt is generated in the CPU each time an external event occurs, and therefore the performance of the CPU is degraded due to the control shift. It increases in proportion to the number of events that occur. Therefore, when a large number of external events are processed, there is a drawback that the performance of the entire computer system is deteriorated. In addition, the look-in method has a drawback in that when the number of events is large because the CPU actively detects the occurrence of each event, the fixed performance deterioration of the CPU, which is proportional to the number of event factors, is proportional to the load amount. It was

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to reduce the CPU load for detecting a large amount of external events. Therefore, the external event detection method for a computer system according to the present invention is an external event holding means for holding the occurrence of each of a plurality of external events in the computer system and outputting a signal for notifying the event occurrence corresponding to the external event, A delay means for receiving the output of the external event holding means, delaying and outputting the logical talk of the output as an interrupt signal, and a reset signal for the external event holding means and the delay means in response to a reset command of the CPU. And a reset means for providing the CPU,
When the interrupt signal is received, the external events held in the external event holding means are sequentially processed, and the reset command is output when the processing is completed.

[0005]

For this reason, when notifying each external event to the CPU, delay the delay within an allowable time, and perform group processing including other events that occurred within the delay time when the CPU analyzes the delay event. Can reduce the overhead per event.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an external event detecting system of a computer system according to the present invention.

In FIG. 1, the delay interrupt circuit 2 includes an external event holding circuit 21, a delay circuit 22 and a reset circuit 23.
have.

The external event detection circuit 21 holds a plurality of external events 1 to n that have occurred and outputs an event occurrence notification signal S1 for notifying the occurrence of the event corresponding to each event.

When the delay circuit 22 receives the event occurrence notification signal S1 output from the external event holding circuit,
The interrupt signal S2 to the CPU is delayed by an allowable time and then output.

The reset circuit 23 receives the reset command S3 sent from the CPU 1 which has completed the process corresponding to the external event via the processor bus 3, and the external event holding circuit 21 holds the information of the external event. And a reset signal S5 for resetting the operation of the delay circuit 22.

Next, the operation of the embodiment of the present invention thus constructed will be described.

External events 1 to n for notifying the CPU 1 of the end of the input / output operation are temporarily held in the external event holding circuit 21. When held, the output of the external event holding circuit 21 is activated and notified to the delay circuit 22 as an event occurrence notification signal S1.

In the delay circuit 22, when any input corresponding to an external event is activated, an output in which information input during that time is aggregated is activated after a certain period of time, which is allowable for processing, is activated and the CPU 1 Interrupt signal S2.

As a result, the CPU 1 executes the interrupt process,
Not only the external event that is the direct factor of the interrupt, but also the external event factors that are generated within the delay time and are held in the external event holding circuit 21 are inspected and each processing is performed.

When the processing corresponding to each event is completed,
To reflect the completion of the process, the CPU 1 sends a reset command S3 to the reset circuit 23 via the processor bus 3.

In the reset circuit 3, the reset command S
Each circuit of the external event holding circuit 21 whose processing is completed by decoding 3 is reset to an inactive state.

When the CPU 1 completes the interrupt processing for each event, the reset circuit 23 resets the activated delay circuit 22 based on the reset command S3 sent from the CPU 1. As a result, the output of the delay circuit 22 becomes inactive and waits for an external event to occur.

After that, when any one of the outputs of the external event holding circuit 21 is activated, the delay circuit 22 again activates the output after a certain time and interrupts the CPU 1.

In this way, the delay interrupt circuit 2
Without interrupting the CPU 1 every time an external event occurs, the external events that occur during the delay time of a fixed time are collectively processed by one interrupt.

[0021]

As described above, according to the external event detecting method for the computer system of the present invention, the interrupt signal generated upon the occurrence of an event is delayed and notified, so that one interrupt process occurs during the delay. Other interrupt factors can be processed together.

Statistically, an external event is bundled to notify an interrupt, the number of interrupts is reduced, the processing required for the interrupt processing of the CPU is reduced, and as a result, the performance of the system can be improved. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an external event detecting method for a computer system according to the present invention.

[Explanation of symbols]

 1 CPU 2 Delay Interrupt Circuit 3 Processor Bus 21 External Event Holding Circuit 22 Delay Circuit 23 Reset Circuit S1 Event Generation Notification Signal S2 Interrupt Signal S3 Reset Command S4, S5 Reset Signal

Claims (1)

[Claims] 1. A computer system, wherein external event holding means for holding the occurrence of each of a plurality of external events and outputting a signal for notifying the event occurrence corresponding to the external event, and receiving the output of the external event holding means. A delay means for delaying and outputting the logical sum of the outputs as an interrupt signal, and a reset means for receiving a reset command from the central processing unit and giving a reset signal to the external event holding means and the delay means. When the central processing unit receives the interrupt signal, the central processing unit sequentially processes the external events held in the external event holding means, and outputs the reset command when the processing is completed. Detection method.