JPH0387962A - Inter-processor communication control method - Google Patents

Abstract

PURPOSE:To attain the smooth and highly efficient communication between processors by deciding autonomously the propriety of receiving the communication information from other processors based on the processor state, i.e., the contents of a register and informing a transmission processor of the reason for rejection of receiving the communication information if decided to 'No'. CONSTITUTION:A register 206 (406) which stores the state of a processor 10 (30) contained in an inter-processor communication equipment 20 (40) grasps the normal state, the congestion state, the initialization state, the faulty state, etc., of the reception processor 30 (10) based on the contents of the register 206 (406) in the reception mode of the equipment 20 (40) to decide the propriety of reception. Thus the propriety of reception is decided in accordance with the degree of congestion and the priority of the communication information if the processor 10 (30) is kept in a congestion state. When the rejection of receiving the information is decided, the equipment 20 (40) informs the transmission processor 10 (30) of the reason for rejection. Thus the processor 10 (30) can decide the propriety and the necessity for retransmission of the information based on the received reason. Meanwhile the processor 30 (10) can reject the reception of the information without performing any reception process. Thus the smooth and highly efficient communication is attained between both processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling communication between distributed processors in a distributed controlled data processing system.

[Conventional technology]

The conventional inter-processor communication control method is as described in the book "Digital Exchange Method" (published by Institute of Electronics and Communication Engineers, March 15, 1985), pages 132 to 135.
The inter-processor communication device does not have a function to grasp the status of the receiving processor, and has achieved inter-processor communication by simply granting the right to use the inter-processor communication bus to the sending processor and the receiving processor. For this reason, the receiving processor is forced to perform reception processing during congestion, which accelerates the congestion.Also, because the receiving processor cannot receive data during failure or initialization, there is no response from the inter-processor communication device. Because it was visible, it was a waste of time to identify the non-response, and since the transmitting processor could not grasp the reason for the non-response, appropriate processing could not be taken.

Furthermore, during congestion, the receiving processors refuse to receive all communication information, and after the congestion recovers, they resume reception all at once, so there is a risk that congestion will occur again.

[Problem to be solved by the invention]

In the above conventional technology, since the inter-processor communication device does not have a function to grasp the status of the receiving processor, the receiving processor accelerates the congestion by receiving processing when it is congested, and furthermore, it is not possible to take appropriate measures when the receiving processor does not respond. There was a problem.

In addition, the receiving processors that are congested will refuse to receive all communication information, and once the congestion has recovered, they will immediately resume receiving, so there is a risk that congestion will occur again.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a smooth and highly efficient inter-processor communication control method that grasps the status of a receiving processor.

[Means to solve the problem]

1. In order to achieve the above object, an inter-processor communication control method according to the present invention includes an inter-processor communication device equipped with a register for identifying the state of each processor, in which each processor registers its own state, and communicates with others. The inter-processor communication device autonomously determines whether reception from the processor is possible based on the contents of the register, and if not, notifies the transmitting processor of the reason, so that the transmitting processor determines whether retransmission is possible and whether it is necessary. This allows the receiving processor to reject reception without performing reception processing, thereby realizing smooth and highly efficient inter-processor communication.

2. In addition to providing the registers mentioned in the above means 1,
The status 3219 sent from each processor is divided into levels according to the degree of processor congestion, and communication information is also prioritized from the viewpoint of the importance and urgency of the information. Furthermore, communication information is classified into inquiries and responses, and responses are given priority over inquiries. As a result, the inter-processor communication device autonomously determines whether reception is possible based on the degree of congestion state registered from each processor and the priority level of the communication information. By determining this, high-priority communication information can be received even during congestion, and there is no fear of re-congestion due to simultaneous reception restarting after congestion recovery. The above congestion control realizes highly efficient inter-processor communication.

3. When the inter-processor communication control device autonomously determines reception rejection using the method described in 2 above, it determines the reason for reception rejection and whether retransmission is possible, based on the contents of the processor status identification register and the priority of the communication information. In this case, by providing the inter-processor communication control device with a function of notifying the transmitting processor of the retransmission timing, the transmitting processor can easily respond to the congested processor.

[Effect]

1. The above-mentioned inter-processor communication control method uses a register that stores the state of each processor included in the inter-processor communication device to determine whether the state of the receiving processor is normal, during congestion, or initial when the inter-processor communication device is in a receiving operation. If the processor that determines whether reception is possible or not by ascertaining from the contents of the register whether a setting is in progress or a failure is occurring is congested, it determines whether reception is possible according to the degree of congestion and the priority of the communication information. If not, the inter-processor communication device notifies the transmitting processor of the reason, so that the transmitting processor can determine whether or not retransmission is possible and whether retransmission is necessary based on the reason notification, and the receiving processor can also avoid performing reception processing. This enables smooth and highly efficient communication between processors. 2. In the case of reception refusal, the inter-processor communication control device notifies the transmitting processor of the reason and whether or not retransmission is possible or the retransmission timing.This makes it easy for the transmitting processor to respond and enables smooth and highly efficient inter-processor communication. enable.

〔Example〕

Embodiment 1 An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIGS. 1 and 3 are diagrams showing the system configuration of a distributed control data processing system and the hardware configuration of an inter-processor communication device, showing an embodiment of the inter-processor communication control method according to the present invention. In FIG. 1, the distributed control data processing system includes a processor 10.30, an interprocessor communication device 20.40, and a bus arbiter (bus contention circuit) 50.
and a unibus 60 that connects these devices. The inter-processor communication device 20.40 includes reception memories 201, 401 and gate circuits 202, 203, 4.
02, 403, decoder 204, 404, reception buffer register 205, 405, processor status register 206, 406, decoder 207, 407, gate circuit 208, 408, reception memory 209, 409, transmission buffer register 210 and 410, respectively.

In FIG. 3, there is no inter-processor communication control device in the system configuration, and the processor 10.30 is connected to the central control bag 5t11.
．． 31 and communication control circuit 21.41,
Other points are the same as in FIG. 1.

An example of the operation when the processor 10 communicates with the processor 30 in the above configuration will be described. When the processor 10 writes the transmission information to the transmission memory 209 of the inter-processor communication device 20 or the communication control circuit 21 (FIG. 3), the transmission information is sent to the transmission buffer register 210. The transmission buffer register 210 receives the right to use the bus from the bus arbiter 50 and sends transmission information to the unibus 60. The functions of the bus arbiter 5o are presented on pages 134 to 135 of the book "Digital Exchange System", which is shown in the conventional example.

This transmission information is received by the reception buffer register 405 of the inter-processor communication device 40 or the communication control circuit 41 (FIG. 3), and its address is decoded by the decoder 404 to determine that it is inter-processor communication information to the processor 30. be judged. At this time, the gate circuit 403 operates,
An attempt is made to send communication information to reception memory 401. When one processor 30 is operating normally, the fact that it is in a normal state is recorded in the processor state register 406, and the decoder 407 recognizes this state and operates the gate circuit 402. As a result, the transmission information from the processor 10 is sent from the reception buffer register 405 to the reception memory 40↓ via the gate circuits 403 and 402.
Communication to processor 30 is complete. The above is the communication operation when the processor 30 is in a normal state. Next, the operation when the processor 30 is not in a normal state will be explained.

Next, the processor 30 is not normal and is congested.

During initialization, during failure, etc., different codes are registered in the processor status register 406 so that each status can be identified. At this time, as described above, the transmission information from the processor 10 is sent by the inter-processor communication device 20 or the communication control circuit 21 (FIG. 3) to the inter-processor communication device 40 or the communication control circuit 41 (FIG. 3) through the unibus 60. When the information is received by the reception buffer 7 register 405, the information is about to be sent to the reception memory 401 via the gate circuit 403. However, the processor state stored in the processor state register 406 is decoded by the decoder 407 and is not normal, so the gate circuit 402 does not open and the reception information is not sent to the reception memory 401. does not perform reception processing. On the other hand, since the processor state is not normal, the decoder 407 opens the gate circuit 408, so the processor state register 406
The state of the processor 30 that is set to 28 in the transmission memory 4
09, from the transmission buffer register 410 via the unibus 60 to the reception buffer register 205 of the interprocessor communication device 20 or the communication control circuit 21 (FIG. 3).
sent to.

Next, the reception information in the reception buffer register 205 is sent to the reception memory 201 via the gate circuits 203 and 202. This allows the processor 10 to know that communication to the processor 30 has been rejected and the reason for the rejection, and when the reason is congestion or initialization, the processor 10 can resend the transmitted information at specific timings. In this case, the transmitted information can be transmitted to another processor or discarded depending on its contents.

FIG. 2 is a flowchart (FIG. 2) showing an overview of the reception process of the inter-processor communication control device (FIG. 1) in the first embodiment.

In addition, a flow diagram (
This will be explained in Fig. 4). The communication information is received by the inter-processor communication control device or communication control circuit on the receiving side in ■, and the status of the receiving processor registered in the processor status register is determined in ■ as normal/abnormal (congested, initializing, or faulty). )
Accordingly, reception is determined by the inter-processor communication control device or communication control circuit. As a result, if the processor status is normal and reception is possible, the communication information is received by the processor in step (3). Further, if the processor state is abnormal and reception is possible, information indicating that the processor is in an abnormal state is returned to the transmission source processor in step (3).

Embodiment 2 Below, an embodiment including claim 2 of the present invention is shown in FIGS. 5 and 6.
This will be explained with reference to FIG. Similar to the first embodiment, when the processor 10 communicates with the processor 30, when the processor 10 writes transmission information to the transmission memory 209, the transmission information is sent to the transmission buffer register 210. The transmission buffer register 210 receives the right to use the bus from the bus arbiter 50 and sends transmission information to the unibus 60.

The transmission information is received by the reception buffer register 405,
The address is decoded by the decoder 404, the priority of the communication information is decoded by the decoder 411, and the processor 30
It is determined that the communication information is inter-processor communication information and the priority is determined. At this time 1. Gate circuit 403 operates and attempts to send communication information to reception memory 401. On the other hand, when the processor 30 is operating normally, the normal state is registered in the processor state register 406, and the result of decoding this state by the decoder 407 and the decoder 41
1 and the decoded priority.

The gate circuit 412 determines whether reception is possible, and the gate circuit 402 is operated based on the result.

As a result, the transmission information from the processor 10 is sent from the reception buffer register 405 to the reception memory 401 via the gate circuits 403 and 402, and communication to the processor 30 is completed.

The above is the communication operation when the processor 30 is in a normal state.Next, the operation when the processor 30 is not normal but in a state of confusion will be explained.

When the processor 30 is in a state of congestion, different codes are registered in the processor status register 406 so that the degree of congestion can be identified. In this example, as shown in FIG. 7, the congestion state is set to a CC usage rate of 70%.

It is ranked as 75%, 80%, 85%, 90%, and 95%, and the communication information is ranked in descending order of priority: emergency processing, call processing,
Each maintenance management process is divided into messages (inquiries) and responses.

On the other hand, when transmission information is sent from the processor 10 as described above, the information received by the reception buffer register 405 attempts to be sent to the reception memory 401 via the gate circuit 403, but the processor status register 406 The gate circuit 412 determines whether or not reception is possible based on the result of decoding the processor state registered in the processor state by the decoder 407 and the result of decoding the priority in the received information in the receive buffer register 405 by the decoder 411. In FIG. 7, when the CC usage rate is 90% and the communication priority type allows reception such as emergency processing, the received information is sent to the reception memory 401 as in the normal state, but the CC usage rate is 90%. % and the communication priority type does not permit reception, such as call processing, the gate circuit 402 is not opened and the reception information is not sent to the reception memory 401.

Thereby, the processor 30 does not perform unnecessary reception rejection processing.

Further, since the congestion status is ranked as shown in FIG. 7, communication information of high importance such as communication priority type such as emergency processing can be received even during congestion. On the other hand, if reception is not permitted due to the processor status and the priority of communication information, the gate circuit 408 is opened based on the information in the gate circuit 412, so the processor status register 406
The state of the processor 30 registered in It is sent to memory 201.

As a result, the processor 10 knows that the communication to the processor 30 has been rejected and the reason thereof, and can take measures against the communication rejection.

An overview of the reception processing of the inter-processor communication control device in the above second embodiment will be explained using a flow diagram (FIG. 6).

The communication information is received by the inter-processor communication control device on the receiving side at (2), and the priority is identified from the communication information at (2). Next, in (2), the state or congestion state of the receiving processor registered in the processor state register and the priority identified in (2) are judged based on the criterion shown in FIG. 7, and it is determined whether or not reception is possible.

■As a result, if reception is possible, the communication information is received by the processor in ■. If reception is not possible, the status of the receiving processor is returned to the transmitting processor in step 3.

Embodiment 3 An embodiment including claim 3 of the present invention will be described below with reference to Embodiment 2 with reference to FIGS. 5, 8, and 9.

In the second embodiment, when the processor 30 is congested, the gate circuit 412 determines whether reception is possible based on the processor status and the priority of the communication information decoded by the decoders 407 and 411, and the result is the CC usage rate shown in FIG. At 90%, the communication priority type is call processing, reception is rejected, and the retransmission timing is 5.
In the case of seconds, the gate circuit 408 is opened according to the information of the gate circuit 412, and the state of the processor 30 registered in the processor state register 406 and the retransmission timing value are stored in the transmission memory 409, the transmission buffer register 410,
It is sent to the reception buffer register 205 of the interprocessor communication device 20 via the unibus 60, and is sent to the gate circuit 203.
, 202 to the reception memory 201.

Thereby, the processor 10 knows the reason why the communication to the processor 30 was rejected and the retransmission timing value, and can easily perform the retransmission process.

An outline of the reception processing of the inter-processor communication control device in the above third embodiment will be explained using a flow diagram (FIG. 8).

The communication information is received by the inter-processor communication control device on the receiving side at step 2, and the priority including the type of message response is identified from the communication information at step 2. Next, in ■, the processor status register is set to 9. The recorded state or congestion state of the receiving side processor and the priority identified by (2) are judged according to the criterion shown in FIG. 9, and whether reception is possible or not is determined. (■) As a result, if reception is possible, the communication information is received by the processor in ■.

In addition, if reception is not possible, check the status of the receiving processor with ■.
The retransmission timing value determined in is returned to the sending processor.

〔Effect of the invention〕

According to the present invention, an inter-processor communication device in a distributed control data processing system is provided with a register for identifying the state of each processor, and the processor state, which is the content of the register, determines whether communication information from other processors can be received. By autonomously making a judgment and notifying the transmitting processor of the reason if no, the transmitting processor can determine whether retransmission is possible and whether it is necessary, and the receiving processor can refuse reception without performing reception processing. This has the effect of realizing smooth and highly efficient inter-processor communication.

Furthermore, the transmission processor gives priority to the communication information during transmission. The processor congestion state is assigned a level according to the degree of congestion.

Based on these two points, the inter-processor communication device on the receiving side can independently determine whether or not communication information can be received.

If not, the sending processor can take action against the reception rejection by notifying the sending processor of the reason. The reception processor can reject reception without performing reception processing. Furthermore, communication information can be received depending on the priority and the degree of congestion, allowing flexible congestion control.

By doing the above, smooth and high-rate inter-processor communication can be realized.

In addition to the above effects, when the inter-processor communication device rejects reception, it notifies the transmitting processor of the reason, whether or not to retransmit, and if not, the retransmission timing, which facilitates retransmission processing at the transmitting processor. Smooth and highly efficient inter-processor communication can be achieved.

[Brief explanation of drawings]

FIG. 1, FIG. 3, and FIG. 5 are system configuration diagrams showing an embodiment of the inter-processor communication control method according to the present invention. FIG. 2, FIG. 4, FIG. 6, and FIG. 8 are flowcharts showing one embodiment of the inter-processor communication control method according to the present invention. FIG. 7 is a diagram showing an example of criteria for determining whether or not reception is possible in congestion control according to the second embodiment. FIG. 9 is a diagram illustrating an example of criteria for determining whether reception is possible or not in congestion control according to the third embodiment and retransmission timing values. DESCRIPTION OF SYMBOLS 10, 30... Processor, 20, 40... Inter-processor communication device, 50... Bus arbiter, 60... Unibus, 206, 406... Processor status register. Figure 8

Claims (1)

[Claims] 1. In a distributed control data processing system, the inter-processor communication device or the communication control circuit in the processor is provided with a register for identifying the state of each processor, so that each processor can identify its normal, congested, and initial state. Statuses such as configuring or failure are registered, and the inter-processor communication device or the communication control circuit within the processor autonomously determines whether or not communication information from other processors can be received, and if not, the reason. An inter-processor communication control method that enables the transmitting processor to determine whether or not retransmission is possible and whether retransmission is necessary by notifying the transmitting processor of the received data and allowing the receiving processor to refuse reception without performing reception processing. 2. In claim 1, priority is given to each communication information of inter-processor communication, and the processor congestion state is divided into levels according to the degree of congestion, and the congestion of the processor state registered in the inter-processor communication control device is A processor characterized in that the inter-processor communication control device autonomously determines whether or not to receive individual communication information depending on the degree of congestion, thereby making it possible to receive communication information of high importance in each congestion state. Intercommunication control method. 3. In claim 2, if reception is refused depending on the priority of the communication information and the processor congestion state, the sending processor notifies the sending processor of the reason, whether retransmission is possible, and if retransmission is possible, the retransmission timing. , an inter-processor communication control method characterized in that retransmission is performed after a specified retransmission timing. 4. The inter-processor communication control system according to claim 2, characterized in that the communication information for each inter-processor communication is classified into inquiries and their responses, and the responses are given priority over the inquiries.