JPS6010355A - Measuring system of activity ratio of central processing unit - Google Patents

Abstract

PURPOSE:To measure accurately the activity ratio of a central processing unit by counting an unload time and accumulating the count result of a system belonging to the central processing unit independently of the central processing unit. CONSTITUTION:When the central processing unit 1 is unloaded, a timer status 2 is set to logical 1 by executing a specific instuction (e.g., halt instruction). The level of timer status information 12 brought into logical 1 makes an AND gate 6 conductive, a clock pulse from a clock generating circuit 4 is inputted to an adder circuit 7 and an external timer register 8 counts time. That is, the 2nd time count means 14 comprising the external timer register 8 and the adder circuit 7 count time accumulatively only for the unload period of the central processing unit 1.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for measuring the utilization rate of a central processing unit, and more particularly to a method for measuring the utilization rate of a central processing unit that makes it possible to obtain accurate measurements.

Prior Art and Problems The conventional technology for measuring the usage rate of a central processing unit requires the central processing unit whose usage rate is to be measured to measure the usage rate in addition to the original processing executed by the central processing unit. It also incorporated processing.

In other words, for example, a clock process with a lower priority level than the collapse process executed by the central processing unit is built into the system, and the central processing unit is not performing any processing, that is, the period when it is not in use. By performing the above-mentioned clock processing, the usage rate is reduced by assuming that the central processing unit is under no load while the above-mentioned built-in clock processing is operating.

However, with this conventional technology, the built-in clock processing (program) must also be managed as a system, and overheads such as starting and terminating the built-in clock processing occur, so there is no load. This method has the disadvantage that it is not possible to accurately measure the time during the period, and it is not possible to accurately measure the usage rate of the central processing unit.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the conventional central processing unit utilization measurement method, and calculates the no-load time of the system to which the central processing unit belongs, independently of the central processing unit processing (program). It is an object of the present invention to provide a method that makes it possible to accurately measure the usage rate of a central processing unit by clocking and accumulating.

Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, 1 is the central processing unit whose usage rate is being measured, 2 is the timer status, which consists of a 1-bit register, 3.8 is the external timer register, and 4 is the clock generation circuit. , 5.7 is an adder circuit, 6 is an AND gate, 9 is a main memory of the system, 10 is an interrupt signal, 11 is a common bus of the system, and 12 is a timer.
This is a status information signal.

The external timer registers 3 are general-purpose registers that can fully initialize the time at any time.The clock pulse from the clock generation circuit 4 (one pulse generated per unit time) is input to the adder circuit 5, and the external timer・It is added to the contents of register 3, and the result of this addition is used as the external timer register 3.
(by updating). At this time, the updated and accumulated normal time is set in the external timer register 3.

The external timer register 3 and the adder circuit 5 constitute a first clock means 13.

The timer status 2 set in the central processing unit 1 is composed of a 1-bit register, and while the central processing unit 1 is operating, the interrupt signal 10ii"l#" is set, and its negation 10" is used. However, when the central processing unit 1 becomes unloaded, by executing a specific command (for example, a halt command, not a program), the multi-signal 1o changes and the timer status changes. 2 to "1n".

The above setting i-information "o"s or "1n of timer status 2 is input to one input terminal of AND gate 6, and according to that 'l"1g"0", AND gate 6
Controls conduction and non-conduction.

When the central processing bag N1 becomes unloaded, the timer status 2 is set to 1'' by executing a specific command (for example, a halt command), as described above.
Status information 12 of 11” indicates AND gate 6
conducts, the clock pulse from the clock generation circuit 4 is input to the adder circuit 7, and the external timer register 3 has already been input.
The external timer register 8 clocks in the same manner as described for the adder circuit 5. Here, the external timer register 8 and the adder circuit 7 constitute a second clock means 14.

However, when the central processing unit 1 enters the operating state from the no-load state (in this embodiment, this is the point at which an interrupt occurs to the central processing unit 1, and at that time, the interrupt signal 10 becomes *1
#, the negative of 1' is input to timer status 2), timer status 2 is set to @0'', and 90'' is sent as timer status information 12.
As a result, the six gates are non-conductive, and therefore the clock pulse from the clock generation circuit 4 is output to the adder circuit 7.
The external timer register 8, ie, the second clock means 14, stops clocking.

FIG. 2 is a diagram showing the timing states of the first and second timing means. In the figure, r and n indicate the clocking operation states of the first and M2 clocking means, respectively.

Now, the first and second timing means are initialized and activated at the time to of the whole building 1, and the period T at the second time ti1 is started.
Suppose we measure the amount of As can be easily understood from the above explanation, after the period T has elapsed, the first clock means 13 clocks continuously as shown by the solid line, and the external timer register 3 maintains the time ttt. Here, j!t6=T.

In Figure 2, 1. The solid line T1 r Tt , T@ shown in ■ which shows the clocking state of the second clocking means 14
indicates a period in which the central processing unit 1 is not loaded, and the second clock means 14 including the external timer register 8 clocks only during the period indicated by the solid line.

At time t1, the external timer register 8 is connected to the solid line T.
Time t corresponding to the sum of the periods indicated by l + T2 + Tg
2 is retained.

Here, the usage rate R of the central processing unit 1 is It is expressed as

Since the above operation is performed, regardless of the operation of the central processing unit 1, the external timer register 3 of the first clock means 13 that continuously clocks the time and the time when the central processing unit 1 is not loaded By simultaneously reading out the contents held by the external timer register 8 of the second clock means 14 and calculating the usage rate R at the second time point t1, You can accurately determine the usage rate.

The calculation of the usage rate is performed by first transferring the contents of external timer registers 3 and 8 to the main memory 9 via the common bus 11 under the control of the central processing unit 1, and
It can be calculated based on smell and outputted to the human blade device as appropriate.

The tie 4 and status 2 do not need to be provided in the central processing unit 1, and may be provided in an external general-purpose register or the like.

In the above embodiment, the external timer register accumulates the time when the central processing unit 1 is not loaded, but the time when the central processing unit 1 is in use may be accumulated.

Effects of the Invention Since the present invention is configured as described above, it has the effect that it is possible to accurately determine the usage rate of the central processing unit without being affected by overhead (with the addition of a small amount of hardware). There is. Therefore, it provides an effective means for measuring the performance of a system in operation, designing a system, etc., and makes it possible to construct a high-performance system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the timing states of the first and second clock means in the button of the embodiment. 1...Central processing unit, 2...Timer status,
3.8... External timer register, 4... Clock generation circuit, 5, 7... Adder circuit, 6... AND gate, 9... Main memory, 10... Interrupt signal,
DESCRIPTION OF SYMBOLS 11... Common bus, 2... Timer status information signal, 13... First clocking means, 14... Second clocking means. Patent applicant Fujitsu Limited

Claims (1)

[Claims] In a system having a central processing unit, a first clock unit continuously measures the passage of time, and a second clock unit measures the passage of time only during periods when the central processing unit is not loaded or is in use. and a timer status for transmitting a signal during an unloaded period of the central processing unit, the first and second clocking means are activated simultaneously at a first point in time, and the timer status is The second clocking means is operated only during the period when the central processing unit is not loaded or is in use, and the contents of the first and second clocking means are read at a second time point. ,
A method for measuring the usage rate of a central processing unit, characterized in that the usage rate of the central processing unit is calculated.