JPS61276039A - Processor using ratio measuring system - Google Patents

Processor using ratio measuring system

Info

Publication number
JPS61276039A
JPS61276039A JP60117972A JP11797285A JPS61276039A JP S61276039 A JPS61276039 A JP S61276039A JP 60117972 A JP60117972 A JP 60117972A JP 11797285 A JP11797285 A JP 11797285A JP S61276039 A JPS61276039 A JP S61276039A
Authority
JP
Japan
Prior art keywords
processor
time
circuit
rate
usage rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60117972A
Other languages
Japanese (ja)
Inventor
Koji Suzuki
鈴木 晃二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60117972A priority Critical patent/JPS61276039A/en
Publication of JPS61276039A publication Critical patent/JPS61276039A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the processor using rate in measuring period time by reading the counting value of processor unusing time by a timer interruption for the measuring period, in a processor using rate measuring system. CONSTITUTION:A processor 1 comes to be holding (HALT) condition when an instruction to be processed is not executed, and generates a signal HALT. While the signal is sent through an AND circuit 5 to a counting circuit 2 together with the clock pulse and at the circuit 2, while an HALT signal is sent from the processor 1, namely, while the processor 1 is not used, at the constant interval, the peripheral using time of the processor is counted based upon the clock pulse. On the other hand, a timer circuit 3 gives the interruption to the processor 1 for one constant period, and at such a time, the counting value of the circuit 2 is read. By the rate of the counting value and the interrupting period of the timer circuit 3, the unusing rate of the processor is calculated, the numeric of the unusing rate is extracted from the processor 1, and the average using rate of the processor in one measuring period time is obtained.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はハードウェアプロセッサ、例えばCPUの使用
率の測定方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for measuring the usage rate of a hardware processor, such as a CPU.

[従来の技術] 従来のプロセッサ使用率測定方式としては、例えば以下
のようなものがある。
[Prior Art] Examples of conventional processor usage rate measurement methods include the following.

即ち、プロセッサで行う処理がない時プログラムは無限
ループに入り、カウンタのよって上記ループを回る1可
数をカウントする。このカウント値はソフトウェアが持
っているタイマにより測定周期毎に読み出され、読み取
り後にクリアされる。ヒ記カウント値に無限ループを一
巡する時の実行時間を掛けることにより、測定周期時間
内でのCPUの未使用時間が得られる。また、測定周期
時間からプロセッサの未使用時間を引けばプロセッサの
使用時間が求められる′。このため、プロセッサの使用
率は測定周期時間内でのプロセッサの使用時間の比率を
求めることで得られる。
That is, when there is no processing to be performed by the processor, the program enters an infinite loop, and the counter counts the number of digits that go through the loop. This count value is read every measurement period by a timer included in the software, and is cleared after reading. The unused time of the CPU within the measurement cycle time can be obtained by multiplying the count value described above by the execution time for one round of the infinite loop. Further, by subtracting the unused time of the processor from the measurement cycle time, the used time of the processor can be obtained. Therefore, the usage rate of the processor can be obtained by determining the ratio of the usage time of the processor within the measurement cycle time.

[解決すべき問題点] 先に述べた従来のプロセッサ使用率測定方法では、プロ
センサの未使用時間の算出をプログラムの無限ループを
回る回数から求める。このためメモリのアクセス速度の
変化によるプロセッサのプログラムの実行速度の変動や
、DMAデバイスが7ヘスを専有することによってプロ
グラムの実行速度が低下すると、プログラムが無限ルー
プを回る回数も変動してしまうので正しいカウント値は
得られなくなる。従ってループのカウント値を元にして
得られるプロセッサの使用率も誤差が生ずるという問題
点があった。
[Problems to be Solved] In the conventional processor usage rate measuring method described above, the unused time of the processor is calculated from the number of times the program goes through an infinite loop. Therefore, if the processor's program execution speed changes due to changes in memory access speed, or if the program execution speed decreases due to the DMA device monopolizing the 7 hess, the number of times the program goes through an infinite loop will also change. Correct count values will no longer be obtained. Therefore, there is a problem in that the processor usage rate obtained based on the loop count value also has an error.

[問題点の解決手段] 本発明に係るプロセッサ使用率測定方式は上記問題点を
解決するために、プロセッサの未使用時間をもとにプロ
セッサ使用率を測定する方式において、処理すべき命令
がない時にホールド状態となるプロ七%ンサと、該プロ
セッサのホールド状態時に一定時間間隔でプロセッサの
未使用時間のカウントを行うカウント回路と、該カウン
ト回路のカウント(+Ciを読み取るためにト記プロセ
ッサに対して発生させる割り込みに対して、その周期を
常に一定させるタイマ回路とを有し、ヒ記測定周期毎の
タイマ割り込みによりプロセッサ未使用時間のカウント
値を読み取って、測定周期時間内のプロセッサ使用率を
求めるものである。
[Means for Solving the Problems] In order to solve the above problems, the processor usage rate measurement method according to the present invention has a method of measuring the processor usage rate based on the unused time of the processor, in which there are no instructions to be processed. A processor that sometimes enters a hold state, a counter circuit that counts the unused time of the processor at fixed time intervals when the processor is in a hold state, and a It has a timer circuit that always keeps the cycle constant for interrupts generated by the system, and reads the count value of unused time of the processor by the timer interrupt at each measurement cycle, and calculates the processor usage rate within the measurement cycle. It is something to seek.

[実施例] 以下、本発明の実施例を図面に基づいて説明する。第1
図は本発明の一実施例によるプロセッサ使用率測定方式
を示すための回路のブロック図である。
[Example] Hereinafter, an example of the present invention will be described based on the drawings. 1st
FIG. 1 is a block diagram of a circuit for illustrating a processor usage rate measurement method according to an embodiment of the present invention.

図に示すように、プロセッサ1は処理すべき命令がない
時にホールド(HALT)状態となり、HALT信号を
発する。このHALT信号はクロックパルスと共にAN
D回路5を介してカウント回路2に送り込まれ、上記カ
ウント回路2はプロセッサlからHALT信号が送られ
て来る間、つまりプロセッサ1が未使用状態の間、一定
間隔で上記プロセッサ1の未使用時間をクロックパルス
に基づいてカウントする。
As shown in the figure, when there is no instruction to be processed, the processor 1 enters a hold (HALT) state and issues a HALT signal. This HALT signal along with the clock pulse
The signal is sent to the count circuit 2 via the D circuit 5, and the count circuit 2 counts the unused time of the processor 1 at regular intervals while the HALT signal is sent from the processor 1, that is, while the processor 1 is in an unused state. is counted based on clock pulses.

一方、タイマ回路3はソフトウェアの有するタイマによ
りプロセッサ1に一定周期毎に割り込みをかけ、この時
点でのカウント回路2のカラントイ1ηを読み取る。こ
のカウント値と上記タイマ回路3の割り込み周期との比
を取ってプロセッサの未使用束を算出し、さらにlから
上記未使用率の数値を引くことにより一測定周期時間内
のプロセッサの平均使用率を得る。なお、図中4はデー
タバスである。また、上記カウント値は、タイマ割り込
みによるカウント値読み取りの後に、次の周期のカウン
トに備えてクリアされる。
On the other hand, the timer circuit 3 interrupts the processor 1 at regular intervals using a timer included in the software, and reads the count 1η of the count circuit 2 at this time. The unused bunch of processors is calculated by taking the ratio of this count value and the interrupt period of the timer circuit 3, and then the average usage rate of the processors within one measurement period is calculated by subtracting the above unused rate from l. get. Note that 4 in the figure is a data bus. Further, the count value is cleared in preparation for the next cycle of counting after the count value is read by a timer interrupt.

このようなプロセッサ使用率測定方式において、測定周
期割込発生時に仮に他の割込み処理をブロセーノサが行
っていて割込みの受は付けが遅れても、プロセッサlは
他の処理を行っているのでHALT状態とはならず、前
記の他の処理が終了して測定18期割込みが受は付けら
れた時に読みとるHALT状態即ち未使用時間のカウン
ト値は、周期割込みの発生した時の値のままである。従
って411定周期割込みの受は付けが遅れても測定値に
誤差は生じない。
In this type of processor usage rate measurement method, even if the interrupt processor is processing other interrupts when a measurement period interrupt occurs and there is a delay in accepting the interrupt, the processor L is in a HALT state because it is processing other processes. Instead, the HALT state, that is, the unused time count value read when the other processing is completed and the 18th measurement period interrupt is accepted, remains the same as the value at the time the periodic interrupt occurred. Therefore, even if there is a delay in accepting the 411 periodic interrupt, no error will occur in the measured value.

[発明の効果] 以上説明したように本発明によるプロセッサ使用率測定
方式は、プロセッサ未使用時間の算出における数値誤差
が極めて小さいので、正確なプロセッサの使用率を求め
ることができる。
[Effects of the Invention] As explained above, in the processor usage rate measurement method according to the present invention, the numerical error in calculating the processor unused time is extremely small, so that it is possible to obtain an accurate processor usage rate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係るプロセッサ使用率測定方式の一実
施例の回路ブロック図である。 1:プロセッサ   2:カウント回路3:タイマ回路
FIG. 1 is a circuit block diagram of an embodiment of a processor usage rate measuring method according to the present invention. 1: Processor 2: Count circuit 3: Timer circuit

Claims (1)

【特許請求の範囲】[Claims] プロセッサの未使用時間をもとにプロセッサ使用率を測
定する方式において、処理すべき命令がない時にホール
ド状態となるプロセッサと、該プロセッサのホールド状
態時に一定時間間隔でプロセッサの未使用時間のカウン
トを行うカウント回路と、該カウント回路のカウント値
を読み取るために上記プロセッサに対して発生させる割
り込みに対して、その周期を常に一定させるタイマ回路
とを有し、上記測定周期毎のタイマ割り込みによりプロ
セッサ未使用時間のカウント値を読み取って、測定周期
時間内のプロセッサ使用率を求めることを特徴とするプ
ロセッサ使用率測定方式。
In the method of measuring the processor usage rate based on the unused time of the processor, there is a processor that enters the hold state when there are no instructions to process, and a count of the unused time of the processor at fixed time intervals while the processor is in the hold state. and a timer circuit that always keeps the cycle constant for interrupts generated to the processor to read the count value of the count circuit, and the timer circuit keeps the cycle constant for interrupts generated to the processor to read the count value of the count circuit. A processor usage rate measuring method characterized by reading a count value of usage time and determining the processor usage rate within a measurement cycle time.
JP60117972A 1985-05-31 1985-05-31 Processor using ratio measuring system Pending JPS61276039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60117972A JPS61276039A (en) 1985-05-31 1985-05-31 Processor using ratio measuring system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60117972A JPS61276039A (en) 1985-05-31 1985-05-31 Processor using ratio measuring system

Publications (1)

Publication Number Publication Date
JPS61276039A true JPS61276039A (en) 1986-12-06

Family

ID=14724831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60117972A Pending JPS61276039A (en) 1985-05-31 1985-05-31 Processor using ratio measuring system

Country Status (1)

Country Link
JP (1) JPS61276039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04104338A (en) * 1990-08-23 1992-04-06 Nec Corp Computer system performance analyzer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5822463A (en) * 1981-08-04 1983-02-09 Mitsubishi Electric Corp Computer load measuring instrument
JPS6010355A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Measuring system of activity ratio of central processing unit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5822463A (en) * 1981-08-04 1983-02-09 Mitsubishi Electric Corp Computer load measuring instrument
JPS6010355A (en) * 1983-06-30 1985-01-19 Fujitsu Ltd Measuring system of activity ratio of central processing unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04104338A (en) * 1990-08-23 1992-04-06 Nec Corp Computer system performance analyzer

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