JP3129027B2 - Parallel processing computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing computer used for a simulator system or a programmable controller, and more particularly to a parallel processing computer capable of monitoring the operation of an arithmetic processor and displaying its operation rate.

[0002]

2. Description of the Related Art Conventionally, in a parallel processing computer operated by interrupt processing, when actually measuring the operation time of an arithmetic processor, a counter for counting the number of processings is provided in a P (processor) level program, and the system is operated for a fixed time. A method is adopted in which the processing is started and then stopped, and a rough processing free time margin is obtained from the count value.

[0003]

However, the conventional method has a problem that the processing time varies due to conditional branching in P-level processing, and an accurate value cannot be obtained. The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a parallel processing computer capable of constantly monitoring the operation of an arithmetic processor and displaying its operation rate in real time. is there.

[0004]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a monitoring processor and a plurality of arithmetic processors connected to an external bus, in which a periodic interrupt signal is alternately performed at a constant cycle. sent to it in a parallel processing computer which performs alternating periodic interrupt processing, the arithmetic processor includes a constant period interrupt processing
From the end of the process until the next periodic interrupt process starts
The execution time is constant during the
Run monitoring programs running on the level repeatedly
Means and a counter for counting the number of executions of the monitoring program
And a monitoring processor, the monitoring processor comprising:
Reading the number of program executions from the arithmetic processor
The monitoring program
Is reduced by subtracting the value multiplied by the execution time of
Means for calculating the execution period of the period interruption process,
Calculation processor operating rate using the execution period of
And means for displaying the operation rate.
It is characterized by.

[0005]

According to the present invention, the arithmetic processor is provided with a monitoring program having a constant execution time and operating on the P level of the arithmetic processor. The number of times the monitoring program is processed is counted, and the counted value is periodically calculated. Is read. In the monitoring processor, the operation rate of the arithmetic processor is calculated from the number of processes, and the operation rate is displayed.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention. In the figure, 1 is a monitoring processor, 2 and 3 are operation processors, 4 is a fixed-cycle timer, 5 is a display unit, 6 is an external common bus, and 7 is a fixed-cycle interrupt signal line. The monitoring processor 1 and the arithmetic processors 2 and 3 are connected to each other via an external common bus 6 and are operated by an interrupt signal alternately sent from the fixed-cycle timer 4 at a fixed cycle via a fixed-cycle interrupt signal line 7. And functions as a parallel processing computer.

The monitoring processor 1 has a built-in interrupt counter 11 for counting the number of interrupt signals sent from the fixed-cycle timer 4 to the monitoring processor 1. Similarly, the arithmetic processors 2 and 3 have built-in sum number counters 21 and 31 for counting the number of program sum checks that are executed for a fixed period of time and operate on the P level of each arithmetic processor. Each of the interrupt counter 11 and the sum counters 21 and 31 is configured by software. The count values of the sum counters 21 and 31 are read by the monitoring processor 1 at a constant cycle, and the operating rates of the arithmetic processors 2 and 3 are calculated from the count values. The calculated operation rate is sent to the display unit 5 and displayed in real time.

Next, a method of calculating the operating rate displayed by the display unit 5 will be described with reference to timing charts shown in FIGS. The arithmetic processor 2, as shown in the interrupt level 2, each time the interrupt signal is input at an interval of a constant period t _c, the periodic interrupt processing is executed. The processing time of the fixed cycle interrupt processing is a fixed cycle t.
Compared with _c, it is a short time and its length varies. Until the next interrupt signal remaining in the fixed-cycle interrupt processing,
Sum check processing is performed at the P level.

FIG. 3 shows a program that is repeatedly executed at the interrupt level and that a sum check process executed at the P level is executed continuously.
That is, it is composed of an overhead of a time t _{o at} the beginning, and a sum check following the overhead as n blocks. The processing time per block is t _s , and the shorter the time t _s , which is the sum check section, the higher the resolution. The number n of blocks in the sum check corresponds to the program length at the interrupt level.

[0010] In this manner, as the periodic processing of the interrupt level, the program is executed with a different length each time, and the remaining time is checked at the P level by the sum check. If the next interrupt signal occurs even in the middle, the operation is interrupted and the rest is resumed in the next section.
That is, the sum of the time of sum check of processing time and fixed cycle interrupt process is periodic t _c. As a result, the operation rate of each of the arithmetic processors 2 and 3 can be calculated by counting the number of sum check blocks processed at the P level within a sufficiently long fixed section. Now, as shown in FIG. 2, when the counted sum number of times within a period of interruption level of processing count n _c is N, operation rate by the following equation η
Is calculated.

[0011]

(Equation 1)

[0012] Note that the processing times n _c and thumb number N in the formula, the interrupt counter 11 of FIG. 1, is counted by the sum counter 21 and 31. When the count value is sent to the monitoring processor 1 and the operating rate η is calculated, the operating rate η is displayed on the display unit 5 in real time for each of the arithmetic processors 2 and 3.

As described above, in the present embodiment, P
Paying attention to the fact that the processing time of the sum check processing executed at the level is a constant cycle for each processing unit, the occupation time at the P level is calculated from the processing time, and the operating rates of the arithmetic processors 2 and 3 are obtained. By displaying, it is possible to monitor the operating state of the parallel processing computer without adding a special hardware device. Note that any monitoring program other than the sum check process that can calculate the occupation time at the P level can be used in the same manner.

[0014]

As described above, according to the present invention, the operating rate of the arithmetic processor is calculated and displayed from the number of times the monitoring program that operates on the P level of the arithmetic processor has a constant execution time. Thus, the operation of the arithmetic processor, that is, the interrupt processing time margin can be monitored in real time as a change in the operation rate. Moreover, the present invention can improve the usability of the parallel processing computer without imposing a special burden on both software and hardware. Further, according to the present invention, it is possible for the arithmetic processor to simultaneously perform WDT (watchdog timer) monitoring, program checksum monitoring, and an operation test based on the checksum operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the embodiment.

FIG. 3 is a timing chart illustrating the operation of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Monitoring processor 2, 3 Arithmetic processor 4 Fixed-cycle timer 5 Display part 6 External common bus 7 Fixed-cycle interrupt signal line 11 Interrupt count counter 21, 31 Sum count counter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/177 678 G06F 11/34

Claims (1)

(57) [Claims] 1. A parallel processing computer which performs the constant period interrupt signal to an external bus connected to the monitor processor on a plurality of arithmetic processors are sent to <br/> alternately at a constant period the periodic interrupt process alternately In the above, after the fixed-period interrupt processing is completed , the arithmetic processor
The execution time is constant during the idle period until the
A monitoring program that runs on the P level of the processor
Means for return run Ri, and a counting means for counting the number of times of execution of the monitoring program, also the monitoring processor is either the arithmetic processor execution count of the monitoring program
Means to read from and the execution time of the monitoring program
Periodic interrupt processing by subtracting the value multiplied by
Calculating means for calculating the execution period of the fixed-cycle interrupt processing,
A means for calculating the operating rate of the computer and a means for displaying the operating rate .