JPS6024655A - Measuring device of utilization factor of central processing unit - Google Patents

Abstract

PURPOSE:To reduce a load of a CPU by providing a pair of counters and a pair of registers, and measuring a utilization factor of the CPU as a hardware. CONSTITUTION:The first counter 4 counts an effective processing time of a CPU1 by a control order from the CPU1, and its result is stored in the first register 5. The second counter 6 counts an idle time of the CPU1 by the control order from the CPU1, and its result is stored in the second register 7. An operating circuit 8 calculates a utilization factor of the CPU1 from the effective processing time and the idle time of the CPU1 stored in the register 5 and 7, and outputs it. Also, an operation of an extension transmission control, etc. can be executed by adding a comparing circuit 9. In this way, a load of the CPU1 can be reduced by providing a pair of counters 4, 6 and a pair of registers 5, 7, and measuring the utilization factor of the CPU1 as a hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an apparatus 1 for measuring the usage rate of a central processing unit used in an automatic exchange! ? Regarding.

Conventionally, the usage rate of the central processing unit is lit! In the I+ system, a counter for interrupt timing generation was used, and the contents of the counter were read by a program and calculated to calculate the usage rate of the central processing unit. This method has the disadvantage that the load on the central processing unit increases due to the calculation of the usage rate.

An object of the present invention is to provide a pair of counters and a pair of registers, respectively, in order to measure the usage rate of a central processing unit.
To provide a central processing unit usage rate measuring device configured to eliminate the above drawbacks and reduce the load on the central processing unit by iI by measuring the usage rate of the central processing unit using hardware. It is in.

The central processing unit usage rate measuring device according to the present invention is used in an automatic father exchange machine that requires time constraints and has a processing format configured by a program that is started at regular time intervals. The device includes first and second counters, first and second registers, an arithmetic circuit, and a control order decoder.

The first counter is for counting the effective processing time of the central processing unit according to control orders from the central processing unit.

The first register is for storing the contents of the first counter.

The second counter is for counting the idle time of the central processing unit according to control orders from the central processing unit.

The second register is for storing the contents of the second counter.

The arithmetic circuit is for calculating the central processing unit usage rate from the effective processing time and stalling time of the central processing unit.

The control order decoder is for decoding control orders from the central processing unit and providing control signals to the first and second counters and the first and second registers.

In the present invention, the contents stored in the first and second registers are computed by an arithmetic circuit to calculate the total usage rate of the central processing unit.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a central processing unit usage rate measuring device according to the present invention. In Figure 1, 1
is a central processing unit, 2 is a clock generator, 3 is a control order decoder, 4 is a first counter, 5 is a first register,
6 is a second counter, 7 is a second register, 8 is an arithmetic circuit, and 9 is a comparison circuit.

In FIG. 1, a first counter 4 and a first register 5 are connected to a central processing unit 1 via a control order decoder 3.
A second counter 6 and a second register 1 are connected. A clock signal from the clock generator 2 is input to the first and second counters 4 and 6. The outputs of the first and second registers 5 and 7 are connected to an arithmetic circuit 8.

The central processing unit 1 is a type of processing unit that executes a periodic program at periodic time intervals, and a clear 0 control order is sent from the central processing unit 1 to the control order decoder 3 at the start of processing of the periodic program. Control order decoder 3
Then, the control order is decoded, a CLRO signal is generated, and the CLRO signal is provided to the first counter 4. When the CI, 'Ro signal is applied, the contents of the first counter 4 are cleared and the first counter 4 starts counting the clock signal sent from the clock generator 2. When the central processing unit 1 completes all the processing of the periodic program, the central processing unit 1 sends 1 lil of clear 1 control orders to the I control order decoder 3. Therefore, the control order decoder 3 decodes this control order, generates a CLRIm number, and supplies it to the second counter 6 and the second register 7. When CLRl(M) is given, the contents of the second counter 6 are cleared and the second counter 6 starts counting the clocks sent from the clock generator 2. At this time, the register 5 of ε1)1 stores the contents of the first counter 4. Fixed time 11
After the central processing unit 1 starts processing the periodic program again, the central processing unit (i21 clears 0 again.
A control order is sent. The contents of the first counter 4 are then cleared and the first counter 4 starts counting the clock signal from the clock generator 2. At this time,
The contents of the second counter 6 are stored in the second register 7. In the arithmetic circuit 8, the effective processing time of the central processing unit f1'11, which is the content of the first register 5, and the free time of the central processing unit 1, which is the content of the second register T, are all used for medium dash processing. The usage rate of the device 1 is calculated and output. Further, a comparison circuit 9 can be added to perform certain operations such as comparison with a constant central processing unit usage rate such as 80%, extension restriction, etc.

By repeating the above steps, it is possible to calculate the usage rate of the central processing unit 1 in terms of hardware.

As explained above, the present invention is capable of reducing the load on the central processing unit by providing a pair of counters and a pair of registers to measure the usage rate of the central processing unit using hardware. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a central processing unit usage rate measuring device having multiple configurations according to the present invention. 1...Central processing unit 2...Clock generator 3.Warning/control order decoder 4.6...Counter 5.7...Register 8...Arithmetic circuit 9...Comparison circuit

Claims (1)

[Claims] A central processing unit usage rate measuring device used in an automatic switchboard having a processing format that requires time constraints and is configured by a program that is activated at regular time intervals, the central processing unit usage rate measuring device a first counter for counting the effective processing time of the central processing unit according to a control order from the central processing unit; a first register for storing the contents of the first counter; A second counter for counting and a second register for storing the contents of the second counter, and a second register for storing the contents of the second counter, and a second register for storing the contents of the second counter according to the control order, an arithmetic circuit for calculating a central processing Φ゛ and equipment usage rate from the effective processing time and the free time; and an arithmetic circuit for decoding the control order from the central processing unit, , and a control order decoder for giving a ?ti1. control signal to the first and second registers, the contents stored in the first and second registers are operated by the arithmetic circuit and the A device for measuring the usage rate of the central processing unit, which is characterized by the ability to calculate the central processing unit usage rate.