JPS59135526A - Data input control system - Google Patents

Data input control system

Info

Publication number
JPS59135526A
JPS59135526A JP959283A JP959283A JPS59135526A JP S59135526 A JPS59135526 A JP S59135526A JP 959283 A JP959283 A JP 959283A JP 959283 A JP959283 A JP 959283A JP S59135526 A JPS59135526 A JP S59135526A
Authority
JP
Japan
Prior art keywords
data
input
signal
data input
input control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP959283A
Other languages
Japanese (ja)
Inventor
Kunitoshi Otsuki
大月　邦俊
Yasuaki Fusejima
伏嶋　康昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP959283A priority Critical patent/JPS59135526A/en
Publication of JPS59135526A publication Critical patent/JPS59135526A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To ensure the stable data input control by using the signal showing that the data given from a data input device is fixed as an interruption signal of a microprocessor unit and giving the interruption processing to said input data. CONSTITUTION:A data input device 5 transmits data to an input controller 2 via a data transmission line 6. The controller 2 delivers a signal to a signal line 4 to show that the received data is fixed. A microprocessor unit 1 supplies said signal as an interruption signal and supplies the data given from the controller 2 via a microprocessor system bus 3 for interruption processing.

Description

【発明の詳細な説明】 本発明はデータ入力制御方式、特にマイクロプロセッサ
のデータ入力制御方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data input control systems, and more particularly to data input control systems for microprocessors.

従来、マイクロプロセッサシステムのデータ入力制御方
式にお−ては、データ入力機器からデータが入力したか
否かを示すデータ入力状態表示信号をマイクロプロセッ
サシステムのデータバスに出力するデータ入力制御装置
と前記データ入力状態表示信号を一定周期で定期的に読
み取るマイクロプロセッサユニットとで構成されており
、データ入力表示がある場合に前記マイクロプロセッサ
ユニットが前記データ入力制御装置からデータを入力し
ていた。Conventionally, a data input control method for a microprocessor system includes a data input control device that outputs a data input status display signal indicating whether or not data has been input from a data input device to a data bus of the microprocessor system; The microprocessor unit periodically reads a data input status display signal at a fixed cycle, and when there is a data input display, the microprocessor unit inputs data from the data input control device.

そのためマイクロプロセッサユニットにデータ入力状態
表示信号を読み取る周期よりも早い周期でデータが入力
された場合、マイクロプロセッサユニットはすべてのデ
ータを入力することが出来ないという欠点があった。Therefore, if data is input to the microprocessor unit at a cycle faster than the cycle at which the data input status display signal is read, there is a drawback that the microprocessor unit cannot input all the data.

本発明はデータ入力機器から入力した入力データが確定
したことを示す信号をマイクロプロセッサユニットへの
割シ込み信号とし、前記入力データを割シ込み処理する
ことによシ上記欠点を除去し、データ入力機器からのす
べてのデ＝タヲマイク四プロセッサユニットへ入力出来
るようにした装置を提供するものである。The present invention eliminates the above drawbacks by using a signal indicating that input data input from a data input device has been determined as an interrupt signal to a microprocessor unit, and processing the input data as an interrupt signal. The present invention provides a device that can input all data from input devices to the four processor units.

２本発明によるとデータ入力機器から入力したデータ及
び該データが確定したことを示す信号を出力する入力制
御装置と、前記信号を割り込み信号として入力し、前記
入力信号データを割シ込み処理するマイクロプロセッサ
ユニットとを含み、前記データ入力機器から送られてく
るすべてのデータを前記入力制御装置を介してマイクロ
プロセッサユニットに入力せしめることを特徴とするデ
ータ入力制御方式が得られる。2. According to the present invention, an input control device outputs data input from a data input device and a signal indicating that the data is finalized; and a microcontroller that inputs the signal as an interrupt signal and performs interrupt processing on the input signal data. A data input control method is obtained, which includes a processor unit, and is characterized in that all data sent from the data input device is input to the microprocessor unit via the input control device.

次に図面を参照し本発明の実施例について説明する。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例を示すマイクロプロセッサシ
ステムのブロック図である。FIG. 1 is a block diagram of a microprocessor system showing one embodiment of the present invention.

第１図において、マイクロプロセッサシステムハ、マイ
クロプロセッサユニット１と、入力制御装置２のほか、
マイクロプロセッサシステムバス３と、信号線４と、デ
ータ入力機器５と。In FIG. 1, in addition to a microprocessor system C, a microprocessor unit 1 and an input control device 2,
A microprocessor system bus 3, a signal line 4, and a data input device 5.

データ伝送線６とから構成されている。It is composed of a data transmission line 6.

データ入力機器５は、データ伝送線６を経由して入力制
御装置２ヘデータを送出する。入力制御装置２は、受信
したデータが確定したことを示す信号を信号線４へ出力
する。マイクロプロセッサユニット１はこの信号を割り
込み信号として入力し、割り込み処理として入力制御装
置２からデータをマイクロプロセッサシステムバス３を
経由して入力する。Data input device 5 sends data to input control device 2 via data transmission line 6 . The input control device 2 outputs a signal to the signal line 4 indicating that the received data has been finalized. The microprocessor unit 1 inputs this signal as an interrupt signal, and inputs data from the input control device 2 via the microprocessor system bus 3 as interrupt processing.

本発明は以上説明したように、データ入力機器からのデ
ータが確定したことを示す信号をマイクロプロセッサユ
ニットの割シ込み信号とし、前記入力データを割シ込み
処理することによシ。As described above, the present invention uses a signal indicating that data from a data input device is finalized as an interrupt signal for a microprocessor unit, and performs interrupt processing on the input data.

データ入力機器からのすべてのデータをマイクロプロセ
ッサユニットへ入力出来るようにし、安定したデータ入
力制御を可能にする効果がある。This has the effect of allowing all data from the data input device to be input to the microprocessor unit, thereby enabling stable data input control.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明のデータ入力制御方式の一実施例を示
すブロック図である。 １・・・・・・マイクロプロセッサユニット、２・・・
・・入力制御装置、３・・・・・・マイクロプロセッサ
システムバス、４・・・・・・信号線、５・・・・・・
データ入力機器％　６・・・・・・データ伝送線。 朶１区FIG. 1 is a block diagram showing an embodiment of the data input control method of the present invention. 1...Microprocessor unit, 2...
...Input control device, 3...Microprocessor system bus, 4...Signal line, 5...
Data input equipment% 6...Data transmission line. 1st ward

Claims (1)

【特許請求の範囲】[Claims] データ入力機器から入力したデータ及び該データが確定
したことを示す信号を出力する入力制御装置と、前記信
号を割シ込み信号として入力し前記入力データを割シ込
み処理するマイクロプロセッサユニットとを含み、前記
データ入力機器から送られてくるすべてのデータを前Ｂ
己入力制御装置を介して前記マイクロプロセッサユニッ
トに入力せしめることを特徴とするデータ入力制御方式
。an input control device that outputs data input from a data input device and a signal indicating that the data has been finalized; and a microprocessor unit that inputs the signal as an interrupt signal and interrupts the input data. , All data sent from the data input device is
A data input control method characterized in that input is made to the microprocessor unit via a self-input control device.
JP959283A 1983-01-24 1983-01-24 Data input control system Pending JPS59135526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP959283A JPS59135526A (en) 1983-01-24 1983-01-24 Data input control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP959283A JPS59135526A (en) 1983-01-24 1983-01-24 Data input control system

Publications (1)

Publication Number Publication Date
JPS59135526A true JPS59135526A (en) 1984-08-03

Family

ID=11724595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP959283A Pending JPS59135526A (en) 1983-01-24 1983-01-24 Data input control system

Country Status (1)

Country Link
JP (1) JPS59135526A (en)

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