JPH07260845A - Pulse period measuring circuit - Google Patents

Abstract

PURPOSE:To lessen a load of a calculator for calculating a pulse interval across a plurality of external pulses. CONSTITUTION:An external pulse detector 1 detects a rise of an external pulse CK at each time of inputting it, and outputs a detection signal SA to a counter 2. The counter 2 counts the signal SA. A frequency set register 3 sets a predetermined number N for calculating the interval of predetermined number N of the generated pulses CK. A comparator 4 compares a counted value NA with the number N, and outputs a control signal SB in the case of coincidence. The signal SB is output to the counter 2 and an interrupt signal generator 5. The counter 2 resets the counted value NA in response to the signal SB. An interrupt signal generator 5 outputs an interrupt signal SC for calculating the interval of the number N of the pulses CK in response to the signal SB. A transfer circuit 6 reads a time when a timer 7 counts in response to the signal SC, and transfers it to a time storage register 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse period measuring circuit, and more particularly, to a pulse period measuring circuit for measuring the time until a predetermined number of subsequently generated pulses are generated on the basis of one pulse generation. Regarding

In a computer system in which an external pulse continuously generated as a detection target is measured, the period of the pulse is measured, and the controlled object or the like is accurately controlled based on the measurement result, higher speed, Higher precision and more functions are desired. Therefore, in the computer system, a pulse period measuring circuit that reduces the load for measuring the external pulse is required.

[0003]

2. Description of the Related Art Conventionally, in the measurement of external pulses CK continuously generated as shown in FIG. 5, one pulse is used as a reference until a predetermined plurality of external pulses CK subsequently generated. Pulse interval TA (= tn -tn-
1) may be measured. FIG. 4 shows the pulse cycle measuring circuit. In FIG. 4, the external pulse detection circuit 31 inputs the external pulse CK to be measured, detects the rising edge thereof, and outputs the rising edge detection signal S1 to the interrupt signal generation circuit 32. The interrupt signal generation circuit 32 responds to the rising edge detection signal S1 by transmitting the interrupt signal S2 to the data latch transfer circuit 33 and the central processing unit (CPU) 34 as an arithmetic unit.
Output to. In response to the interrupt signal S2, the data latch transfer circuit 33 causes the reference time axis generation timer 35 to read the time measured at that time as the event occurrence time tn and transfer it to the event occurrence time storage register 36 in the next stage.

In response to the interrupt signal S2, the CPU 34 executes a time acquisition determination processing operation based on the signal S2. The time acquisition determination process is performed according to software, and the current interrupt signal S2 is the external pulse CK that serves as a reference.
From the number of external pulses CK, the target number (Fig.
Then, it is determined whether four external pulses CK have been generated. If it is not the fourth external pulse CK,
The CPU 34 ends this time acquisition determination process and executes another process. On the contrary, in the case of the fourth external pulse CK, the event occurrence time tn stored in the event occurrence time storage register 36 is read to the event occurrence time tn-
Comparing with 1, the pulse interval TA is calculated.

Thereafter, the same processing is repeated, and the pulse interval T during the generation of four external pulses CK that are sequentially generated.
Measure A. Although not shown as another pulse cycle measuring circuit, there is a circuit in which a data latch transfer circuit and an event occurrence time storage buffer register are provided between the reference time axis generation timer 35 and the data latch transfer circuit 33 shown in FIG. . This data latch transfer circuit is an external pulse detection circuit 3
In response to the rising detection signal S1 of 1, the reference time axis generation timer 35 measures the time measured at that time as the event occurrence time tn.
, And transfer it to the event occurrence time storage buffer register of the next stage. Then, the data latch transfer circuit 33 reads the event occurrence time tn transferred to the event occurrence time storage buffer register in response to the interrupt signal S2,
The data is transferred to the event occurrence time storage register 36 in the next stage. Similarly, this pulse period measuring circuit can measure the pulse interval TA across a plurality of external pulses CK.

[0006]

However, in any of the pulse cycle measuring circuits, the interrupt signal S2 is output every time the external pulse CK is generated, and each time the interrupt signal S2 is output, the arithmetic unit serves as an arithmetic unit. CPU34
Performs the time acquisition determination process by stopping other processing operations. That is, even when an external pulse CK that is not the desired number of external pulses CK occurs, the CPU 34 enters the time acquisition determination process, and it is determined that the external pulse CK is not the desired number of external pulses CK. Return to processing. Therefore, during that time, the CPU 34 performs an unnecessary time acquisition determination processing operation, which is a big problem in performing high-speed and efficient processing.

The present invention has been made in order to solve the above problems, and its object is to reduce the load on an arithmetic unit for calculating a pulse interval over a plurality of external pulses and to make the arithmetic unit operate at high speed. An object is to provide a pulse period measuring circuit that can efficiently execute a program.

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention. The external pulse detection circuit 1 receives the external pulse CK, detects the rising or falling of the external pulse CK each time the external pulse CK is input, and outputs a detection signal SA to the counter 2. The counter 2 counts the detection signal SA. The frequency setting register 3 has a predetermined number N of external pulses CK to be generated.
The predetermined number N for calculating the pulse interval of is set in advance.

The comparison circuit 4 counts the count value NA of the counter 2.
And the predetermined number N of the frequency setting registers 3 are compared, and when they match, the control signal SB is output. The control signal SB is output to the counter 2 and the interrupt signal generation circuit 5. And
The counter 2 responds to the control signal SB with the count value N
Reset A. The interrupt signal generation circuit 5 uses the control signal S
In response to B, an interrupt signal SC for calculating the interval of the predetermined number N of the external pulses CK is output. Transfer circuit 6
Responds to the interrupt signal Sc and transfers the time tn measured by the timer 7 to the read time storage register 8 at that time.

[0010]

According to the present invention, when the predetermined number N of external pulses CK are generated, the comparison circuit 4 generates the control signal SB. Then, in response to the control signal SB, the interrupt signal SC is output from the interrupt generation circuit 5. That is, the interrupt signal SC is not output every time the external pulse CK is generated, but one interrupt signal SC is output every time the predetermined number N is generated. Therefore, for example, if this interrupt signal SC is output to the arithmetic unit for calculating the interval of the predetermined number N of the external pulses CK, the arithmetic unit outputs the time storage register 8
Therefore, the number of times of capturing time from is also reduced and the load is reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the pulse period measuring circuit of the present invention will be described below with reference to FIG. For convenience of explanation, the pulse cycle measuring circuit measures the pulse interval TA when four external pulses CK shown in FIG. 5 are generated.

The external pulse detection circuit 11 receives the external pulse CK shown in FIG. 5, detects the rising edge thereof, and outputs the rising edge detection signal SA. Therefore, the external pulse detection circuit 11
Outputs the rising detection signal SA every time the external pulse CK is input. The counter 12 receives the rising edge detection signal SA and counts the input number NA. The interrupt frequency setting register 13 has a predetermined number N for calculating the interval TA when four external pulses CK are generated.
The data of (= 4) is preset.

The comparison circuit 14 compares the count value NA of the counter 12 with the predetermined number N of data in the interrupt frequency setting register 13 and outputs a control signal SB when the count value NA reaches N (= 4). Control signal SB is counter 1
2 and the interrupt signal generation circuit 15. The counter 12 resets the count value NA from "4" to "1" in response to the control signal SB. In response to the control signal SB, the interrupt signal generation circuit 15 outputs an interrupt signal SC for calculating a predetermined number N (= 4) of intervals TA of the external pulse CK. The interrupt signal SC is the data latch transfer circuit 16 and the central processing unit (CPU) as an arithmetic unit.
It is output to 17.

The data latch transfer circuit 16 receives an interrupt signal S
In response to C, the time tn at which the reference time axis generation timer 18 composed of a free-running counter is clocking is read, and the time tn is read as the event occurrence time storage register 1
It is supposed to be transferred to 9. On the other hand, the CPU 17 executes the time acquisition determination processing in response to the interrupt signal SC. In the time acquisition determination processing, the time tn stored in the event occurrence time storage register 19 is read out, and the CPU 1
The pulse interval TA (= tn-tn-1) is calculated based on the previous time tn-1 read out based on the one previous interrupt signal SC stored in the internal register incorporated in FIG. ing. Then, after calculating the interval TA and storing the newly read time tn in the internal register, CP
U17 ends the time acquisition determination process and executes other processes until the next new interrupt signal SC is input.

Next, the operation of the pulse period measuring circuit configured as described above will be described. Now, when the count value NA of the counter 12 is "1" and the previous time tn-1 is stored in the internal register of the CPU 17, a new external pulse C
When K is generated, the external pulse detection circuit 11 outputs the rising edge detection signal SA. The counter 12 has a rising detection signal S
Count A and set the count value NA to "2". Since the count value NA (= 2) is not "4" set by the interrupt frequency setting register 13 in the comparison circuit 14, the control signal SB
Is not output. Therefore, the interrupt signal SC is not output from the interrupt generation circuit 15. As a result, the CPU 17 does not perform the time acquisition determination process.

When the next new external pulse CK is generated,
Similarly to the above, the counter 1 is based on the rising detection signal SA.
2 counts the rising detection signal SA and changes the count value NA from "2" to "3". Therefore, since the count value NA is "3", the control signal SB and the interrupt signal SC are not output, and the CPU 17 does not perform the time acquisition determination process even at this time.

When the next new external pulse CK is generated, the counter 12 counts the rising detection signal SA based on the rising detection signal SA and sets the count value NA to "4" in the same manner as described above. The comparison circuit 14 outputs the control signal SB because the count value NA (= 4) coincides with "4" set in the interrupt frequency setting register 13.

The counter 12 is based on the control signal SB.
Is reset and an interrupt signal SC is output from the interrupt signal generation circuit 15. In response to the interrupt signal Sc, the data latch transfer circuit 16 reads the time tn (> tn-1) at that time, which is being counted by the reference time axis generation timer 18, and the time tn is stored at the event occurrence time storage register 19
Transfer to. On the other hand, the CPU 17 executes the time acquisition determination processing in response to the interrupt signal SC. The CPU 17 stores the time tn stored in the event occurrence time storage register 19
Then, the interval TA (= tn-tn-1) is calculated based on the previous time tn-1 stored in the internal register. After obtaining the interval TA, the contents of the internal register are changed from the time tn-1 to the time t.
It is rewritten to n and the time acquisition determination process ends. Then, other processing is executed until the next new interrupt signal SC is input.

As described above, in this embodiment, even if the external pulse CK is generated, the interrupt signal SC is not output to the CPU 17 unless the count value NA of the counter 12 reaches the predetermined number N set by the interrupt frequency setting register 13. . Therefore, every time the external pulse CK is generated, the CPU 1
7 does not perform the time acquisition determination process. As a result, unlike the conventional case, unnecessary time acquisition determination processing is eliminated every time the external pulse CK is generated, and the load on the CPU 17 is reduced accordingly. Then, the CPU 17 can execute other processing by the reduced amount, and the high-speed and efficient program execution of the CPU 17 becomes possible.

The present invention is not limited to the above embodiment, but may be carried out in the following modes. (1) Although the predetermined number N of the interrupt frequency setting registers 13 is set to "4" in the above embodiment, it is not limited to "4" as long as it is plural. Of course, it may be set to "1". (2) The external pulse detection circuit 11 of the above embodiment detects the rising edge of the external pulse CK and outputs the rising edge signal SA, but detects the falling edge of the external pulse CK and outputs the falling edge signal to output the pulse. The interval may be measured. (3) In the above embodiment, the counter 12 is an addition counter that is reset to "1", but it may be a subtraction counter. In this case, the interrupt frequency setting register 13 sets the reset value of the subtraction counter,
The comparison circuit 14 outputs the control signal SB when the count value of the subtraction counter becomes "0", for example. By the way, in the case of the above embodiment, the reset value is "3". (4) As shown in FIG. 3, it can be applied to a pulse cycle measuring circuit in which a data latch transfer circuit 20 and an event occurrence time storage buffer register 21 are provided between a reference time axis generation timer 18 and a data latch transfer circuit 16. Good. That is, the data latch transfer circuit 20 reads the current time of the reference time axis generation timer 18 as the event occurrence time tn in response to the rising edge detection signal S1 of the external pulse detection circuit 11, and the event occurrence time storage buffer register 21 of the next stage. Transfer to.
Then, the data latch transfer circuit 16 reads the event occurrence time tn transferred to the event occurrence time storage buffer register 21 in response to the interrupt signal SC and transfers it to the event occurrence time storage register 19 in the next stage. In this case, the load on the CPU 17 is reduced as in the above embodiment. (5) The pulse cycle measuring circuit may be incorporated in a semiconductor integrated circuit such as a watch microcomputer to be implemented. (6) Although the counter 12 is reset by the control signal SB, it may be reset by the interrupt signal SC.

[0021]

As described in detail above, according to the inventions of claims 1 to 3, the load on the arithmetic unit for calculating the pulse interval over a plurality of external pulses is reduced, and the arithmetic unit is operated at high speed and efficiency. There is an excellent effect that the program can be executed effectively.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram of a pulse period measuring circuit for explaining an embodiment.

FIG. 3 is a block circuit diagram of a pulse period measuring circuit for explaining another embodiment.

FIG. 4 is a block circuit diagram of a conventional pulse period measuring circuit.

FIG. 5 is a waveform diagram for explaining a pulse cycle.

[Explanation of symbols]

 1 external pulse detection circuit 2 counter 3 frequency setting register 4 comparison circuit 5 interrupt signal generation circuit 6 transfer circuit 7 timer 8 time storage register CK external pulse SA detection signal SB control signal SC interrupt signal

Claims (4)

[Claims] 1. An external pulse detection circuit (1) for detecting the rising or falling of an external pulse (CK) and outputting a detection signal (SA), and a detection signal (SA) for the external pulse detection circuit (1). A counter (2) for counting, a frequency setting register (3) in which a predetermined number (N) is set to calculate the generation interval of a predetermined number (N) of external pulses (CK) to be generated, and the counter ( Comparing the count value (NA) of 2) with the predetermined number (N) of the frequency setting register (3) and outputting the control signal (SB) when they match, the control circuit (SB) and the comparison circuit (4) An interrupt signal generating circuit (5) for inputting and outputting an interrupt signal (SC) for executing a calculation of a predetermined number (N) of generation intervals of external pulses (CK) in response to the control signal (SB) , In response to the interrupt signal (SC) A pulse cycle measuring circuit comprising a transfer circuit (6) for transferring the time measured by the timer (7) to the read time storage register (8). 2. A transfer circuit (6) for transferring with a timer (7)
A second transfer circuit (20) and a time storage buffer register (21) are provided between the second transfer circuit (20) and the external pulse detection circuit (1) in response to the detection signal (SA).
Transfers the current time of the timer (7) to the read time storage buffer register (21), and the transfer circuit (6) transfers the time stored in the time storage buffer register (21) in response to the interrupt signal (SC). The pulse period measuring circuit according to claim 1, wherein the pulse period measuring circuit is adapted to transfer to a read time storage register (8). 3. An external pulse (C) generated by inputting an interrupt signal (SC) and responding to the interrupt signal (SC) at the time of the time storage register (8) and the time previously read.
The pulse period measuring circuit according to claim 1 or 2, further comprising a computing device (17) for computing a generation interval of a predetermined number (K) of K). 4. The pulse period measuring circuit according to claim 1, wherein the counter (2) is reset by either a control signal (SB) or an interrupt signal (SC).