JPH08292822A - Intelligent timer - Google Patents

Abstract

PURPOSE: To provide an intelligent timer which can be set to a proper software timer value each time a clock frequency is changed. CONSTITUTION: A CPU 2 sets a constant time according to the reference signal S1 supplied from a reference signal generator 4 and counts how many times the count-up signal S2 is inputted from the timer 1 in the constant time. Then the CPU 2 finds B/A from the frequency A and frequency B of the count-up signal S2 before and after the clock frequency of a clock generation source 3 is changed and multiplies it by a constant C to set the timer value T after the change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intelligent timer, and more particularly to an intelligent timer having a timer value changing function.

[0002]

2. Description of the Related Art If the clock frequency is increased to increase the processing speed, the time until the software timer counts up, that is, the period (timer value) of the software timer is shortened, which may cause inconvenience. For example, when reading a floppy disk such as a personal computer, copy protection is applied by using a technique such as loading the head of the floppy disk drive after a certain period of time with a software timer after detecting an index hole. If so, the time of the software timer becomes short, and there is an inconvenience that the contents of the previous floppy disk cannot be read at all.

Therefore, when the clock frequency is changed,
Each time, the software timer value was reset to an appropriate value.

When changing the clock frequency,
An invention for accurately knowing the changed clock frequency is disclosed in JP-A-64-38814.

According to the present invention, a CPU is provided with a frequency comparison unit.
It is to know the oscillation frequency of the crystal oscillator by comparing the oscillation frequency of the crystal oscillator and the reference frequency.

[0006]

However, JP-A-64-64
The invention of Japanese Patent No. 38814 stops at knowing the oscillation frequency of the crystal oscillator, and the software timer value still has to be reset to an appropriate value each time.

Therefore, an object of the present invention is to provide an intelligent timer capable of setting an appropriate software timer value each time the clock frequency is changed.

[0008]

In order to solve the above-mentioned problems, the present invention is an intelligent timer for generating a start signal in a predetermined cycle according to a clock signal, and a counting for counting the number of times the start signal is generated in a unit time. Means and means for calculating the period of the timer in proportion to the change in the number of times the activation signal is generated when the frequency of the clock signal is changed.

[0009]

When the frequency of the clock signal increases and the number of times the start signal is generated per unit time increases, the timer period is lengthened, and conversely, the frequency of the clock signal decreases and the number of times the start signal occurs per unit time decreases. In this case, the calculation means calculates so as to shorten the period of the timer.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of an intelligent timer according to the present invention. The intelligent timer includes a timer 1 and a CPU (Central P) to which a count-up signal (start signal) is input from the timer 1.
processing unit; central processing unit 2),
A clock generation source (C that drives the timer 1 and the CPU 2
lock Generator; CG) 3 and CPU2
And a reference signal generator 4 for supplying a reference signal to the.

With this configuration, the CPU 2 causes the reference signal S1 supplied from the reference signal generator 4 to perform a predetermined period of time.
The number of count-up signals S2 input from the timer 1 is counted, and the timer value of the timer 1, that is, the cycle of the timer 1 is determined based on this number.

Further, the CPU 2 inputs the timer initial setting signal S3 to the timer 1 and the timer setting signal S4 when the frequency of the clock generation source 3 is changed, and the clock generation source 3 operates the timer 1 to the timer 1. The clock signal S5 for CPU is input to the CPU 2 as the clock signal S6 for CPU operation.

Next, the process of calculating the timer value in the CPU 2 will be described with reference to FIG. Figure 2 is C
6 is a flowchart showing a process of calculating a timer value in PU.

First, at N1, the CPU 2 sets the deviation measurement timer value, that is, the timer initial setting value to the initial setting signal S3.
To set timer 1.

Next, proceeding to N2, the CPU 2 makes the reference signal S1.
Based on the above, a fixed time is set, and the number A of the count-up signal S2 input from the timer 1 is counted during this fixed time. Then, this number of times A is held in a register (not shown) in the CPU 2. Next, the count B of the count-up signal S2 after changing the clock frequency of the clock generation source 3
Is held in another register (not shown) in the CPU 2.

Next, proceeding to N3, the CPU 2 takes out the count A of the count-up signal S2 before change and the count B of the count-up signal S2 after change from the two registers,
The deviation between the number of times A and B is calculated. This deviation is B / A in this embodiment. That is, the ratio of the number B to the number A is the deviation.

Next, in N4, the CPU 2 determines the deviation B
Based on / A, a desired timer value, that is, the changed timer value T is calculated by the following calculation formula.

T = C × (B / A) where C is a positive constant whose number is determined according to the software used. According to this equation, if the value of B becomes larger than the value of A, the value of T also becomes larger. That is, T is proportional to the value of B. This means that when the clock frequency rises and the number of count-ups increases, the timer value T of the timer 1 also increases in proportion to the increase. On the contrary, when the clock frequency decreases and the number of count-ups decreases, the timer value T of the timer 1 also decreases in proportion to the decrease.

Next, proceeding to N5, the CPU 2 sets the timer value T to the timer 1 by the timer setting signal S4. This completes the arithmetic processing.

If the deviation is calculated by BA, for example, T can be obtained by T = A + D (BA). Here, D is a positive constant.

[0021]

According to the present invention, there is provided counting means for counting the number of times a start signal is generated in a unit time, and when the frequency of the clock signal is changed, the period of the timer is proportional to the change in the number of times the start signal is generated. Is configured to be calculated by the calculation means, the timer can be set to an appropriate timer value each time the clock frequency is changed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an intelligent timer according to the present invention.

FIG. 2 is a flowchart showing a process of calculating a timer value in a CPU.

[Explanation of symbols]

 1 timer 2 CPU 3 clock generation source 4 reference signal generator S1 reference signal S2 count up signal S3 timer initial setting signal S4 timer setting signal S5 timer operating clock signal S6 CPU operating clock signal

Claims (4)

[Claims] 1. An intelligent timer for generating a start signal at a predetermined cycle according to a clock signal,
And counting means for counting the number of times the start signal is generated in a unit time; and calculating means for calculating the period of the timer in proportion to the change in the number of times the start signal is generated when the frequency of the clock signal is changed. Intelligent timer featuring. 2. The calculating means calculates a ratio of the number of times of generation of a current start signal to the number of times of generation of a previous start signal,
The intelligent timer according to claim 1, wherein the intelligent timer is a means for calculating a cycle of a current timer by multiplying a cycle of the previous timer by the calculation result. 3. A clock generation source, a timer for generating a start signal at a predetermined cycle according to a clock signal from the clock generation source, a reference signal generator, and a unit time based on a reference signal obtained from the reference signal generator. And a change in the frequency of the clock signal when the frequency of the clock signal is changed, a change in the number of times the activation signal is generated in the unit time is detected, and a central processing unit that calculates the period of the timer in proportion to the change in the number of times is generated. An intelligent timer characterized by including. 4. The central processing unit calculates a ratio of the number of times the present activation signal is generated to the number of times the last activation signal is generated, and multiplies the calculation result by the period of the last timer to calculate the period of the present timer. 4. The intelligent timer according to claim 3, which is a means for calculating