JPH10170564A - Clock frequency measurement circuit, and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a frequency measurement circuit of an ultra-wide band for coping with a specific input clock frequency range by preparing several types of reference clocks and selecting a reference clock and a measurement method according to preliminary measurement. SOLUTION: A reference clock generation circuit 1 generates several types of highly stable reference clocks that are to be the reference of frequency measurement. A reference clock selector 2 selects a reference clock when measuring a frequency. A reference clock counter 3 counts the number of pulses of the reference clock. Then, a clock counter 4 to be measured counts the number of pulses of an input clock pulse signal to be measured. A control part 5 gives the timing for starting and ending measurement to both clock counters 3 and 4, selects the reference clock on preliminary measurement, and judges the measurement method, and calculates the frequency of the input clock pulse signal to be measured after the frequency measurement operation is completed, thus performing an efficient measurement with a measurement error within ±0.01% for the frequency of a wide range of input clock pulse signal to be measured, for example, 2Hz-1MHz.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock frequency measuring circuit and a method thereof, and more particularly to an ultra-wide band clock frequency measuring circuit and a method thereof.

[0002]

2. Description of the Related Art In some cases, it is necessary to measure an ultra-wide band clock such as 2 Hz to 1 MHz. In a conventional clock frequency measuring circuit, for example, as shown in the time chart of FIG.
In some cases, the number N1 of input (clock) pulses is counted every time, and the frequency f1 of the input pulse is calculated from f1 = N1 / T1. In this case, the calculated frequency of the input pulse is as shown in FIG.

However, in this case, since the frequency is measured with a resolution of 1 / T1, there is a problem that sufficient measurement accuracy cannot be obtained. This is due to the fact that the sampling period T1 is not synchronized with the input (clock) pulse, so that a fractional time occurs as shown in FIG.

[0004] Japanese Patent Application Laid-Open No. 1-124773 discloses FIG.
A method has been proposed for measuring the fractional time c using a fractional clock having a period shorter than the sampling period T1. However, in this proposal, measurement cannot be performed if the period of the input (clock) pulse is longer than the sampling period T1.

Japanese Unexamined Patent Publication (Kokai) No. 4-339272 discloses a method of counting pulses of a reference clock included in one cycle of an input (clock) pulse, as shown in FIG. By measuring the number of pulses of the reference clock included in the cycle of the input pulse N2 (adjusted by the input pulse frequency) when measuring the input pulse frequency, an appropriate value corresponding to the input pulse frequency can be obtained. By setting an appropriate measurement time, measurement can be performed with high accuracy and in a short time.

[0006] That is, in FIG.
The value N2 set by the control means 34 comprising a CPU
Just count the input (clock) pulses. The counter 32 generates a start signal when receiving the first input pulse, and generates a stop signal when counting the input pulses by the set value N2. Timer 3
Reference numeral 38 denotes a time period from when the start signal is received from the counter 32 to when the stop signal is received.
(Output), and measures the time value by the control means 34.
Output to The control means 34 determines that the time measurement value is the set value N2.
If the time value is within the range corresponding to the time measurement value, the frequency value corresponding to the time measurement value is calculated and output.
If it is not within the range corresponding to 2, the set value of the counter 32 is changed according to this time measurement value.

However, when the input (clock) pulse frequency is low, it is necessary to increase the number of digits of the counter for counting the input pulses, and the measurement accuracy is increased, but the circuit size remains large. In addition, if the cycle of the input (clock) pulse is shorter than the reference clock (sampling) cycle, measurement cannot be performed.

Japanese Unexamined Patent Publication No. 3-27787 discloses an input pulse signal PG and a time base signal T as shown in FIG.
B. A clock frequency measuring circuit provided with a state machine 46 for inputting a (reference) clock signal CK0 from an oscillator 45 has been proposed.

The clock frequency measuring circuit clears the count by the CCL signal from the state machine 46, counts the pulse signal PG, and counts the (reference) clock signal CK0 from the oscillator 45. 48, state machine 4
Pulse counter 4 by the latch signal RCK from
7, a latch register 49, 40 for latching the count data of each clock counter 48, and a CPU bus 41 coupled to the CPU for providing the count data of these latch registers 49, 40 to the CPU.

The state machine 46 can take five states between S0 and S4, and four registers are defined internally for each state. The state machine 46 transitions between states S0 to S4 in response to a change in two input conditions of PG and TB. And C
When CL = 1, the pulse counter 47 and the clock counter 48 are cleared, and similarly, when the RCK rises, the count data of the pulse counter 47 and the clock counter 48 are latched by the registers 49 and 40, respectively.

In response to an instruction from the state machine 46, the pulse counter 47 changes from "1" to "0" in the next TB from the first rising edge of PG after TB changes from "1" to "0". The number of rising edges of the PG in the period T between the rising edges of the first PG is counted. Further, the clock counter 48 counts the number of pulses of the reference clock signal CK0 during the period T.

Then, the counters 47 and 48 cause the counters 47 and 48 to respectively operate in registers 49 and
At 40, the count data N3 and M3 during the period T3 are latched, and the counters 47 and 48 are cleared of the count data by the CCL signal one pulse after the CK0 signal. The count data N3 and M3 latched by the latch registers 49 and 40 are output to the CPU via the CPU bus 41 by a call from the CPU.
Here, the input pulse frequency f3 is f3 = (N3 / M3)
It is calculated based on CK0. In this case, an input pulse frequency measurable range is, for example, 16 Hz to 120 kHz.

[0013]

SUMMARY OF THE INVENTION FIG.
In the case of the proposal described in Japanese Patent No. 27787, the measurable range of the input pulse frequency is wide, for example, from 16 Hz to 120 kHz.

An object of the present invention is to provide an ultra-wide band clock frequency measuring circuit and a method thereof that can cope with an input clock frequency range of 2 Hz to 1 MHz, for example.

[0015]

SUMMARY OF THE INVENTION A clock frequency selection circuit according to the present invention includes: a reference clock selection means for selectively deriving a plurality of reference clocks having mutually different frequencies; First and second counting means for respectively counting, and counting by the second counting means until the count value of the first counting means reaches a predetermined value. At that time, the first and second counting means Until the count difference of the counting means becomes a value within a predetermined range, the selection of the reference clock selecting means is controlled, and the selected reference clock when the count difference becomes a value within a predetermined range is selected. Control means for counting the clock to be measured by the first and second counting means for a predetermined time; and calculating the frequency of the clock to be measured according to the counting result of the first and second counting means. Wherein the output and means.

The control means determines the magnitude of the frequency between the selected reference clock and the clock to be measured. If the frequency of the clock to be measured is high, the control means terminates counting corresponding to the predetermined time. Means for setting a value in the first counting means.

Further, the control means determines whether the frequency of the selected reference clock and the clock to be measured is large or small, and terminates the counting corresponding to the predetermined time when the frequency of the selected reference clock is large. Means for setting a value to the second counting means.

[0018] The calculating means may include the first and the second.
When the counting result of the counting means is X and Y, and the cycle of the selected reference clock is T, the frequency f of the clock to be measured is calculated by f = Y / (T × X). It is characterized by the following.

The clock frequency measuring method according to the present invention comprises:
A first step of selecting one of a plurality of reference clocks having different frequencies from each other and counting the clock to be measured while counting until the count value of the selected reference clock reaches a predetermined value; and A second step of determining whether or not the count difference reaches a predetermined range and sequentially controlling the selection of the selected reference clock until the count difference reaches the predetermined range; and then counting the selected reference clock and the clock under measurement. The method includes a third step of performing a predetermined time and a fourth step of calculating a frequency of the clock to be measured according to the counting result.

In the third step, the magnitude of the frequency of the selected reference clock and the frequency of the clock to be measured is determined. If the frequency of the clock to be measured increases according to this determination, it corresponds to the predetermined time. The clock to be measured is counted until the count value of the selected reference clock reaches the count end value.

Further, in the third step, the magnitude of the frequency between the selected reference clock and the clock to be measured is determined, and when the frequency of the selected reference clock is increased by this determination, it corresponds to the predetermined time. The selection reference clock is counted until the count value of the measured clock reaches the count end value.

In the fourth step, when the count results of the selected reference clock and the clock to be measured are X and Y, respectively, and the cycle of the selected reference clock is T, the frequency f of the clock to be measured is It is characterized in that it is calculated by f = Y / (T × X).

The operation of the present invention is as follows. Several kinds of reference clocks are prepared. Preliminary measurement is performed to select this reference clock and determine the frequency relationship between the reference clock and the signal to be measured (input clock pulse). Select a clock. In order to perform frequency measurement with high accuracy and in a short time (high efficiency), the frequency ratio between the two signals (input clock and reference clock) must be on a circuit (mainly a counter for counting pulse signals) scale. Accordingly, it must be kept properly. If the frequency ratio is too large, the measurement accuracy is increased, but the measurement time is longer than necessary, or the prepared counter may overflow. Conversely, if the frequency ratio is too small, high-precision measurement cannot be performed. Therefore, it is important to always select the optimal clock.

A clock pulse frequency measurement method is selected according to the result of the preliminary measurement. First, when the input clock frequency is higher than the selected reference clock, N pulses of the selected reference clock are used as the measurement time, and the number of input clock pulses within that time is counted.
Calculate the input clock pulse signal frequency. Conversely, if the input clock frequency is lower than the selected reference clock, N pulses of the input clock pulse are used as the measurement time, and the number of the selected reference clock pulses within that time is counted. Calculate the clock pulse signal frequency. The value of the numerical value N is set to an appropriate value each time based on the result of the preliminary measurement.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a clock frequency measuring circuit according to the present invention.

In FIG. 1, a clock frequency measuring circuit according to the present invention selects a reference clock generating circuit 1 for generating several types of highly stable reference clocks, which serves as a reference for frequency measurement, and a reference clock for performing frequency measurement. A reference clock selector 2 for counting, a reference clock counter 3 for counting the number of pulses of the reference clock, a clock counter 4 for counting the number of pulses of the (measured) input clock pulse signal, and measurement starts for both clock counters 3 and 4. And a control unit 5 for selecting the reference clock and determining the measurement method at the time of preliminary measurement, and calculating the frequency of the (measured) input clock pulse signal after the completion of the frequency measurement operation.

In the operation of the embodiment of the present invention, a preliminary measurement is first performed as shown in the flowchart of FIG. in this case,
The reference clock selector 2 sets it to a predetermined initial position (because the frequency of the measured input clock pulse signal cannot be predicted in advance) (step 11). Next, an appropriate count end value is set to the reference clock counter 3 (the measurement time of the preliminary measurement is determined by the set value) (step 12). The control unit 5 gives a trigger to start measurement, and starts counting up the counters 3 and 4 (step 13).

Until the reference clock counter 3 reaches the set count end value (corresponding to the measurement time),
The measured clock counter 4 counts the number of pulses. It is determined whether or not the reference clock counter 3 has reached the set count end value (step 14).
In the case of O, the counting is continued, and in the case of YES, the operations (counting) of the counters 3 and 4 are stopped at that point, and the control unit 5 acquires the count value of the clock counter 4 to be measured (step 15). At this time, it is confirmed that the counters 3 and 4 do not overflow.

From the count end value of the reference clock counter 3 set in step 12 and the count value of the measured clock counter 4 obtained in step 15, selection of a frequency measurement reference clock and determination of a frequency measurement method are possible. ?) (Step 16) is performed.

However, if the frequency difference between the reference clock used for the preliminary measurement and the input clock is too large, or conversely too small (NO), the reference clock for the preliminary measurement is set to the reference clock selector. The pre-measurement operation of steps 11 to 16 is repeated until the frequency difference becomes an appropriate value (a preset value).

When the frequency difference between the selected reference clock and the input clock pulse signal to be measured has the above-mentioned appropriate value (step 17), the reference clock and the measured signal are measured as follows. It is divided into which one of the input clock pulse signal and the frequency is higher (step 18).
And start measuring the frequency.

First, when the input clock pulse signal to be measured is faster than the selected reference clock (period T), the reference clock counter 3 gives an appropriate (determined from the preliminary measurement result) count end value "X". Is set (step 19). The timing of the measurement end (measurement time) is determined by the set value.

A trigger to start measurement is given from the control unit 5,
The counters 3 and 4 start counting up (step 20). Until the reference clock counter 3 reaches the set count end value (measurement time), the measured clock counter 4 counts the number of pulses. It is determined whether the reference clock counter 3 has reached the set count end value (measurement time) and the count has ended (step 21). If NO, the count is continued. 5 acquires the count value "Y" of the clock counter 4 to be measured (step 22).

The measurement time (T ×
X), and the measured input clock pulse signal frequency (f) is given by f = Y / (T × X) from the count value “Y” of the measured clock counter 4 acquired in step 21 (step 27). . FIG. 3 shows a timing chart in this case.

Next, when the input clock pulse signal to be measured is later than the selected reference clock (period T), an appropriate (determined from the preliminary measurement result) count end value is supplied to the clock counter 4 to be measured. Y "is set (step 23). The timing (the number of pulses) at which measurement ends is determined by the set value.

A trigger to start measurement is given from the control unit 5,
The counters 3 and 4 start counting up (step 24). Until the measured clock counter 4 reaches the set count end value (number of pulses), the reference clock counter 3 counts the number of pulses. The measured clock counter 4 reaches the set count end value (the number of pulses), and determines whether or not the count is completed (step 25). If NO, the count is continued, and if YES, the control is performed. The unit 5 acquires the count value “X” of the reference clock counter 3 (Step 26).

From the number of pulses set in step 22 and the count value “X” of the reference clock counter 3 obtained in step 25, the input clock pulse signal frequency (f) to be measured is f = Y / (T × X). (Step 27). FIG. 4 shows a timing chart in this case.

As described above, with respect to the selected reference clock, two measurement methods are employed, ie, when the frequency of the input clock pulse signal to be measured is high and when the frequency is low, and the count end value "X" or "Y" is used. By setting an appropriate value in accordance with the frequency difference, highly accurate and efficient ultra-wide band frequency measurement can be performed.

The following cases will be described as specific examples (numerical examples) of the present invention. First, 1 MHz (T = 1 μs) and 1 kHz (T = 1 m
s) are prepared. A 16-bit (0-65535) counter is used as each of the reference clock counter 3 and the clock counter 4 to be measured. The control unit 5 uses a CPU to control the entire clock frequency measurement circuit.
Judgment of preliminary measurement results, frequency calculation, etc. are performed. In this case, the frequency of the input clock pulse signal to be measured is high: 1M
With respect to three examples of Hz, low speed: 2 Hz, and medium speed: 1 kHz, measurement methods and examples of measurement accuracy will be described.

High speed: 1 MHz, control unit (CPU)
5 is 1 kHz as the reference clock from the result of the preliminary measurement.
Select z. The count end value “X” of the reference clock counter 3 is set to an appropriate value. In this case, X = 10
Set as The control unit 5 gives a count start trigger to both counters 3 and 4 to start clock frequency measurement. Assuming that the reference clock and the input clock to be measured are asynchronous, the obtained count value “Y” of the clock counter 4 to be measured is expected to be in the range of 10,000 ± 1.

In this case, the frequency (f) of the input clock pulse to be measured is calculated as follows: f = 10,000 / (1 ms × 10) = 1.0000 MHz Y = 10,001 / f = 10,001 / ( 1ms × 10) = 1.0001 MHz When Y = 9,999, f = 9,999 / (1ms × 10) = 0.9999 MHz That is, the measurement error is theoretically within ± 0.01%.

Low speed: 2 Hz, control unit (CPU) 5
Is 1 kHz as the reference clock from the result of the preliminary measurement.
Select The count end value “Y” of the measured clock counter 4 is set to an appropriate value. In this case, Y = 20
Set as The control unit 5 gives a count start trigger to both counters 3 and 4 to start clock frequency measurement. Assuming that the reference clock and the input clock to be measured are asynchronous, the obtained count value “X” of the reference clock counter 3 is expected to fall within the range of 10,000 ± 1.

In this case, the calculated frequency (f) of the input clock pulse to be measured is f = 20 / (1 ms × 10,000) = 2.0000 Hz when X = 10,000, f = 20 / (X = 10,001) (1ms × 10,001) = 1.9998Hz When X = 9,999, f = 20 / (1ms × 9,999) = 2.0002Hz That is, the measurement error is theoretically within ± 0.01%.

Middle speed: 1 kHz, control unit (CPU)
5 is 1 MH as the reference clock from the result of the preliminary measurement.
Select z. The count end value “Y” of the measured clock counter 4 is set to an appropriate value. In this case, Y = 1
Set to 0. The control unit 5 gives a count start trigger to both counters 3 and 4 to start clock frequency measurement. Assuming that the reference clock and the input clock to be measured are asynchronous, the obtained count value “X” of the reference clock counter 3 is expected to fall within the range of 10,000 ± 1.

In this case, the calculated frequency (f) of the input clock pulse to be measured is: f = 10 / (1 μs × 10,000) = 1.0000 kHz when X = 10,000 f = 10 / (when X = 10,001) 1 μs × 10,001) = 0.9999 kHz When Y = 9,999, f = 10 / (1 μs × 9,999) = 1.0001 kHz That is, the measurement error is theoretically within ± 0.01%.

In the case of the present example, the frequency of ± 0.
Efficient frequency measurement is possible with a measurement error within 01%.

[0048]

As described above, the present invention prepares several kinds of reference clocks, selects a reference clock and a measuring method by preliminary measurement, and selects a wide range of input clock pulse signals to be measured, for example, from 2 Hz to 1 MHz. This has the effect of enabling efficient frequency measurement with a measurement error within ± 0.01% with respect to the above frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of frequency measurement according to the embodiment of the present invention.

FIG. 3 is a timing chart when an input clock is faster than a reference clock.

FIG. 4 is a timing chart when an input clock is later than a reference clock.

FIG. 5 is a timing chart of an example of a conventional clock frequency measurement circuit.

FIG. 6 is a block diagram of another example of a conventional clock frequency measurement circuit.

FIG. 7 is a block diagram of still another example of the conventional clock frequency measurement circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reference clock generation circuit 2 Reference clock selector 3 Reference clock counter 4 Clock counter under measurement 5 Control part

Claims (8)

[Claims] 1. A reference clock selecting means for selectively deriving a plurality of reference clocks having different frequencies from each other, and first and second counting means for counting the selected reference clock and the clock to be measured, respectively. And counting the second counting means until the count value of the first counting means reaches a predetermined value. At that time, the difference between the counts of the first and second counting means is within a predetermined range. The selection of the reference clock selecting means is controlled until the value becomes a value, and the selected reference clock and the clock to be measured when the count difference becomes a value within a predetermined range are set for the first and second times. Control means for counting by the second counting means; and the first and second control means.
And a calculating means for calculating the frequency of the clock under measurement according to the counting result of the counting means. 2. The control means according to claim 1, wherein said control means determines a magnitude of a frequency between said selected reference clock and said clock to be measured, and terminates counting corresponding to said predetermined time when said clock to be measured becomes high in frequency. 2. A clock frequency measuring circuit according to claim 1, further comprising means for setting a value in said first counting means. 3. The control unit determines a magnitude of a frequency between the selected reference clock and the clock to be measured. When the frequency of the selected reference clock is large, the control unit terminates counting corresponding to the predetermined time. 2. A clock frequency measuring circuit according to claim 1, further comprising means for setting a value in said second counting means. 4. The calculating means sets the frequency f of the clock to be measured assuming that the count results of the first and second counting means are X and Y, respectively, and the cycle of the selected reference clock is T. 4. The clock frequency measuring circuit according to claim 2, wherein f = Y / (T × X) is calculated. 5. A first step of selecting one of a plurality of reference clocks having different frequencies from each other and counting the clock to be measured while counting until the count value of the selected reference clock reaches a predetermined value; A second step of determining whether or not the count difference between the two count values reaches a predetermined range and sequentially controlling the selection of the selected reference clock until the count difference reaches the predetermined range; A clock frequency measuring method, comprising: a third step of counting a clock for a predetermined time; and a fourth step of calculating a frequency of the clock to be measured according to the counting result. 6. In the third step, the magnitude of the frequency of the selected reference clock and the frequency of the clock to be measured is determined, and if the frequency of the clock to be measured increases by this determination, it corresponds to the predetermined time. 6. The clock frequency measuring method according to claim 5, wherein the clock to be measured is counted until the count value of the selected reference clock reaches the count end value. 7. In the third step, a magnitude of a frequency between the selected reference clock and the clock to be measured is determined, and when the frequency of the selected reference clock is increased by the determination, the predetermined time is corresponded. 6. The clock frequency measuring method according to claim 5, wherein the counting of the selected reference clock is performed until the counted value of the clock to be measured reaches the counting end value. 8. The method according to claim 4, wherein the counting results of the selected reference clock and the clock to be measured are X and Y, respectively.
8. The clock according to claim 6, wherein when a cycle of the selected reference clock is T, a frequency f of the clock to be measured is calculated by f = Y / (T × X). Frequency measurement method.