JPS6061662A - Digital speed detection system - Google Patents

Abstract

PURPOSE:To realize a highly accurate detection with the minimum delay time by managing the delay in and the accuracy of the detection independently of each other. CONSTITUTION:Output signals from a pulse generator are inputted into a counter 4 through a waveform shaping circuit 3 to count. The counter 4 is set by a counter synchronous signal from a control signal generation circuit 6 at a fixed time interval. A data latch 5 latches counts immediately before the resetting of the counter 4. A CPU1 reads pulse counts latched with the data latch 5 and executes the computation for the detection of speed according to a specified algorism.

Description

[Detailed Description of the Invention] [Technical Field to Which the Invention Pertains] This invention relates to measurement of continuous pulse frequencies, particularly to a speed detection method of a rotating machine using a pulse generator [Prior art and its problems] In this type of speed detection, It is required to perform stable and highly accurate detection in a short time, that is, to minimize the delay of the detected value with respect to the actual speed value.

Generally speaking, speed detection methods for rotating machines using pulse generators include (1) a method that counts the number of pulses generated within a certain period of time (method that measures the period of the generated pulses (3) (1);
A method that combines the two methods is widely used. Among these methods, the method that measures the period of force has the following problems: the measurement time varies greatly depending on the frequency (velocity), and the detection accuracy is limited by the manufacturing precision of the pulse generator. In addition, the method (3) is not often used because of the
Considering the above method, there is a relationship as shown in FIG. 1 between the actual speed value and the detected value. Note that FIG. 1 is a timing chart showing the relationship between actual speed and detected value (measured value). In FIG. 1, the detected speed value ωd(k) detected at time t-kT is nothing but the average speed of the actual speed value ω(1) up to t=(k-1)T-kT. Moreover, this ωa (k) is expressed as time t−(k+l)
Since the data is not updated until the next detected speed value ωd(Ic+l) is detected in T, the detected speed values ω are equal when considered in a continuous time system. (1) is the actual speed value ω(1)
Using a delay τ equivalent to , it can be expressed as in the following equation (1). Moreover, this delay τ, that is, the sampling period T
is decomposed as shown in equation (2).

ωe(t)−ω(−τ) ・・・・・・(1) T τ=・−”−1 ・・・・・・(2) 2 In equation (2), the first term on the right side is the delay due to the detected value being the average velocity, and the second term is due to the effect of the holder on the sampling operation.

Therefore, in such a speed detection method, the sampling period T may be shortened in order to reduce the detection delay. However, since the detection accuracy (error) is inversely proportional to the measurement time T, shortening the sampling period T reduces the detection accuracy at the cost of reducing the detection delay. Conversely, if the sampling period T is determined, the detection accuracy is also determined by it, and a system with a short sampling period will not be able to detect speed with high accuracy. In other words, in the conventional speed detection method, shortening the detection delay and increasing detection accuracy are mutually contradictory matters, so a drawback is that it is not possible to shorten the delay time and perform high-precision speed detection. However, this is due to the fact that detection delay and accuracy are not managed independently of each other.

[Purpose of the invention]

The present invention has been made in view of the above points, and by managing detection delay and detection accuracy independently of each other in a speed detection method using a pulse generator, highly accurate speed detection can be achieved with the minimum delay time. The aim is to realize this.

[Key points of the invention]

The key point is that in the speed detection method using a pulse generator, the sampling period and measurement time are managed independently by performing speed detection calculations at each sampling point using data from several previous samplings. It is something. As a result, the frequency of updating the speed detection value (inversely proportional to the sampling period) is increased, that is, the delay in equivalent detection is kept small, and the detection accuracy (proportional to the measurement time) is improved.

[Embodiments of the invention]

<A) In the case of a method based on counting the number of pulses generated within a certain period of time Figure 2 shows how the present invention is applied to the ``method of counting the number of pulses generated within a certain period of time'' mentioned above as prior art (1). 3 is a timing chart of speed detection according to the present invention, and FIG. 4 is a flowchart 1 for explaining the operation of FIG. 2.

As is clear from FIG. 2, this embodiment is composed of a digital processing unit (CPU) 1 such as a microprocessor, a memory 2, a waveform shaping circuit 3, a counter 4, a data latch 5, a control signal generation circuit 6, etc. be done.

lit force signal A from a pulse generator not shown
After being subjected to waveform shaping and logical operation processing by the waveform shaping circuit 3, the signal is manually inputted to the counter 4 as a counter drive pulse signal B. The counter 4 counts the pulses from the pulse generator using the counter drive Φb pulse (ΔB) of C, and controls the illumination at every fixed time T.
Due to the counter synchronization number 1d from the i-th signal generation circuit 6,
81 Reset the numerical values. The data latch 5 launches the count value C of the counter 4 immediately before being reset in response to the data latch signal E from the control signal generation circuit 6. That is, the data latched in the data latch 5 does not represent the number of pulses generated by the pulse generator during time T. The CPU starts an interrupt processing program (see Fig. 4) for speed detection value calculation using a fixed period interrupt signal F generated by the control signal generation circuit 6 every hour, and outputs data via the data control bus G. The pulse count value latched in the latch 5 is read and speed detection calculation is executed according to a predetermined algorithm.

Now, the count value of m raw pulses of the pulse generator of 0ulJ t=(k-1)T~kT is calculated as same as C11, time t=(k-n)T~(Ic-n+1)T(
: If the pulse count value of n-1v L-) is Cn, the average speed vk at time 1 = (k-n)T-kT is expressed by the following formula (3) '11'D Note that TD is , TDmi, 1ril... (4). At this time, the equivalent delay τ of the speed detection value is expressed as the following equation (5) in the same manner as equation 21.

Considering a system in which the measurement time TD is predetermined, the detection delay τ can be expressed as the following equation by transforming equation (5).

1 τ-TD(-i15) (6) This is n+1/2 n (2 (n+1
) / nT ). For example, n=
Considering the case of 5, the delay is reduced to 60 in the conventional system. Conversely, if we consider a system in which the calculation period T is predetermined, the speed detection value is updated every calculation period T, whereas the accuracy of the speed detection value is determined by the measurement time TD =
Guaranteed by nT. That is, compared to the case where the measurement time and the calculation cycle are made equal, it is possible to detect the speed with n times precision.

Timing charts and program flowcharts based on the above algorithm are shown in FIGS. 3 and 4, respectively, and although these seem to be clear from the above explanation, some additional explanation will be given here. The timing chart in Fig. 3 is an example when the measurement time TD is set to 5 times the zumbling period T (n=s), and ■(ri is the actual speed value, vi is the detected speed value at t=iT, respectively. On the other hand, in the flowchart of Fig. 4, ■ is the part where the pulse count value is read, and O is the part where the pulse count value is read.
is the part that calculates the speed Vk in the above equation (3), and O is the part that updates the pulse count value Ci.

(It) Counting the number of pulses and generating pulses 7, (7
Figure 5 shows the dl of the number of pulses generated within a certain period of time mentioned above.
6 is a configuration diagram showing an embodiment in which the present invention is applied to a known speed detection method that combines speed measurement and period measurement.
Figure A is a waveform diagram of each part to explain the speed detection principle.
FIG. 6B shows waveforms of various parts for explaining the speed detection operation according to the present invention. As is clear from No. 51, this embodiment uses a data processing device 1 such as a microprocessor.
, a memory 2, a waveform shaping circuit 3, a pulse counter 4, data latches 5 and 8, a control signal generation circuit 6, a timer 7, and the like. The output signal A (see FIGS. 6A and 613) from a pulse generator (not shown) is subjected to waveform shaping and logical operation processing by the waveform shaping circuit 3, and then outputted to the counter drive pulse signal B (see FIGS. 6A and 6B). (see e)) is input to the pulse counter 4 and timer 7. The pulse counter 4 calculates the aI of the pulse from the pulse generator based on the counter drive pulse signal B.
The counter synchronization signal D from the control signal generation circuit 6 is generated every fixed time T (see Figures 6A and 6I3 (c)).
The count value is reset by . Data latch 5 is
Data latch signal E from control signal generation circuit 6 (6th A
, 6B ←)), the count value C of the pulse counter 4 immediately before being reset is latched.

That is, the data latched in the data latch 5 represents the number of pulses generated by the pulse generator during the measurement time T. The timer 7 receives the basic clock pulse I from the control signal generation circuit 6 (see Fig. 6A + 6B (a)).
The count value is reset by the counter drive pulse signal B. The data latch 8 launches the H] value of the timer 7, that is, the elapsed time Pi from the time of the last pulse generation, in response to the data latch signal E from the control signal generation circuit 6. In other words, it is known that the general operation of such a system is as shown in the figure at beat 6, which is the same as in the past, and the detected velocity value vk at time t=kT is expressed as follows. However, CI=H]
represents the number of pulses of the pulse generator of t-(k-1) T-kT, and Pn is t-(lc-n)T
From the time of pulse generation immediately before , the yambbling point (1=(k
-n) represents the elapsed time until T). On the other hand, the operating waveform diagram when the present invention is applied to such a known speed detection method is as shown in FIG.
The speed detection value Vk at T is expressed as follows by applying the concept of equation (3) above to equation (7). Note that Ci is the number of pulses of the pulse generator from t-(k-i)T to (k-i+1)T. The accuracy of the speed detector in this case is guaranteed by l1lD (=nT),
The equivalent detection delay τ is expressed by the following equation.

τ-TD/2 +T/2 = (n+1) T/2 = (1-F-!-) 'l
'D/2 - (9) wSI diagram is a flowchart for explaining the operation of FIG. 5, and corresponds to the previous FIG. 4.

That is, after receiving the interrupt fTji, reading the pulse count value (Ci) (see ■) and reading the elapsed time since the last pulse generation (see 0), the speed calculation based on the above equation (8) is performed. Perform t7 (see L/3)
, the pulse count value (Ci) and the elapsed time value (Pi) are updated (◯, ■g rp-t), and the series of processing is completed.

〔Effect of the invention〕

According to the present invention, the following effects can be expected.

(1) By dividing the sampling period (T) into 1/n of the measurement period (TD) used for speed detection calculation, the equivalent detection delay can be reduced while maintaining speed detection accuracy. Can be made smaller. That is, the speed detection value can be updated at a shorter period than the measurement time.

(2) Even in a speed detection system with a short sampling period (T), the measurement time (TD) is
Since the speed can be set arbitrarily to double the speed, the required speed detection accuracy can be easily obtained.

(3) Even in a system with a short sampling period, since the measurement time can be long, it is possible to detect the speed at which the output frequency of the pulse generator reaches a low speed value J where the output frequency becomes low.

(4) The present invention can be realized by simply adding a function of storing sample data of the past n-1 times to a conventional speed detection system using a pulse generator. In other words, since a speed detection system using a microprocessor-based arithmetic processing unit necessarily includes a memory, this function can be easily realized. Therefore,
When applying the present invention to a conventional speed detection system, no hardware changes or additions are required at all.

(5) Depending on the rotational speed of the rotating machine, that is, the output frequency of the pulse generator, n' of the third, fourth or eighth equation.
f: switching, the data update degree ← ripple period required for a speed detector remains constant, and only the measurement time is made variable. High speed detection can be performed.

[Brief explanation of the drawing]

Fig. 1 is a timing chart for explaining the conventional speed detection method, Fig. 2 is a configuration diagram without showing an embodiment of the present invention, Fig. 3 is a timing chart for explaining its operation, and Fig. 3 is a timing chart for explaining its operation. 4 is a 70-diameter diagram, FIG. 5 is a block diagram showing another embodiment of the present invention, FIG. 6A is a waveform diagram for explaining a general speed detection operation, and FIG. 6B is another embodiment. Waveform diagram to explain speed detection based on the operation, part 7
The figure is a 70-chart for explaining the operation of FIG. Description of symbols 1... Data processing device (microphone 11 computer)) 2... Memory, 3... Waveform shaping circuit, 4... Song counter, 5, 8... ...Data latch, 6...Control signal generation circuit, 7...
・Timer agent Patent attorney Kiyoshi Matsuzaki ■ Figure 2L blow 6A Zuman (Figure 18/' Finished Lh I CV

Claims (1)

[Claims] A pulse generator provided corresponding to a rotating machine and generating pulses according to its rotation speed, a counting means for counting the pulses, a sampling means for sampling the number of pulses at a predetermined period, and the sampling In a digital speed detection method comprising a memory means for storing the stored pulse number while updating it sequentially, and an arithmetic processing means for performing a speed detection calculation based on the stored pulse number, the speed detection calculation in the arithmetic processing means is performed. The relationship between the time for and the sampling period is n:l (n is a positive integer)
A digital speed detection method characterized by: