CN117110707B - SOC integrated chip, frequency measurement circuit and frequency measurement method - Google Patents

Abstract

The invention provides an SOC integrated chip, a frequency measurement circuit and a frequency measurement method, which are applied to the technical field of electronic and time-frequency measurement. Specifically, an input end of the measurement period generating module is connected with a measurement period self-adaptive adjusting module, so that an adjusted measurement period is generated and output through the measurement period self-adaptive adjusting module, continuous adjustment of the test period is achieved, and based on the continuously adjusted measurement period, a counter is used for sampling and counting a clock to be measured for multiple times, so that the frequency of the clock to be measured is finally obtained. The frequency measuring circuit provided by the invention can measure the high-speed clock in the high-speed SOC integrated chip and any other clocks with different frequencies, and as a large amount of operations are carried out on the software layers of the measuring period self-adaptive adjusting module and the comparison memory, the complexity of the IC circuit design can be effectively reduced, the debugging time of the chip can be effectively reduced, the time cost can be saved, and the business and updating efficiency can be accelerated.

Description

SOC integrated chip, frequency measurement circuit and frequency measurement method

Technical field

The invention relates to the technical fields of electronics and time-frequency measurement, and in particular to a SOC integrated chip, a frequency measurement circuit and a frequency measurement method.

Background technique

Since current ultra-large-scale data centers require network switching bandwidth of 12.8Tbps or even higher, the demand for high-speed photoelectric transceiver chips in data centers is becoming increasingly urgent. As the service rates carried by transceiver chips are getting higher and higher, especially high-speed service signals have higher requirements for clock frequency and type. Therefore, high-speed SOCs need to support a wider range of clock rates.

The clock frequency refers to the frequency of the reference clock signal running inside the chip, which determines the operating speed of each functional module inside the chip. In high-speed chips, the measurement of clock frequency is very important for the following reasons: 1. Performance evaluation: Clock frequency is one of the key indicators for evaluating chip performance. By measuring the clock frequency of the chip, you can understand the highest operating frequency that the chip can achieve, thereby evaluating whether the chip's performance meets the design requirements; 2. Troubleshooting: In high-speed chips, the accuracy of the clock signal is crucial to the normal operation of the chip. By measuring the clock frequency, it can be determined whether the clock signal is stable and whether there are problems such as clock offset or clock jitter, which is crucial for troubleshooting and debugging; 3. Synchronization and protocol: High-speed chips usually require complex Synchronization and protocol processing, and these operations are usually based on clock signals. By accurately measuring the clock frequency, the correctness of the timing relationship between various functional modules can be ensured, thereby ensuring the normal operation of the chip. Therefore, clock frequency measurement is very important in high-speed chips and involves critical aspects such as chip performance evaluation, troubleshooting, and synchronization and protocols. Accurate clock frequency measurement ensures proper chip operation and optimized performance.

However, as the design complexity of transceiver chips increases, the frequency of clocks becomes higher and higher. Therefore, how to effectively detect and measure the frequency of each high-speed clock has become a difficulty to be solved by those skilled in the art.

Contents of the invention

The technical problem to be solved by the present invention is to overcome the deficiencies of the existing technology and propose a SOC integration that combines software and hardware with greater adaptability, can adaptively learn to adjust the measurement cycle, is compatible with a variety of measurement ranges, and can improve measurement accuracy. Chip, frequency measurement circuit and frequency measurement method.

In the first aspect, in order to solve the above technical problems, the frequency measurement circuit is characterized by including:

A measurement period generation module, connected to the measurement period adaptive adjustment module, for generating and outputting an adjustment based on the adjustment period generated by the measurement period adaptive adjustment module after generating and outputting an initial value of the measurement period according to the period of the reference clock. subsequent measurement period.

A periodic pulse generation module, connected to the reference clock and connected with the measurement period generation module and the cross-clock domain circuit, for intermittent generation and outputting to the cross-clock domain circuit a clock domain consistent with the reference clock. The same first periodic pulse signal, wherein the period of the first periodic pulse signal is the measurement period.

A cross-clock domain circuit is connected to a clock to be tested and connected to a counter for adapting the first periodic pulse signal to a second periodic pulse signal that is the same as the clock domain of the clock to be tested, wherein the The period of the second periodic pulse signal is the measurement period.

A counter, connected to the clock to be tested and connected to the comparison memory, for using the second periodic pulse signal to sample and count the clock to be tested multiple times, and sending the counting results to the comparison memory for storage.

A comparison memory, connected to the decision module, is used to compare with the maximum value and/or minimum value of the stored counting result after receiving the counting result. If it is greater than the maximum value of the stored counting result, The counting result is used as the new maximum value of the counting result. If it is smaller than the stored minimum value of the counting result, the counting result is used as the new minimum value of the counting result, and then the new maximum value of the counting result is summed. The minimum value is stored and sent to the decision module.

A decision module connected to the measurement cycle adaptive adjustment module for comparing the difference between the new maximum value and the minimum value of the counting result. If the difference value is not within the preset range, automatically adjust the measurement cycle to the measurement cycle. The adaptation adjustment module sends a start command.

The measurement period adaptive adjustment module is configured to form an adjustment period according to a preset adaptive algorithm after receiving the startup instruction, and send the adjustment period to the measurement period generation module.

In some optional embodiments, the frequency measurement circuit may further include: a measurement start module connected to the measurement cycle generation module, and configured to send the frequency measurement start instruction to the measurement cycle after receiving the frequency measurement start instruction sent by the host computer. The period generation module sends parameter information of the reference clock, where the parameter information includes a period.

In some optional embodiments, the frequency measurement circuit may be applied to a SOC integrated chip, and the SOC integrated chip may include multiple clock signals.

In some optional embodiments, the frequency measurement circuit may further include: a clock selection module that accesses the multiple clock signals and is connected to the cross-clock domain circuit and the counter for selecting from the Select a clock signal from multiple clock signals as the clock to be tested, and send the selected clock to be tested to the cross-clock domain circuit and the counter.

In some optional embodiments, the frequency measurement circuit further includes: a counting measurement module, connected to the decision module, for comparing the new maximum value and minimum value of the counting result in the decision module. When the difference value is within the preset range, the frequency of the clock to be measured is calculated and output.

In a second aspect, based on the same inventive concept, the present invention also proposes a SOC integrated chip. Specifically, the SOC integrated chip may include the frequency measurement circuit as described above.

In a third aspect, based on the same inventive concept, the present invention also proposes a frequency measurement method, which may include the following steps:

Determine the period of the reference clock to form the measurement period.

Based on the measurement period and the parameter clock, a first periodic pulse signal that is the same as the clock domain of the reference clock is formed.

The clock to be tested is determined, and the first periodic pulse is processed across clock domains based on the clock to be tested, to obtain a second periodic pulse signal that is the same as the clock domain of the clock to be tested.

The second periodic pulse signal is used to sample and count the clock to be measured to obtain the current counting result.

Compare the current counting result with the maximum value and/or minimum value of the pre-stored counting result, and determine the updated maximum value and minimum value of the counting result based on the comparison result.

Compare the updated maximum value and minimum value of the counting result. If the difference between the maximum value and the minimum value is not within the preset range, use an adaptive learning algorithm to form an adjustment cycle, and return to execute the forming process. The step of measuring a period to form an adjusted measurement period based on the adjustment period.

In some optional embodiments, the first periodic pulse signal and the second periodic pulse signal have the same period, and both are the measurement period.

In some optional embodiments, the step of determining the updated maximum value and minimum value of the counting result based on the comparison result may specifically include:

If the current counting result is greater than the maximum value of the pre-stored counting result, the current counting result is used as the updated maximum value of the counting result.

If the current counting result is smaller than the minimum value of the pre-stored counting result, the current counting result is used as the updated minimum value of the counting result.

In some optional embodiments, the frequency measurement method may further include: if the difference between the updated maximum value and the minimum value of the counting result is within a preset range, updating the counting result based on the The step of obtaining the frequency of the clock to be measured from the maximum or minimum value.

In some optional embodiments, the preset range of the difference value may specifically be: 1~2, and is preferably 1.

In a fourth aspect, the present invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory complete communication with each other through the communication bus;

Memory, used to store computer programs;

The processor is used to implement the steps of the frequency measurement method as described above when executing the program stored in the memory.

Compared with the prior art, the present invention has the following beneficial effects:

In a frequency measurement circuit provided by the present invention, an input end of the measurement period generation module is connected to a measurement period adaptive adjustment module, so that the measurement period output by the measurement period adaptive adjustment module is used to adjust the measurement period. Adjust the cycle to obtain the adjusted measurement cycle, and then based on the continuously adjusted measurement cycle, count the rising edge or falling edge of the clock to be measured multiple times, and when the difference between the maximum value and the minimum value of the counting result is within the preset range , only then the cycle counting is stopped, and the frequency of the clock under test is finally obtained.

Since the frequency measurement circuit provided in the present invention does not limit the frequency range to be measured, it can not only measure the high-speed clock in the high-speed SOC integrated chip, but also can measure any other clocks with different frequencies. Therefore, the present invention The frequency measurement circuit provided is more adaptable, can adaptively learn to adjust the measurement period, is compatible with a variety of measurement ranges, and improves measurement accuracy.

Moreover, when the present invention measures the frequency of the clock to be measured, the maximum or minimum value of the counting result used to determine the frequency of the clock to be measured will not be updated as the measurement cycle is adjusted, until the counting result reaches When the difference between the maximum value and the minimum value is 1, it means that the adjusted measurement period reaches the target measurement period, and the frequency calculated based on the target measurement period is the most accurate.

Furthermore, since the present invention places a large number of operations on the software level of the measurement cycle adaptive adjustment module and the comparison memory, the main design idea of the frequency measurement circuit provided by the present invention is the combination of software and hardware, and based on this design The frequency measurement circuit of Idea can effectively reduce the complexity of IC circuit design, effectively reduce chip debugging time, save time and cost, and accelerate the commercialization and update efficiency of chips as soon as possible.

Description of the drawings

Figure 1 is a circuit schematic diagram of a frequency measurement circuit provided in some embodiments of the present invention.

Figure 2 is a schematic flow chart of a frequency measurement method provided in some embodiments of the present invention.

Detailed ways

In order to make the purpose, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, each drawing needs to display different emphasis, and sometimes uses different proportions.

As used in this invention, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in its sense including "and/or", and the term "several" The term "at least two" is usually used in a meaning including "at least one", and the term "at least two" is usually used in a meaning including "two or more". In addition, the terms "first" and "th "Second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying the relative importance or implicitly indicating the quantity of the technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of these features, "one end" and "other end" and "proximal end" and "Remote" usually refers to the two corresponding parts, which not only includes the endpoints. The terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection, or Integrated; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. In addition, as used in the present invention, one element is disposed on another element, which usually only means that there is a connection, coupling, matching or transmission relationship between the two elements, and the relationship between the two elements may be direct or indirect through an intermediate element. connection, coupling, cooperation or transmission, and cannot be understood as indicating or implying the spatial positional relationship between two elements, that is, one element can be in any position inside, outside, above, below or to one side of another element, unless the content Also clearly stated. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

As mentioned in the background art, frequency has always been one of the most basic parameters in electronic technology, and is closely related to many electrical parameter measurement plans and measurement results. Therefore, frequency measurement is also particularly important. However, as the design complexity of transceiver chips increases, the frequency of clocks becomes higher and higher. Therefore, how to effectively detect and measure the frequency of each high-speed clock has become a difficulty to be solved by those skilled in the art.

Therefore, the present invention proposes a SOC integrated chip, a frequency measurement circuit and a frequency measurement method that are more adaptable, can adaptively learn to adjust the measurement cycle, are compatible with a variety of measurement ranges, and can improve measurement accuracy by combining software and hardware.

A frequency measurement circuit of the present invention will be described in further detail below. The invention will now be described in more detail with reference to Figure 1, in which a preferred embodiment of the invention is shown, it being understood that those skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Therefore, the following description should be understood as being widely known to those skilled in the art and is not intended to limit the present invention.

Referring to Figure 1, a frequency measurement circuit provided in an embodiment of the present invention may specifically include: a measurement start circuit 10, a measurement period generation module 20, a periodic pulse generation module 30, a cross-clock domain circuit 40, a clock selection module 50, and a counter. 60. Comparison memory 70, decision module 80, measurement period adaptive adjustment module 90 and counting measurement module 100; wherein,

The measurement startup circuit 10 includes an input terminal and an output terminal. The input terminal is used to receive the frequency measurement startup command sent by the host computer and the parameter information of the reference clock, such as the period (period value) of the reference clock. The output terminal is connected to the The measurement period generation module 20 is connected and used to send the received period of the reference clock to the measurement period generation module 20 .

The measurement period generation module 20 includes a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the output terminal of the measurement start circuit 10 , and the second input terminal is connected to the measurement period. The output end of the adaptive adjustment module 90 is connected, and its output end is connected to the periodic pulse generation module 30, so as to generate and output the initial value of the measurement period according to the period of the reference clock, and automatically adjust the measurement period based on the measurement period. Adapting the adjustment period generated by the adjustment module 90 generates and outputs an adjusted measurement period.

The periodic pulse generation module 30 includes a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the reference clock, and the second input terminal is connected to the output of the measurement period generation module 20 . terminal is connected, and its output terminal is connected to the cross-clock domain circuit 40 for intermittently generating a first periodic pulse signal that is the same as the clock domain of the reference clock, and the generated signal is passed through its output terminal. The first periodic pulse signal is sent to the cross-clock domain circuit 40 , wherein the period of the first periodic pulse signal is the measurement period.

The cross-clock domain circuit 40 includes a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the output terminal of the periodic pulse generation module 30 , and the second input terminal is connected to the clock The output terminal of the selection module 50 is connected to a clock signal selected by the clock selection module 50 from a plurality of clock signals and used as the clock to be measured through the second input terminal, and its output terminal is connected to The input end of the counter 60 is connected to perform cross-clock domain processing on the first periodic pulse signal according to the clock domain of the clock to be measured, that is, to adapt the first periodic pulse signal to the clock domain of the clock to be measured. A second periodic pulse signal with the same clock domain of the clock to be measured, wherein the period of the second periodic pulse signal is the measurement period.

The clock selection module 50 includes an input terminal, a first output terminal and a second output terminal. The input terminal can receive multiple clock signals. The first output terminal and the second input of the cross-clock domain circuit 40 terminal is connected, the second output terminal is connected to an input terminal of the counter 60 for selecting a clock signal from the plurality of clock signals connected to its input terminal as the clock to be measured, and The selected clock to be measured is sent to the cross-clock domain circuit 40 and the counter 60 respectively.

The counter 60 includes a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the output terminal of the cross-clock domain circuit 40 , and the second input terminal is connected to the clock selection module 50 is connected to the second output terminal, and its output terminal is connected to the comparison memory 70 for using the second periodic pulse signal to perform multiple sampling and counting of the clock to be measured, and sending the counting results to the The comparison memory 70 performs storage.

The comparison memory 70 includes an input terminal and an output terminal. The input terminal is connected to the output terminal of the counter 60 and the output terminal is connected to the input terminal of the decision module 80 for receiving the counter. 60 After counting the counting results in each measurement cycle, adjust the maximum value and/or minimum value, and store the adjusted maximum value and minimum value. Specifically, after receiving the counting results corresponding to each measurement cycle, the comparison memory 70 may first compare the maximum value and/or the minimum value of the stored counting results, and if it is greater than the stored count If the maximum value of the result is larger, the counting result will be used as the new maximum value of the counting result. If it is smaller than the minimum value of the stored counting result, the counting result will be used as the new minimum value of the counting result, and then the counting result will be used as the new minimum value of the counting result. The new maximum value and minimum value are stored and sent to the decision module 80.

The decision module 80 includes an input terminal, a first output terminal and a second output terminal. The input terminal is connected to the output terminal of the comparison memory 70 . The first output terminal is connected to the measurement period adaptive adjustment module. 90 is connected to the input terminal, and the second output terminal is connected to the input terminal of the counting measurement module 100 to compare the difference between the new maximum value and the minimum value of the counting result. If the difference value is not Within the preset range, a start instruction is sent to the measurement period adaptive adjustment module 90. If the difference value is within the preset range, the new maximum value of the counting result of this comparison is directly and the minimum value is sent to the count measurement module 100 .

The measurement period adaptive adjustment module 90 includes an input terminal and an output terminal. The input terminal is connected to the first output terminal of the decision module 80 , and the output terminal is connected to the second output terminal of the measurement period generation module 20 . The input terminal is connected for receiving the start instruction sent by the decision module 80, that is, when the difference between the new maximum value and the minimum value of the counting result is not within the preset range, the predetermined The adaptive algorithm is assumed to form an adjustment period, and the adjustment period is sent to the measurement period generation module 20, so that after receiving the adjustment period, the measurement period generation module 20 uses the adjustment period as the The period of the reference clock is used to form a new measurement period (that is, the adjusted measurement period) again, and based on the adjusted measurement period, the sampling and counting of the clock to be measured is performed again.

The counting measurement module 100 includes an input terminal and an output terminal. The input terminal is connected to the second output terminal of the decision module 80 for comparing the new counting result in the decision module 80 . When the difference between the maximum value and the minimum value is within the preset range, the frequency of the clock to be measured is calculated and output based on the maximum value or minimum value.

The preset range of the difference value may specifically be: 1 to 2, and is preferably 1.

It should be noted that in some embodiments of the present invention, the frequency measurement circuit shown in Figure 1 can be used as a separate frequency measurement test circuit, so that the frequency measurement circuit can be started under the control of an external host computer. ; In other embodiments of the present invention, the frequency measurement circuit shown in Figure 1 can also be used as a sub-circuit in a circuit that needs to measure frequency. For example, the frequency measurement circuit shown in Figure 1 can be The frequency measurement circuit shown in FIG. 1 is connected to a SOC integrated chip including multiple clock signals to measure a certain clock signal in the SOC integrated chip. That is, the frequency measurement circuit shown in FIG. 1 is used by the present invention. There are no restrictions on specific use, as long as frequency measurement is achieved.

Obviously, due to the frequency measurement circuit provided in the embodiment of the present invention, a measurement period adaptive adjustment module is connected to an input end of the measurement period generation module, so that the frequency measurement circuit output by the measurement period adaptive adjustment module is used. Adjust the adjustment period of the measurement period to obtain the adjusted measurement period. Then, based on the continuously adjusted measurement period, count multiple rising edges or falling edges of the clock to be measured, and the difference between the maximum value and the minimum value of the counting result is in the preset value. When it is within the set range, the cycle counting is stopped, and the frequency of the clock under test is finally obtained.

Since the frequency measurement circuit provided in the present invention does not limit the frequency range to be measured, it can not only measure the high-speed clock in the high-speed SOC integrated chip, but also can measure any other clocks with different frequencies. Therefore, the present invention The frequency measurement circuit provided in the embodiment can achieve at least unexpected technical effects: greater adaptability, adaptive learning and adjustment of the measurement period, compatibility with multiple measurement ranges, and improved measurement accuracy.

Moreover, since the frequency measurement circuit provided in the embodiment of the present invention offloads a large amount of calculations to the software level for execution, it can also effectively reduce the complexity of the chip, save frequency calculation time and cost, and effectively reduce the power consumption of the chip. and reduce the complexity of digital logic.

Based on the frequency measurement circuit shown in Figure 1, the embodiment of the present invention also provides a frequency measurement method, as shown in Figure 2. Figure 2 is a flow chart of a frequency measurement method provided in the embodiment of the present invention. Schematic diagram.

Referring to Figure 2, the frequency measurement method may specifically include the following steps:

Step S201: Determine the period of the reference clock to form a measurement period.

Step S202: Based on the measurement period and parameter clock, form a first periodic pulse signal that is the same as the clock domain of the reference clock.

Step S203: Determine the clock to be tested, and perform cross-clock domain processing on the first periodic pulse based on the clock to be tested, to obtain a second periodic pulse signal that is the same as the clock domain of the clock to be tested.

Step S204: Use the second periodic pulse signal to sample and count the clock to be measured to obtain this counting result.

Step S205: Compare the current counting result with the maximum value and/or minimum value of the pre-stored counting result, and determine the updated maximum value and minimum value of the counting result based on the comparison result.

Step S206: Compare whether the updated maximum value and minimum value of the counting result are within a preset range.

Step S207, if the difference between the maximum value and the minimum value is not within the preset range, use an adaptive learning algorithm to form an adjustment period, and return to the step of forming a measurement period to form a measurement period based on the adjustment period. Adjusted measurement period.

Step S208: If the difference between the updated maximum value and the minimum value of the counting result is within the preset range, then based on the updated maximum value or minimum value of the counting result, obtain the value of the clock to be measured. frequency.

Wherein, the periods of the first periodic pulse signal and the second periodic pulse signal are the same and both are the measurement period.

In the above step S201, after receiving the frequency test start instruction, the measurement period generation module 20 in FIG. 1 first forms an initial value of a measurement period based on the period of the reference clock received at the same time, and then, based on the measurement The initial value of the period executes steps S202 to S208 in sequence to obtain the initial values of the maximum value and minimum value of the counting result. However, since there is only one counting result at this time, the corresponding maximum value and minimum value are equal, that is, the counting result The difference between the maximum value and the minimum value is 0, which is not within the preset range. Therefore, the measurement period adaptive adjustment module 90 will adjust the measurement cycle according to the preset adaptive learning algorithm (such as zero-forcing algorithm, steepest descent algorithm, LMS algorithm or RLS algorithm) to obtain an adjustment period, and the measurement period generation module 20 uses the adjustment period as the period of the new reference clock to execute the steps S202 to S208 again, and so on, until based on a certain When the difference between the maximum value and the minimum value of the updated counting result obtained by the adjusted measurement period is 1, the output of the adjusted measurement period is stopped, that is, iterative counting is stopped.

In the above step S202, the periodic pulse production module 30 forms a pulse in each measurement cycle based on the accessed reference clock and each received measurement cycle (the initial value of the measurement cycle and the subsequent adjusted measurement cycle). A first periodic pulse signal whose clock domain is the same as that of the reference clock and whose period is the measurement period.

In the above step S203, in each measurement cycle, the cross-clock domain circuit 40 performs cross-clock domain processing on the first periodic pulse signal according to the received clock domain of the clock to be measured, so as to obtain the same result as the clock domain to be measured. The clock domain of the clock under test is the same as the second periodic pulse signal, wherein the clock domains of the clock to be measured and the reference clock are different.

In the above-mentioned steps S204 to S205, in each measurement period, the counter 60 uses the clock domain of the second periodic pulse signal formed each time to be the same as the clock domain of the clock to be measured to avoid sub-sampling. The principle of the steady-state problem is to count the rising edges or falling edges of the clock under test within the measurement period, and then obtain a counting result, and compare it with the maximum and minimum values based on the counting results obtained from at least two previous measurements. (Pre-stored in the comparison memory 70), if the counting result is greater than the maximum value of the pre-stored counting result, then the counting result is used as the updated maximum value of the counting result; if the If the counting result is smaller than the minimum value of the pre-stored counting result, the current counting result is used as the updated minimum value of the counting result, that is, the updated maximum value and minimum value of the counting result are determined.

In the above steps S206 to S208, in each measurement cycle, the decision module 80 will receive a maximum value and a minimum value of the counting result, and compare the maximum value and the minimum value. If If the difference between the maximum value and the minimum value is 1, it means that the adjusted measurement period has reached the target measurement period, and the frequency calculated based on the target measurement period is the most accurate, then the iterative counting can be stopped and the counting can be directly performed. The measurement module 100 only needs to output the frequency of the clock to be measured. If the difference between the maximum value and the minimum value is greater than 2, it means that the adjusted measurement period has not reached the target measurement period, and the calculated value based on this measurement period There is an error in the counting result, that is, there is an error between the calculated frequency of the clock to be measured and the frequency of the clock to be measured. Therefore, it is necessary to readjust the measurement period and re-execute the above steps S201 to S208.

To sum up, in the frequency measurement circuit provided by the present invention, a measurement period adaptive adjustment module is connected to an input end of the measurement period generation module, so that the user outputted by the measurement period adaptive adjustment module can be In order to adjust the adjustment period of the measurement period, the adjusted measurement period is obtained, and then based on the continuously adjusted measurement period, the clock under test is counted for multiple rising edges or falling edges, and the difference between the maximum value and the minimum value of the counting result is When the frequency is within the preset range, the cycle counting is stopped, and the frequency of the clock under test is finally obtained.

Since the frequency measurement circuit provided in the present invention does not limit the frequency range to be measured, it can not only measure the high-speed clock in the high-speed SOC integrated chip, but also can measure any other clocks with different frequencies. Therefore, the present invention The frequency measurement circuit provided is more adaptable, can adaptively learn to adjust the measurement period, is compatible with a variety of measurement ranges, and improves measurement accuracy.

Moreover, when the present invention measures the frequency of the clock to be measured, the maximum or minimum value of the counting result used to determine the frequency of the clock to be measured will not be updated as the measurement cycle is adjusted, until the counting result reaches When the difference between the maximum value and the minimum value is 1, it means that the adjusted measurement period reaches the target measurement period, and the frequency calculated based on the target measurement period is the most accurate.

Furthermore, since the present invention places a large number of operations on the software level of the measurement cycle adaptive adjustment module and the comparison memory, the main design idea of the frequency measurement circuit provided by the present invention is the combination of software and hardware, and based on this design The frequency measurement circuit of Idea can effectively reduce the complexity of IC circuit design, effectively reduce chip debugging time, save time and cost, and accelerate the commercialization and update efficiency of chips as soon as possible.

An embodiment of the present invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory complete communication with each other through the communication bus,

Memory, used to store computer programs;

The processor is configured to implement a frequency measurement method provided by an embodiment of the present invention when executing a program stored in the memory.

In addition, other implementation methods of the method for adding auxiliary graphics implemented by the processor executing the program stored in the memory are the same as the implementation methods mentioned in the foregoing method embodiments, and will not be described again here.

The communication bus mentioned in the above control terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into address bus, data bus, control bus, etc. For ease of presentation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the above-mentioned electronic devices and other devices.

The memory may include random access memory (Random Access Memory, RAM) or non-volatile memory (Non-Volatile Memory, NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far away from the aforementioned processor.

The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (Network Processor, NP), etc.; it can also be a digital signal processor (Digital SignalProcessing, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

In yet another embodiment provided by the present invention, a computer-readable storage medium is also provided. The computer-readable storage medium stores instructions, which when run on a computer, cause the computer to execute any one of the above embodiments. A frequency measurement method.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website site, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated. The available media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), etc.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations are mutually exclusive. any such actual relationship or sequence exists between them. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the stated element.

Each embodiment in this specification is described in a related manner. The same and similar parts between the various embodiments can be referred to each other. Each embodiment focuses on its differences from other embodiments. In particular, for the apparatus, electronic equipment and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the descriptions are relatively simple. For relevant details, please refer to the partial description of the method embodiments.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (9)

1. A frequency measurement circuit, comprising:

the measuring period generating module is connected with the measuring period self-adaptive adjusting module and is used for generating and outputting an adjusted measuring period based on the adjusting period generated by the measuring period self-adaptive adjusting module after generating and outputting an initial value of the measuring period according to the period of the reference clock;

the periodic pulse generation module is connected with the reference clock and connected with the measurement period generation module and the clock domain crossing circuit, and is used for generating at intervals and outputting a first periodic pulse signal which is the same as the clock domain of the reference clock to the clock domain crossing circuit, wherein the period of the first periodic pulse signal is the measurement period;

the clock domain crossing circuit is connected with a clock to be measured and connected with the counter, and is used for adapting the first periodic pulse signal to a second periodic pulse signal which is the same as the clock domain of the clock to be measured, wherein the period of the second periodic pulse signal is the measurement period;

the counter is connected with the clock to be detected and connected with the comparison memory, and is used for sampling and counting the clock to be detected for a plurality of times by using the second periodic pulse signal, and sending the counting result to the comparison memory for storage;

the comparison memory is connected with the judging module and is used for comparing the counting result with the stored maximum value and/or minimum value of the counting result after receiving the counting result, taking the counting result as a new maximum value of the counting result if the counting result is larger than the stored maximum value of the counting result, taking the counting result as a new minimum value of the counting result if the counting result is smaller than the stored minimum value of the counting result, and then storing and sending the new maximum value and the new minimum value of the counting result to the judging module;

the judging module is connected with the measurement period self-adaptive adjustment module and is used for performing difference comparison on the new maximum value and the new minimum value of the counting result, and if the difference value is not in a preset range, a starting instruction is sent to the measurement period self-adaptive adjustment module;

the measurement period self-adaptive adjustment module is used for forming an adjustment period according to a preset self-adaptive algorithm after receiving the starting instruction, and sending the adjustment period to the measurement period generation module; and

and the counting measurement module is connected with the judgment module and is used for calculating and outputting the frequency of the clock to be measured when the judgment module compares that the difference value of the new maximum value and the new minimum value of the counting result is in the preset range.

2. The frequency measurement circuit of claim 1, wherein the frequency measurement circuit further comprises: and the measurement starting module is connected with the measurement period generating module and is used for transmitting the parameter information of the reference clock to the measurement period generating module after receiving the frequency measurement starting instruction transmitted by the upper computer, wherein the parameter information comprises a period.

3. The frequency measurement circuit of claim 1, wherein the frequency measurement circuit is applied to an SOC integrated chip that includes a plurality of clock signals.

4. The frequency measurement circuit of claim 3, wherein the frequency measurement circuit further comprises: and the clock selection module is connected with the clock signals and connected with the clock domain crossing circuit and the counter, and is used for selecting a clock signal from the clock signals as the clock to be tested and sending the selected clock to be tested to the clock domain crossing circuit and the counter.

5. An SOC integrated chip comprising the frequency measurement circuit of any of claims 1 to 4.

6. A method of frequency measurement, comprising:

determining the period of a reference clock to form a measurement period;

forming a first periodic pulse signal which is the same as the clock domain of the reference clock based on the measurement period and the parameter clock;

determining a clock to be detected, and performing cross-clock domain processing on the first periodic pulse based on the clock to be detected to obtain a second periodic pulse signal which is the same as the clock domain of the clock to be detected;

sampling and counting the clock to be tested by using the second periodic pulse signal to obtain a current counting result;

comparing the current counting result with the maximum value and/or the minimum value of the pre-stored counting result, and determining the updated maximum value and minimum value of the counting result according to the comparison result;

comparing the updated maximum value and the updated minimum value of the counting result, if the difference value of the maximum value and the minimum value is not in the preset range, forming an adjustment period by using an adaptive learning algorithm, and returning to the step of executing the measurement period to form an adjusted measurement period based on the adjustment period;

and if the difference value of the updated maximum value and the updated minimum value of the counting result is in a preset range, obtaining the frequency of the clock to be tested based on the updated maximum value or the updated minimum value of the counting result.

7. The method of measuring frequency according to claim 6, wherein the periods of the first periodic pulse signal and the second periodic pulse signal are the measurement periods.

8. The frequency measurement method of claim 6, wherein the step of determining updated maximum and minimum values of the count result based on the comparison result comprises:

if the current counting result is larger than the maximum value of the pre-stored counting results, taking the current counting result as the updated maximum value of the counting results;

and if the current counting result is smaller than the minimum value of the pre-stored counting results, taking the current counting result as the updated minimum value of the counting result.

9. The method of claim 8, wherein the predetermined range of the difference value is: 1-2.