CN116107187B

CN116107187B - Time interval measurement method, chip and device

Info

Publication number: CN116107187B
Application number: CN202211568506.3A
Authority: CN
Inventors: 许钟子珩; 胡金春
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2022-12-08
Filing date: 2022-12-08
Publication date: 2024-05-31
Anticipated expiration: 2042-12-08
Also published as: CN116107187A

Abstract

The application relates to a time interval measurement method, a chip and a device. The method comprises the following steps: and obtaining a measurement synchronous clock, performing frequency multiplication processing on the measurement synchronous clock to obtain a measurement reference clock and an online calibration signal, and performing n-time latching operation on the delayed clock signal according to the online calibration signal to obtain a plurality of fitting straight lines. And then counting the rising edge of the level signal of the measurement reference clock between the reception of the measurement start signal and the reception of the measurement end signal to obtain a measurement integer part N, carrying out latching operation on the delay clock signal according to the measurement end signal to obtain a delay clock signal corresponding to the end time, determining a measurement decimal part M according to a plurality of fitting straight lines and the delay clock signal corresponding to the end time, and determining a time interval to be measured according to the measurement integer part N and the measurement decimal part M. By adopting the method, the measurement accuracy can be improved.

Description

Time interval measurement method, chip and device

Technical Field

The present application relates to the field of signal processing technologies, and in particular, to a method, a chip, and an apparatus for measuring a time interval.

Background

With the development of the signal processing technology field of the time-to-digital converter (Time to Digital Converter, TDC), various TDC implementation methods have been presented, wherein the simplest TDC relies on clock counting to implement time interval measurement, but is influenced by factors such as chip technology, and the time resolution of the method is low, and in order to implement higher resolution time interval measurement, a TDC time measurement method based on a delay line has been presented.

In the conventional delay line TDC technology, the time measurement accuracy is determined by means of the delay time of a known delay unit, but in the time measurement process, the delay time of the delay unit is not always constant and is affected by environmental factors such as temperature, the delay time can change to different degrees, and the time interval obtained by measurement is affected by environmental factors to change, so that the measurement accuracy is reduced.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a time interval measurement method, a chip, and a device that can improve measurement accuracy.

In a first aspect, the present application provides a time interval measurement method. The method comprises the following steps:

acquiring a measurement synchronous clock, and performing frequency multiplication processing on the measurement synchronous clock to respectively acquire a measurement reference clock and an online calibration signal;

According to the online calibration signal, carrying out N latching operations on a delay clock signal, and obtaining a plurality of fitting straight lines according to the delay clock signal corresponding to the N latching operations, wherein the delay clock signal is the measurement reference clock delayed by a plurality of delay lines, a time interval to be measured comprises a measurement integer part N and a measurement decimal part M, and the fitting straight lines represent the relation between delay line channel numbers corresponding to the delay lines and the measurement decimal part M, wherein N is a positive integer;

Counting the rising edges of the level signals of the measurement reference clock between the reception of the measurement start signal and the reception of the measurement end signal to obtain the measurement integer part N;

According to the measurement termination signal, carrying out latching operation on the delay clock signal to obtain the delay clock signal corresponding to each delay line at the termination moment;

Determining the measurement decimal part M according to a plurality of fitting straight lines and the delay clock signals corresponding to the delay lines at the termination time;

and determining the time interval to be measured according to the measurement integer part N and the measurement decimal part M.

In one embodiment, the performing n latching operations on the delayed clock signal according to the online calibration signal, and obtaining a plurality of fitting straight lines according to the delayed clock signal corresponding to the n latching operations includes:

When the level signal of the online calibration signal is a rising edge, carrying out one-time latch operation on the delayed clock signal to obtain the delayed clock signal corresponding to the latch operation;

and when the number of the latch operations is n, determining a plurality of fitting straight lines according to the delay clock signals corresponding to the n latch operations.

In one embodiment, the determining a plurality of fitting straight lines according to the delay clock signals corresponding to the n latch operations includes:

determining level change point information according to the delay clock signal corresponding to the latch operation for any latch operation, wherein the level change point information comprises a target delay line channel number i and latch time information corresponding to the latch operation, the level change point information is used for representing a level change point, and in the latch operation, the delay clock signal corresponding to the target delay line channel number i is different from the level of the delay clock signal corresponding to the delay line channel number i-1, and the i is an integer greater than 1;

determining a plurality of straight lines to be fitted according to the delay clock signals corresponding to the delay lines;

and fitting to obtain a plurality of fitting straight lines according to the level change point information and the plurality of to-be-fitted straight lines.

In one embodiment, the method further comprises:

Determining a period corresponding relation according to the period of the measurement reference clock and the period of the online calibration signal;

Determining the period information of the online calibration signal corresponding to the latch operation according to any latch operation;

And determining the latching time information corresponding to the latching operation according to the period corresponding relation and the period information of the online calibration signal corresponding to the latching operation.

In one embodiment, the determining a plurality of lines to be fitted according to the delay clock signals corresponding to the delay lines includes:

And carrying out connection processing on rising edges of the delay clock signals corresponding to the first delay lines, and carrying out connection processing on falling edges of the delay clock signals corresponding to the second delay lines to obtain a plurality of lines to be fitted, wherein the first delay lines are adjacent to each other in pairs, and the second delay lines are adjacent to each other in pairs.

In one embodiment, the level change point information further includes a change trend, the change trend includes a first trend or a second trend, the first trend represents that the level is changed from high to low, the second trend represents that the level is changed from low to high, and fitting is performed according to the level change point information and a plurality of to-be-fitted straight lines to obtain a plurality of fitted straight lines, including:

For any straight line to be fitted, determining a target level change point corresponding to the straight line to be fitted according to the level change point information, wherein the distance between the target level change point and the straight line to be fitted is smaller than a preset distance, and the change trend corresponding to each target level change point is the same;

Fitting is carried out according to the target level change points, and a fitting straight line is obtained.

In one embodiment, the determining the measurement fractional part M according to the plurality of fitted straight lines and the delay clock signals corresponding to the delay lines at the termination time includes:

Determining termination level change point information of the termination time according to the delay clock signals corresponding to the delay lines at the termination time, wherein the termination level change point information comprises a termination level change trend and a termination delay line channel number j, the termination level change trend comprises a third trend or a fourth trend, the third trend represents that the level is changed from high to low, the fourth trend represents that the level is changed from low to high, the delay clock signals corresponding to the termination delay line channel number j are different from the level of the delay clock signals corresponding to the delay line channel number j-1, and j is an integer greater than 1;

Determining a target fitting straight line corresponding to the termination level change point information from a plurality of fitting straight lines according to the termination level change trend and the termination delay line channel number j aiming at any termination level change point information;

Determining a target measurement decimal part according to the termination level change point information and the target fitting straight line;

and carrying out average value processing on the target measurement decimal part corresponding to each termination level change point information to obtain the measurement decimal part M.

In one embodiment, the counting the rising edge of the level signal of the measurement reference clock between the reception of the measurement start signal and the reception of the measurement end signal to obtain the measurement integer part N includes:

after receiving a measurement starting signal, counting the rising edge of the level signal of the measurement reference clock when the level signal of the measurement synchronous clock is the rising edge;

and under the condition that a measurement termination signal is received, stopping counting the rising edge of the level signal of the measurement reference clock to obtain a measurement integer part N, wherein N is a positive integer.

In a second aspect, the application also provides a time interval measurement chip. The chip comprises: the phase-locked loop, the whole period counting unit, the delay line output state latch and the data processing unit; wherein,

The phase-locked loop is used for acquiring a measurement synchronous clock, performing frequency multiplication processing on the measurement synchronous clock to respectively acquire a measurement reference clock and an online calibration signal, respectively transmitting the measurement reference clock to the whole period counting unit and the delay line, and transmitting the online calibration signal to the delay line output state latch;

The delay line is used for delaying the online calibration signal to obtain a delayed clock signal;

The delay line output state latch is configured to perform n latching operations on the delay clock signal according to the online calibration signal, obtain the delay clock signal corresponding to the n latching operations, and send the delay clock signal corresponding to the n latching operations to the data processing unit;

The data processing unit is configured to receive the delay clock signals corresponding to the N times of latching operations sent by the delay line output state latch, determine a plurality of fitting straight lines according to the delay clock signals corresponding to the N times of latching operations, where a time interval to be measured includes a measurement integer part N and a measurement fractional part M, and the fitting straight lines represent a relationship between a delay line channel number corresponding to the delay line and the measurement fractional part M, where N is a positive integer;

The whole period counting unit is used for counting the rising edge of the level signal of the measurement reference clock between the reception of the measurement starting signal and the reception of the measurement ending signal to obtain the measurement integer part N, and sending the measurement integer part N to the data processing unit;

The delay line output state latch is further configured to latch the delay clock signal according to the measurement termination signal, obtain the delay clock signal corresponding to each delay line at a termination time, and send the delay clock signal corresponding to each delay line at the termination time to the data processing unit;

The data processing unit is further configured to receive the delay clock signal and the measurement integer part N corresponding to each delay line at the termination time, determine the measurement fractional part M according to the plurality of fitting straight lines and the delay clock signal corresponding to each delay line at the termination time, and determine the time interval to be measured according to the measurement integer part N and the measurement fractional part M.

In a third aspect, the application further provides a time interval measurement device. The device comprises:

the acquisition module is used for acquiring a measurement synchronous clock, performing frequency multiplication processing on the measurement synchronous clock, and respectively acquiring a measurement reference clock and an online calibration signal;

The first latch module is used for carrying out N latching operations on a delay clock signal according to the online calibration signal, obtaining a plurality of fitting straight lines according to the delay clock signal corresponding to the N latching operations, wherein the delay clock signal is the measurement reference clock delayed by a plurality of delay lines, the time interval to be measured comprises a measurement integer part N and a measurement decimal part M, and the fitting straight lines represent the relation between delay line channel numbers corresponding to the delay lines and the measurement decimal part M, wherein N is a positive integer;

the counting module is used for counting the rising edge of the level signal of the measurement reference clock between the reception of the measurement start signal and the reception of the measurement end signal to obtain the measurement integer part N;

the second latch module is used for latching the delay clock signals according to the measurement termination signals to obtain the delay clock signals corresponding to the delay lines at the termination time;

A first determining module, configured to determine the measurement fractional part M according to a plurality of fitted straight lines and the delay clock signals corresponding to the delay lines at the termination time;

And the second determining module is used for determining the time interval to be measured according to the measurement integer part N and the measurement decimal part M.

In one embodiment, the first latch module is further configured to:

In one embodiment, the apparatus further comprises:

the third determining module is used for determining a period corresponding relation according to the period of the measurement reference clock and the period of the online calibration signal;

a fourth determining module, configured to determine, for any one of the latch operations, period information of the online calibration signal corresponding to the latch operation;

And a fifth determining module, configured to determine the latch time information corresponding to the latch operation according to the period correspondence and period information of the online calibration signal corresponding to the latch operation.

In one embodiment, the first latch module is further configured to:

In one embodiment, the level change point information further includes a change trend, the change trend includes a first trend or a second trend, the first trend represents that the level is changed from high to low, the second trend represents that the level is changed from low to high, and the first latch module is further configured to:

In one embodiment, the first determining module is further configured to:

In one embodiment, the counting module is further configured to:

According to the time interval measuring method, the chip and the device, the measuring synchronous clock is obtained, frequency multiplication processing is carried out on the measuring synchronous clock, and the measuring reference clock and the on-line calibration signal are respectively obtained. And carrying out N latching operations on the delay clock signals according to the online calibration signals to obtain a plurality of fitting straight lines, wherein the delay clock signals are the measurement reference clocks delayed by the delay lines, the time interval to be measured comprises a measurement integer part N and a measurement decimal part M, and the fitting straight lines represent the relation between the delay line channel numbers and the measurement decimal part M, wherein N is a positive integer. And counting the rising edge of the level signal of the measurement reference clock between the reception of the measurement start signal and the reception of the measurement end signal to obtain a measurement integer part N, and carrying out latching operation on the delay clock signal according to the measurement end signal to obtain the delay clock signal corresponding to the end time. And then determining a measurement decimal part M according to the delay clock signals corresponding to the fitting straight lines and the termination time, and determining a time interval to be measured according to the measurement integer part N and the measurement decimal part M. Based on the time interval measuring method, the chip and the device, the time interval to be measured is determined by measuring how many periods of the measuring reference clock exist in the time interval to be measured, wherein the number of the measuring reference clock periods corresponding to the time interval to be measured comprises a measuring integer part and a measuring decimal part. In the process of determining the measurement decimal part, the online calibration signal and the measurement reference clock are obtained by frequency multiplication of the measurement synchronous clock, wherein the three signals are determined, the period of the online calibration signal is not influenced by environmental factors such as temperature and the like to change, then n latching operations are carried out on the delay clock signal according to the online calibration signal, and the obtained multiple fitting straight lines can accurately represent the relation between the delay line channel number and the measurement decimal part M and cannot be influenced by the environmental factors. By latching the delay clock signal at the termination time, the measurement decimal part M is determined according to the delay clock signal corresponding to the termination time and the fitting straight line, and the measurement decimal part obtained according to the fitting straight line is not influenced by environment because the functional relation represented by the fitting straight line is not influenced by environment, so that the influence of environmental factors on the measurement accuracy of the time interval is eliminated, and the measurement accuracy is improved.

Drawings

FIG. 1 is a flow chart of a method for measuring time intervals in one embodiment;

FIG. 2 is a schematic diagram of a delay clock signal corresponding to each delay line in one embodiment;

FIG. 3 is a schematic diagram of signals during measurement of a time interval to be measured in one embodiment;

FIG. 4 is a flowchart of another embodiment of a method for measuring time intervals;

FIG. 5 is a flowchart of another embodiment of a method for measuring time intervals;

FIG. 6 is a flowchart of a time interval measurement method according to another embodiment;

FIG. 7 is a flowchart of a time interval measurement method according to another embodiment;

FIG. 8 is a flowchart of a time interval measurement method according to another embodiment;

FIG. 9 is a flowchart of a time interval measurement method according to another embodiment;

FIG. 10 is a schematic diagram of a time interval measurement chip according to an embodiment;

FIG. 11 is a diagram of a multiphase clock TDC structure based on a phase locked loop in one embodiment;

FIG. 12 is a schematic diagram of a basic structure of a TDC based on a delay line in one embodiment;

FIG. 13 is a schematic diagram illustrating a multi-edge sampling principle performed by Wave Union TDC in one embodiment;

fig. 14 is a block diagram of a time interval measurement apparatus in one embodiment.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.

In one embodiment, as shown in fig. 1, a time interval measurement method is provided, where this embodiment is applied to a terminal to illustrate the method, it is understood that the method may also be applied to a server, and may also be applied to a system including a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the steps of:

Step 102, obtaining a measurement synchronous clock, and performing frequency multiplication processing on the measurement synchronous clock to respectively obtain a measurement reference clock and an online calibration signal.

In the embodiment of the application, the measurement synchronous clock is a square wave signal with a constant period, after the measurement synchronous clock is obtained, the measurement reference clock and the online calibration signal can be respectively obtained by carrying out different frequency multiplication processing on the measurement synchronous clock, the frequency of the measurement reference clock and the frequency of the online calibration signal are respectively a plurality of times of the frequency of the measurement synchronous clock, wherein the times corresponding to the measurement reference clock are different from the times corresponding to the online calibration signal, and when the level signal of the measurement synchronous clock is a rising edge, the level signal of the measurement reference clock and the online calibration signal are also rising edges.

Taking a measurement synchronous clock with the frequency of 25Hz as an example, the measurement synchronous clock is multiplied by frequency respectively to obtain a measurement reference clock with the frequency of 200Hz and an online calibration signal with the frequency of 2000 Hz.

Step 104, performing N latching operations on the delayed clock signal according to the online calibration signal, and obtaining a plurality of fitting straight lines according to the delayed clock signal corresponding to the N latching operations, wherein the delayed clock signal is a measurement reference clock delayed by a plurality of delay lines, the time interval to be measured comprises a measurement integer part N and a measurement decimal part M, and the fitting straight lines represent the relation between the delay line channel number corresponding to the delay lines and the measurement decimal part M, wherein N is a positive integer.

In the embodiment of the present application, the time interval to be measured is determined by measuring the period of several measurement reference clocks in the time interval to be measured, where the time interval to be measured includes a measurement integer part N and a measurement fractional part M, and by taking the example that the time interval to be measured includes 5.7 measurement reference clock periods T, the measurement integer part n=5, and the measurement fractional part m=0.7.

In the embodiment of the present application, a reference clock is measured and input into a series of delay lines, delay of the delay lines is performed to obtain delay clock signals, n latching operations are performed on the delay clock signals according to on-line calibration signals, delay clock signals corresponding to the n latching operations are obtained, and finally a plurality of fitting straight lines are obtained according to the delay clock signals corresponding to the n latching operations, where the delay clock signals corresponding to the latching operations refer to the level of the delay clock signals on each delay line at the time corresponding to the latching operation, for example, as shown in fig. 2, by taking the second latching operation n=2 as an example, the delay clock signals on each delay line are respectively in a high level, a low level, and a low level … … according to the sequence from top to bottom of the delay line.

Referring to fig. 2, there are five dash-dot lines, where the leftmost dash-dot line coincides with the solid line, and the five dash-dot lines indicate that the delayed clock signal is subjected to 5 latch operations, where the time of performing the latch operation may be determined according to an on-line calibration signal, for example: the latch operation may be performed once at the rising edge of the online calibration signal each time, or performed once at the falling edge of the online calibration signal each time, and the signal on each delay line at this time is latched, so as to obtain the delay clock signal on each delay line corresponding to the latch operation, where the time of performing the latch operation may be represented by the period of the online calibration signal. The measurement reference clock and the on-line calibration signal are obtained by frequency multiplication of the measurement synchronous clock, and the period of the on-line calibration signal and the period of the measurement reference clock have a certain multiple relationship, so that the period of the on-line calibration signal can be represented by the period of the measurement reference clock, and further, the period of the measurement reference clock corresponding to the latching operation can be obtained.

For example, still taking the above example as an example, the frequency of the on-line calibration signal is 2000Hz, the frequency of the measurement reference clock is 200Hz, the period of the measurement reference clock is T, and the period of the on-line calibration signal is 0.1T. At this time, when the line calibration signal is a rising edge, the latch operation is performed, and when n=1, the delay clock signal of each delay line corresponding to 0T is obtained, and when n=2, the delay clock signal … … n=5 of each delay line corresponding to 0.1T is obtained, and when the delay clock signal of each delay line corresponding to 0.4T is obtained.

In the embodiment of the application, a two-dimensional coordinate system can be established by taking the decimal part of the measurement reference clock period corresponding to the latching moment as an x axis and taking the delay line channel number as a y axis. According to the delay clock signals obtained by n latching operations, fitting to obtain a plurality of fitting straight lines which can represent the functional relation between the delay line channel number and the measurement reference clock period corresponding to the latching time, wherein the measurement reference clock period corresponding to the latching time selects decimal, and the fitting straight lines can directly represent the relation between the delay line channel number and the measurement decimal part M.

In another example, the period of the on-line calibration signal is greater than the period of the measurement reference clock, taking the period of the measurement reference clock as T, and taking the period of the on-line calibration signal as 1.1T as an example, the period of the measurement reference clock actually corresponding to the 5 latching operations is respectively 0T, 1.1T, 2.2T, 3.3T, and 4.4T, at this time, the decimal part of the data is taken as the period of the measurement reference clock corresponding to the latching operation, and the period of the measurement reference clock corresponding to the latching operation is respectively 0T, 0.1T, 0.2T, 0.3T, and 0.4T.

Step 106, counting the rising edge of the level signal of the measurement reference clock between the reception of the measurement start signal and the reception of the measurement end signal, to obtain the measurement integer part N.

In the embodiment of the application, when only the measurement start signal is received and measurement is not performed, the counting of the rising edge of the level signal of the measurement reference clock is started until the level signal of the measurement synchronous clock is the rising edge, and after the measurement end signal is received, the counting is stopped to obtain the measurement integer part N.

Illustratively, referring to fig. 3, between receiving a measurement start signal and receiving a measurement end signal, there are 2 measurement reference clock level signal rising edges, and the measurement integer part n=2.

And step 108, latching the delayed clock signals according to the measurement termination signals to obtain the delayed clock signals corresponding to the delay lines at the termination time.

In the embodiment of the application, when the measurement termination signal is received, the delay clock signal is latched once, so that the delay clock signal on each delay line corresponding to the termination time is obtained.

Step 110, determining the measurement fraction part M according to the plurality of fitting straight lines and the delay clock signals corresponding to the delay lines at the termination time.

In the embodiment of the present application, as can be seen from the above description, the fitted straight line may directly represent the relationship between the delay line channel number and the measurement fractional part M, and the measurement fractional part M may be determined according to a plurality of fitted straight lines and delay clock signals corresponding to the termination time (i.e., level signals corresponding to the delay line channel numbers).

Step 112, determining the time interval to be measured according to the measured integer part N and the measured decimal part M.

In the embodiment of the application, the measurement integer part N can be multiplied by the measurement reference clock period, the measurement decimal part M can be multiplied by the measurement reference clock period, and the two obtained product results are added to obtain the time interval to be measured.

In the time interval measuring method, the time interval to be measured is determined by measuring how many periods of the measuring reference clock are in the time interval to be measured, wherein the number of the measuring reference clock periods corresponding to the time interval to be measured comprises a measuring integer part and a measuring decimal part. In the process of determining the measurement decimal part, the online calibration signal and the measurement reference clock are obtained by frequency multiplication of the measurement synchronous clock, wherein the three signals are determined, the period of the online calibration signal is not influenced by environmental factors such as temperature and the like to change, then n latching operations are carried out on the delay clock signal according to the online calibration signal, and the obtained multiple fitting straight lines can accurately represent the relation between the delay line channel number and the measurement decimal part M and cannot be influenced by the environmental factors. By latching the delay clock signal at the termination time, the measurement decimal part M is determined according to the delay clock signal corresponding to the termination time and the fitting straight line, and the measurement decimal part obtained according to the fitting straight line is not influenced by environment because the functional relation represented by the fitting straight line is not influenced by environment, so that the influence of environmental factors on the measurement accuracy of the time interval is eliminated, and the measurement accuracy is improved.

In one embodiment, as shown in FIG. 4, step 104 includes:

And step 402, when the level signal of the on-line calibration signal is a rising edge, performing a latch operation on the delayed clock signal to obtain a delayed clock signal corresponding to the latch operation.

In the embodiment of the application, when the level signal of the online calibration signal is the rising edge, the delayed clock signal can be latched once, at this time, the delayed clock signal on each delay line during the latching operation can be obtained, and the number of latching operations is also required to be counted, namely, the rising edge of the level signal of the online calibration signal is counted, so as to obtain the latching number.

The delay clock signal may be latched once when the level signal of the on-line calibration signal is a falling edge, or may be latched once when the level signal of the on-line calibration signal is changed.

It should be noted that the above is only an example of the latch operation in the embodiment of the present application, and the present application is not limited to the latch operation manner.

In step 404, when the number of latching operations is n, a plurality of fitting straight lines are determined according to the delay clock signals corresponding to the n latching operations.

In the embodiment of the application, when the latching times are n, the latching operation is not performed on the delayed clock signal, and a plurality of fitting straight lines are determined according to the delayed clock signal obtained by the n latching operations, wherein the latching times n can be set by a worker according to actual conditions.

The step of performing n latching operations on the delayed clock signal according to the online calibration signal may be performed before measurement starts or during measurement. If the latching times are performed during the measurement process, the latching times need to satisfy n×t ₀ < Δt, where n represents the latching times, T ₀ represents the on-line calibration signal period, and Δt represents the time interval to be measured.

In this embodiment, the delay clock signal is latched once at the rising edge of each online calibration signal, where the time corresponding to the rising edge of the online calibration signal is known and can be represented by the measurement reference clock period, so that the delay clock signal at the time corresponding to each latching operation can be obtained, so that according to the delay clock signal, a fitting straight line representing the relationship between the measurement reference clock period corresponding to the latching time and the delay line channel number can be obtained, and then according to the delay line channel number and the fitting straight line corresponding to the termination time, the corresponding measurement fractional part M can be directly obtained.

In one embodiment, referring to FIG. 5, step 404 comprises:

Step 502, for any latch operation, determining level change point information according to a delay clock signal corresponding to the latch operation, where the level change point information includes a target delay line channel number i and latch time information corresponding to the latch operation, and the level change point information is used to characterize a level change point, and in the latch operation, the delay clock signal corresponding to the target delay line channel number i is different from the level of the delay clock signal corresponding to the delay line channel number i-1, where i is an integer greater than 1.

In the embodiment of the application, for any latch operation, the delay clock signals on each delay line obtained by the latch operation are sequentially compared to determine the level change point information, wherein the level change point information is the information corresponding to the change of the level signal of the delay clock signal. The level change point information comprises a target delay line channel number i, a delay clock signal corresponding to the target delay line channel number i is different from the level of a delay clock signal corresponding to a delay line channel number i-1, i is an integer greater than 1, and the level change point information also comprises latch time information corresponding to a latch operation, wherein the latch time information is a measurement reference clock period corresponding to the moment of carrying out the latch operation.

And establishing a two-dimensional coordinate system by taking the decimal part of the measurement reference clock period corresponding to the latching moment as an x-axis and taking the delay line channel number as a y-axis, wherein the latching time information in the level change point information and the target delay line channel number i can determine the corresponding level change point in the two-dimensional coordinate system.

For example, referring to fig. 2, taking the above example as an example, taking the number of latches n as 2 as an example, it can be seen that the delay clock signal corresponding to the delay line channel number 4 is at a low level, the delay clock signal corresponding to the delay line channel number 3 is at a high level, and then the target delay channel number i=4, and the latch time information is 0.1T; the delay clock signal corresponding to the delay line channel number 7 is at a low level, and the delay clock signal corresponding to the delay line channel number 8 is at a high level, so that the target delay channel number i=8 and the latch time information is 0.1T.

In step 504, a plurality of lines to be fitted are determined according to the delay clock signals corresponding to the delay lines.

In the embodiment of the application, a plurality of to-be-fitted straight lines can be determined according to the delay clock signals corresponding to each delay line, wherein the level change points corresponding to the level change point information are distributed near each to-be-fitted straight line respectively, and the to-be-fitted straight lines can represent the distribution trend of each level change point, so that the level change points required for fitting the same straight line can be determined according to the to-be-fitted straight lines, and then straight line fitting is carried out according to the level change points to obtain a fitting straight line.

Step 506, fitting to obtain a plurality of fitting straight lines according to the level change point information and the plurality of straight lines to be fitted.

In the embodiment of the application, a plurality of fitting straight lines can be obtained by fitting according to the level change point information and a plurality of to-be-fitted straight lines, wherein the number of the to-be-fitted straight lines is the same as that of the fitting straight lines.

In the embodiment of the application, the level change point information of the level change in the delay clock signal obtained by each latching operation is firstly determined, then a plurality of lines to be fitted which can represent the distribution trend of the level change points corresponding to the level change point information are determined, wherein the level change points are distributed near the lines to be fitted, the level change points positioned in the same line to be fitted are used for fitting the same straight line to be fitted, and the fitting operation according to the level change points can be more accurately determined by determining the straight line to be fitted, so that the error in fitting is avoided.

In one embodiment, referring to fig. 6, the method further comprises:

Step 602, determining a period corresponding relation according to the period of the measurement reference clock and the period of the on-line calibration signal.

In the embodiment of the application, the period corresponding relation can be determined according to the period of the measurement reference clock and the period of the on-line calibration signal. For example: the period of the measurement reference clock is t=5s, the period of the on-line calibration signal is T ₀ =0.5s, and the period corresponding relation is T ₀ =0.1t.

Step 604, for any latch operation, determining the period information of the on-line calibration signal corresponding to the latch operation.

In the embodiment of the application, for any latch operation, the period information of the on-line calibration signal corresponding to the latch operation is determined, and the period information indicates that a plurality of periods of the on-line calibration signal pass from the beginning of measurement to the time of the latch operation. As still another example, referring to fig. 2 and 3, when the number of latches n=2, 1 period of the on-line calibration signal passes from the start of measurement to the 2 nd latch, and the period information of the latch operation corresponding to the on-line calibration signal is 1.

Step 606, determining the latch time information corresponding to the latch operation according to the period corresponding relation and the period information of the on-line calibration signal corresponding to the latch operation.

In the embodiment of the application, the period corresponding relation can be multiplied by the period information of the online calibration signal corresponding to the latch operation, and the obtained product is the latch time information corresponding to the latch operation, namely the measurement reference clock period corresponding to the moment of carrying out the latch operation.

In the embodiment of the application, each latching operation corresponds to each rising edge of the online calibration signal, so that the corresponding relation between the period of the measurement reference clock and the period of the online calibration signal can be determined to obtain the measurement reference clock period at the moment corresponding to the latching operation, namely the latching time information, the moment corresponding to the latching operation is expressed by the measurement reference clock period, the fitting straight line obtained subsequently is related to the measurement reference clock period, and the measurement reference clock period corresponding to the termination moment can be directly obtained when the termination moment is calculated according to the fitting straight line, namely the measurement decimal part M can be directly obtained, the data processing process is simplified, and the data processing efficiency is improved.

In one embodiment, the step 504 includes:

and carrying out connection processing on rising edges of delay clock signals corresponding to the first delay lines, and carrying out connection processing on falling edges of delay clock signals corresponding to the second delay lines to obtain a plurality of lines to be fitted, wherein the first delay lines are adjacent to each other, and the second delay lines are adjacent to each other.

In the embodiment of the application, rising edges of delay clock signals corresponding to the first delay lines which are adjacent to each other in pairs can be connected, and falling edges of delay clock signals corresponding to the second delay lines which are adjacent to each other in pairs can be connected, so that a plurality of straight lines to be fitted can be obtained.

And if the level change points near any one line to be fitted are regarded as a group of data points, the distance between each data point of the group and the line to be fitted is far smaller than the distance between the data points of the group and other lines to be fitted.

In the embodiment of the application, in the actual measurement process, the delay clock signals on each delay line at a certain moment can only be obtained through measurement, and the delay clock signals on each delay line at each moment can not be obtained as shown in fig. 2, so before the line connection is carried out on the straight line to be fitted, two level changes can be determined according to the delay clock signals obtained through any latch operation, the number of the delay lines with the phase difference between the two level changes is determined, the period of the delay clock signals with the phase difference between the two level changes is determined according to the two level changes, and the delay amount of one delay unit can be obtained according to the number of the delay lines with the phase difference and the period of the delay clock signals with the phase difference (the delay amount of each delay unit is assumed to be identical). Then, the delay clock signal corresponding to each delay line can be estimated based on the delay amount of the delay unit.

Illustratively, referring to FIG. 2, taking the 2 nd latch as an example, the first level change is: the level is changed from high to low, the channel number 1 of the delay line corresponding to the level change is 4, and the second level change is as follows: the level is changed from low to high, the channel number of the delay line corresponding to the level change is 8, the number of delay lines with phase difference between the two level changes is 4, the period of the phase difference delay clock signal is 0.5T, and the delay amount of one delay unit is obtained by dividing 0.5T by 4.

Then, as shown in fig. 2, the delayed clock signal on each delay line is delayed by 0.125T from the delayed clock signal on the last delay line, and the delayed clock signal corresponding to each delay line can be predicted according to the rule described above with reference to the delay line with the delay line channel number of 1.

After predicting the delay clock signals corresponding to each delay line, the embodiment of the application respectively connects the rising edge and the falling edge of the delay clock signals corresponding to the adjacent delay lines, and the obtained multiple lines to be fitted can represent the distribution trend of the level change points of the delay clock signals obtained by n latching operations, so that according to the lines to be fitted, the level change points can be determined to be used for fitting the same fitting line, and the condition of wrong fitting is avoided.

In one embodiment, referring to fig. 7, the level change point information further includes a change trend, where the change trend includes a first trend or a second trend, the first trend indicates that the level is changed from high to low, and the second trend indicates that the level is changed from low to high, and the step 506 includes:

Step 702, for any line to be fitted, determining a target level change point corresponding to the line to be fitted according to the level change point information, where the distance between the target level change point and the line to be fitted is smaller than a preset distance, and the change trend corresponding to each target level change point is the same.

In the embodiment of the application, for any straight line to be fitted, the distance between the level change point corresponding to each level change information and the straight line to be fitted is calculated, and the level change point with the distance smaller than the preset distance is used as the target level change point corresponding to the straight line to be fitted, wherein the change trend of the target level change point corresponding to the straight line to be fitted is the same.

The level change information comprises a change trend, the change trend comprises a first trend and a second trend, the first trend represents that the level is changed from high to low, and the second trend represents that the level is changed from low to high.

For example, referring to fig. 2, the oblique line is a line to be fitted, taking the line k ₁ to be fitted as an example, the target level change points corresponding to the line k ₁ to be fitted are respectively that the level changes from low to high at the delay line channel number 3 when the latch is performed for the 4 th time; at the time of 5 th latching, the level changes from low to high at the delay line channel number 5, and the change trend of the two level change points is the same.

And step 704, fitting according to the target level change points to obtain a fitting straight line.

In the embodiment of the application, the fitting line can be obtained by fitting the target level change points corresponding to the line to be fitted, wherein the fitting line can be obtained by fitting the target level change points corresponding to the line to be fitted according to the least square method, and the fitting line can be marked according to the change trend of the target level change points corresponding to the line to be fitted, and the marking is used for representing the change trend.

It should be noted that, in the embodiment of the present application, only one example of the fitting method is provided, and in practical application, other fitting methods may be adopted to perform the fitting, and the present application does not specifically limit the fitting method.

According to the embodiment of the application, the level change points corresponding to the straight line to be fitted are determined by comparing the distances between the level change points and the straight line to be fitted, and fitting is carried out according to the level change points corresponding to the straight line to be fitted, so that the fitted straight line is obtained.

In one embodiment, referring to fig. 8, the step 110 includes:

Step 802, determining termination level change point information of a termination time according to delay clock signals corresponding to each delay line at the termination time, wherein the termination level change point information comprises a termination level change trend and a termination delay line channel number j, the termination level change trend comprises a third trend or a fourth trend, the third trend represents that the level is changed from high to low, the fourth trend represents that the level is changed from low to high, the delay clock signals corresponding to the termination delay line channel number j are different from the level of the delay clock signals corresponding to the delay line channel number j-1, and j is an integer greater than 1.

In the embodiment of the application, delay clock signals on delay lines corresponding to termination time can be compared to determine information of points of level change, wherein the information is termination level change point information, the termination level change point information comprises a termination level change trend and a termination delay line channel number j, the termination level change trend comprises a third trend and a fourth trend, the third trend represents that the level is changed from high to low, the fourth trend represents that the level is changed from low to high, the delay clock signals corresponding to the termination delay line channel number j are different from the level of the delay clock signals corresponding to the delay line channel number j-1, and j is an integer greater than 1.

For example, referring to fig. 2, the delayed clock signal passed by the dashed line is the delayed clock signal corresponding to the termination time, at which the level changes 3 times, where the termination level change point 1 is that the level changes from low to high between the delay line channel numbers 3-4, the corresponding termination level change trend is the third trend, and the delay line channel number j ₁ =4 is terminated; the termination level change point 2 is that the level is changed from high to low between the delay line channel numbers 7-8, the corresponding termination level change trend is a fourth trend, and the delay line channel numbers j ₁ = 8 are terminated; the termination level change point 3 is a point where the level is changed from high to low between the delay line channel numbers 10 to 11, and the corresponding termination level change trend is a third trend, terminating the delay line channel numbers j ₁ =11.

Step 804, for any termination level change point information, determining a target fitting straight line corresponding to the termination level change point information from a plurality of fitting straight lines according to the termination level change trend and the termination delay line channel number j.

In the embodiment of the application, the same fitting straight line is marked for the change trend, the corresponding delay line channel numbers are not overlapped, namely, for any termination level change point information, according to the termination level change trend and the termination delay line channel number j, a corresponding unique target fitting straight line can be determined. The specific steps include: first, according to the variation trend of the termination level, determining first fitting straight lines identical to the variation trend of the termination level from a plurality of fitting straight lines, wherein each first fitting straight line corresponds to different delay line channel number ranges, so that the delay line channel number range to which the termination delay line channel number j belongs needs to be determined, and the first fitting straight line corresponding to the delay line channel number range is the target fitting straight line.

Step 806, determining a target measurement fraction part according to the termination level change point information and the target fitting straight line.

In the embodiment of the application, the termination delay line channel number j in the termination level change point information can be brought into the target fitting straight line, and the target measurement decimal part can be obtained through calculation.

Step 808, performing an average process on the target measurement fraction corresponding to the information of each termination level change point to obtain a measurement fraction M.

In the embodiment of the application, through the steps, a plurality of target measurement decimal parts can be obtained, and in order to obtain a more accurate measurement decimal part M, the average value of the target measurement decimal parts corresponding to the information of each termination level change point can be calculated, and the average value is taken as the measurement decimal part M.

Taking the example of information with 3 termination level change points as an example, the number of a termination delay line channel in the termination level change point information 1 is j ₁, the number of a termination delay line channel in the termination level change point information 2 is j ₂, the number of a termination delay line channel in the termination level change point information 3 is j ₃, j ₁、j₂、j₃ is substituted into a corresponding target fitting straight line, a target measurement fraction part a1, a target measurement fraction part a2 and a target measurement fraction part a3 are calculated, and then an average value of the 3 target measurement fraction parts is taken as a measurement fraction part M, namely m= (a1+a2+a3)/3.

According to the embodiment of the application, the target fitting straight line into which the termination level change point information is substituted is firstly determined through the termination level change point information, then the termination level change point information is substituted into the target fitting straight line to obtain the target measurement decimal part, the average value of each target measurement decimal part is used as the measurement decimal part M, the random error in the data processing process can be reduced in a mean value mode, the more accurate measurement decimal part M is obtained, and the measurement accuracy is improved.

In an embodiment of the present application, referring to fig. 9, the step 106 includes:

in step 902, after receiving the measurement start signal, when the level signal of the measurement synchronization clock is a rising edge, the rising edge of the level signal of the measurement reference clock is counted.

In the embodiment of the application, when only the measurement start signal is received, the measurement is not started until the level signal of the measurement synchronous clock is the rising edge, and the counting of the rising edge of the level signal of the measurement reference clock is started.

In step 904, when the measurement termination signal is received, counting of the rising edge of the level signal of the measurement reference clock is stopped, and a measurement integer part N is obtained, where N is a positive integer.

In the embodiment of the application, when the measurement termination signal is received, that is, the level rising edge of the measurement reference clock is not counted any more, the obtained number is the measurement integer part N, and N is a positive integer.

In the embodiment of the application, the time interval to be measured is divided into the measurement integer part N and the measurement decimal part M, and the measurement integer part N is obtained by a simple counting mode, so that the measurement process is simplified.

In a specific embodiment, the time interval measurement method is applied to an FPGA (Field Programmable gate array) chip (shown in fig. 10), firstly, a measurement synchronization clock is obtained, and frequency multiplication processing is performed on the measurement synchronization clock according to a preset frequency multiplication requirement to obtain a measurement reference clock and an on-line calibration signal, and taking the measurement synchronization clock with the frequency of 25Hz as an example, frequency multiplication is performed on the measurement synchronization clock to obtain a measurement reference clock with the frequency of 200Hz and an on-line calibration signal with the frequency of 2000 Hz.

The measured reference clock is delayed after passing through the delay line, and a delayed clock signal is obtained, fig. 11 and fig. 12 respectively show a multiphase clock TDC structure diagram based on a phase locked loop (PLL, phase Locked Loop) and a TDC basic structure diagram based on the delay line, and fig. 13 shows a schematic diagram of the multi-edge sampling principle performed by a Wave Union TDC.

Then, according to the rising edge of the on-line calibration signal, n latching operations are performed on the delayed clock signal, and, taking the above example as an example, n=5 is taken as an example, and as shown in fig. 2 and 3, latch time information corresponding to the above 5 latching operations is determined: according to the frequency of the measurement reference clock and the frequency of the on-line calibration signal, the period corresponding relation is T ₀ =0.1t, where T ₀ is the period of the on-line calibration signal, and T is the period of the measurement reference clock, so that latching time information corresponding to 5 latching operations can be obtained to be 0, 0.1, 0.2, 0.3 and 0.4 respectively. The level change point information can then be determined from the delayed clock signal obtained from the 5 latch operations.

According to the delay clock signals corresponding to the delay lines, a plurality of straight lines to be fitted are determined, and the process of determining the straight lines to be fitted refers to the above, and is not repeated here.

And determining target level change points corresponding to the straight lines to be fitted according to the distances between the level change points and the straight lines to be fitted, wherein when the distances between the level change points and the straight lines to be fitted are smaller than a preset distance, the level change points are the target level change points corresponding to the straight lines to be fitted. Taking the above example as an example, referring to fig. 2, for the line k ₁ to be fitted, the level change points corresponding to the line k ₁ to be fitted are respectively: the level changes from low to high at delay line channel number 3 at latch 4; when the level is latched for the 5 th time, the level is changed from low to high at the delay line channel number 5, and the level change point information of the corresponding target level change points is respectively as follows: target delay line channel number i ₁ =3, latch time information 1 is 0.3T; the target delay line channel number i ₂ =5, the latch time information 1 is 0.4T, and fitting processing can be performed on the two level change points according to the least square method, so as to obtain a fitting straight line 1 _{Second trend}. Repeating the above operation to obtain a plurality of fitting straight lines.

And after receiving the measurement start signal, when the level signal of the measurement synchronous clock is a rising edge, starting to count the rising edge of the level signal of the measurement reference clock, and when the measurement end signal is received, stopping counting the rising edge of the level signal of the measurement reference clock to obtain the measurement integer part N. And according to the measurement termination signal, latching the delay clock signal to obtain the delay clock signal corresponding to each delay line at the termination time.

Determining termination level change point information according to delay clock signals corresponding to each delay line at a termination time, and taking the above example as an example, referring to fig. 2, at the termination time, the level changes 3 times, wherein, a termination level change point 1 is that the level changes from low to high between delay line channel numbers 3-4, and then the corresponding termination level change trend is a third trend, and the delay line channel number j ₁ =4 is terminated; the termination level change point 2 is that the level is changed from high to low between the delay line channel numbers 7-8, the corresponding termination level change trend is a fourth trend, and the delay line channel numbers j ₁ = 8 are terminated; the termination level change point 3 is a point where the level is changed from high to low between the delay line channel numbers 10 to 11, and the corresponding termination level change trend is a third trend, terminating the delay line channel numbers j ₁ =11.

According to the termination level change trend and the termination delay channel number j, a target fitting straight line corresponding to the termination level change point is determined, and still taking the above example as an example, referring to fig. 2, the change trend of the termination level change point 1 is a fourth trend (the level changes from low to high), the fitting straight line identical to the fourth trend has a fitting straight line 1 _{Second trend} and a fitting straight line 3 _{Second trend}, and according to the termination delay channel number j ₁ =4, the corresponding target fitting straight line can be determined to be the fitting straight line 1 _{Second trend}.

After the target fitting straight line is obtained, substituting the termination level change point information (namely the termination delay line channel number j) into the target fitting straight line to obtain a target measurement fraction corresponding to the target fitting straight line, repeating the operation to obtain a plurality of target measurement fraction, and taking the average value of the plurality of target measurement fraction as the measurement fraction M.

Finally, the measured integer part N may be multiplied by the measured reference clock period T, the measured fractional part M may be multiplied by the measured reference clock period T, and the two multiplication results obtained above may be added to obtain the time interval to be measured.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.

In one embodiment, as described with reference to fig. 10, a time interval measurement chip, wherein the chip comprises: the phase-locked loop, the whole period counting unit, the delay line output state latch and the data processing unit; wherein,

the delay line output state latch is used for carrying out n latching operations on the delay clock signal according to the online calibration signal to obtain delay clock signals corresponding to the n latching operations, and sending the delay clock signals corresponding to the n latching operations to the data processing unit;

The data processing unit is used for receiving delay clock signals corresponding to N latching operations sent by the delay line output state latch, determining a plurality of fitting straight lines according to the delay clock signals corresponding to the N latching operations, wherein the time interval to be tested comprises a measurement integer part N and a measurement decimal part M, and the fitting straight lines represent the relation between the delay line channel number corresponding to the delay line and the measurement decimal part M, and N is a positive integer;

The whole period counting unit is used for counting the rising edge of the level signal of the measurement reference clock between the reception of the measurement starting signal and the reception of the measurement ending signal to obtain a measurement integer part N, and sending the measurement integer part N to the data processing unit;

The delay line output state latch is further used for latching the delay clock signal according to the measurement termination signal to obtain delay clock signals corresponding to the delay lines at the termination time and sending the delay clock signals corresponding to the delay lines at the termination time to the data processing unit;

The data processing unit is further used for receiving the delay clock signals corresponding to the delay lines at the termination time and the measurement integer part N, determining the measurement decimal part M according to the plurality of fitting straight lines and the delay clock signals corresponding to the delay lines at the termination time, and determining the time interval to be measured according to the measurement integer part N and the measurement decimal part M.

In the embodiment of the application, after the measurement synchronous clock is input into the PLL, the PLL can perform frequency multiplication processing on the measurement synchronous clock according to preset frequency multiplication requirements to respectively obtain the measurement reference clock and an online calibration signal, the measurement reference clock is respectively latched for n times according to the online calibration signal to obtain a plurality of fitting straight lines, the fitting straight lines are respectively sent to the whole period counting unit and the delay line, and the online calibration signal is sent to the delay line output state latch, wherein the PLL can ensure that the measurement reference clock and the online calibration signal are both rising edges when the measurement synchronous clock is rising edges when the PLL is frequency-multiplied.

The measurement synchronous clock is delayed after passing through the delay lines to obtain delay clock signals, referring to fig. 11, which is a schematic diagram of partial connection of the delay lines, and delay line output state latches are respectively connected with a plurality of delay lines, and can perform N latching operations on the delay clock signals according to online calibration signals to obtain a plurality of fitting straight lines, wherein a time interval to be measured includes a measurement integer part N and a measurement decimal part M, and the fitting straight lines represent the relationship between the delay line channel number and the measurement decimal part M, where N is a positive integer.

In one embodiment, the chip may further include a control unit for receiving the measurement start signal, the measurement synchronization clock, and the measurement end signal, and controlling the chip to start measurement according to the measurement start signal and the measurement synchronization clock, and controlling the chip to stop measurement according to the measurement end signal.

In the embodiment of the application, the whole period counting unit starts counting the rising edge of the level signal of the measurement reference clock when the measurement synchronous clock is the rising edge after receiving the measurement starting signal, and stops counting when receiving the measurement ending signal, so as to obtain the measurement integer part N.

And the delay line output state latch performs latching operation on the delay clock signal according to the measurement termination signal to obtain the delay clock signal corresponding to the termination moment.

The data processing unit is used for receiving the delay clock signal obtained by N times of latching operation, the delay clock signal corresponding to the termination time and the measurement integer part N sent by the whole period counting unit, determining the measurement decimal part M according to a plurality of fitting straight lines and the delay clock signal corresponding to the termination time, and determining the time interval to be measured according to the measurement integer part N and the measurement decimal part M.

The embodiment of the application determines the time interval to be measured by measuring how many periods of the measurement reference clock are in the time interval to be measured, wherein the number of the measurement reference clock periods corresponding to the time interval to be measured comprises a measurement integer part and a measurement decimal part. In the process of determining the measurement decimal part, the online calibration signal and the measurement reference clock are obtained by frequency multiplication of the measurement synchronous clock, wherein the three signals are determined, the period of the online calibration signal is not influenced by environmental factors such as temperature and the like to change, then n latching operations are carried out on the delay clock signal according to the online calibration signal, and the obtained multiple fitting straight lines can accurately represent the relation between the delay line channel number and the measurement decimal part M and cannot be influenced by the environmental factors. By latching the delay clock signal at the termination time, the measurement decimal part M is determined according to the delay clock signal corresponding to the termination time and the fitting straight line, and the measurement decimal part obtained according to the fitting straight line is not influenced by environment because the functional relation represented by the fitting straight line is not influenced by environment, so that the influence of environmental factors on the measurement accuracy of the time interval is eliminated, and the measurement accuracy is improved.

Based on the same inventive concept, the embodiment of the application also provides a time interval measuring device for realizing the above related time interval measuring method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitations in the embodiments of the time interval measurement device or time interval measurement devices provided below can be referred to above for the limitations of the time interval measurement method, and are not repeated here.

In one embodiment, as shown in fig. 14, there is provided a time interval measuring apparatus including: the acquisition module 1402, the first latching module 1404, the counting module 1406, the second latching module 1408, the first determination module 1410, and the second determination module 1412, wherein:

the acquisition module 1402 is configured to acquire a measurement synchronization clock, and perform frequency multiplication processing on the measurement synchronization clock to obtain a measurement reference clock and an online calibration signal respectively;

the first latch module 1404 is configured to perform N latching operations on the delayed clock signal according to the online calibration signal, obtain a plurality of fitting straight lines according to the delayed clock signal corresponding to the N latching operations, where the delayed clock signal is a measurement reference clock delayed by a plurality of delay lines, and the interval to be measured includes a measurement integer part N and a measurement fractional part M, and the fitting straight line represents a relationship between a delay line channel number corresponding to the delay line and the measurement fractional part M, where N is a positive integer;

a counting module 1406 for counting rising edges of a level signal of the measurement reference clock between receiving the measurement start signal and receiving the measurement end signal to obtain a measurement integer part N;

a second latch module 1408, configured to latch the delayed clock signal according to the measurement termination signal, to obtain a delayed clock signal corresponding to each delay line at the termination time;

A first determining module 1410, configured to determine a measurement fractional part M according to a plurality of fitting straight lines and delay clock signals corresponding to delay lines at a termination time;

A second determining module 1412, configured to determine a time interval to be measured according to the measured integer part N and the measured fractional part M.

In the embodiment of the application, the time interval to be measured is determined by measuring how many periods of the measurement reference clock are in the time interval to be measured, wherein the number of the measurement reference clock periods corresponding to the time interval to be measured comprises a measurement integer part and a measurement decimal part. In the process of determining the measurement decimal part, the online calibration signal and the measurement reference clock are obtained by frequency multiplication of the measurement synchronous clock, wherein the three signals are determined, the period of the online calibration signal is not influenced by environmental factors such as temperature and the like to change, then n latching operations are carried out on the delay clock signal according to the online calibration signal, and the obtained multiple fitting straight lines can accurately represent the relation between the delay line channel number and the measurement decimal part M and cannot be influenced by the environmental factors. By latching the delay clock signal at the termination time, the measurement decimal part M is determined according to the delay clock signal corresponding to the termination time and the fitting straight line, and the measurement decimal part obtained according to the fitting straight line is not influenced by environment because the functional relation represented by the fitting straight line is not influenced by environment, so that the influence of environmental factors on the measurement accuracy of the time interval is eliminated, and the measurement accuracy is improved.

In one embodiment, the first latch module 1404 is further configured to:

When the level signal of the online calibration signal is a rising edge, carrying out one-time latch operation on the delayed clock signal to obtain a delayed clock signal corresponding to the latch operation;

When the number of latching operations is n, a plurality of fitting straight lines are determined according to delay clock signals corresponding to the n latching operations.

In one embodiment, the first latch module 1404 is further configured to:

For any latching operation, determining level change point information according to a delay clock signal corresponding to the latching operation, wherein the level change point information comprises a target delay line channel number i and latching time information corresponding to the latching operation, the level change point information is used for representing a level change point, and in the latching operation, the delay clock signal corresponding to the target delay line channel number i is different from the level of the delay clock signal corresponding to the delay line channel number i-1, and i is an integer larger than 1;

determining a plurality of lines to be fitted according to delay clock signals corresponding to the delay lines;

and fitting to obtain a plurality of fitting straight lines according to the level change point information and the plurality of straight lines to be fitted.

In one embodiment, the apparatus further comprises:

The third determining module is used for determining a period corresponding relation according to the period of the measurement reference clock and the period of the on-line calibration signal;

A fourth determining module, configured to determine, for any latch operation, period information of an online calibration signal corresponding to the latch operation;

and the fifth determining module is used for determining the latching time information corresponding to the latching operation according to the period corresponding relation and the period information of the online calibration signal corresponding to the latching operation.

In one embodiment, the first latch module 1404 is further configured to:

In one embodiment, the level change point information further includes a change trend, the change trend including a first trend or a second trend, the first trend representing that the level is changed from high to low, the second trend representing that the level is changed from low to high, the first latch module 1404 is further configured to:

for any straight line to be fitted, determining a target level change point corresponding to the straight line to be fitted according to level change point information, wherein the distance between the target level change point and the straight line to be fitted is smaller than a preset distance, and the change trend corresponding to each target level change point is the same;

In one embodiment, the first determining module 1408 is further configured to:

Determining termination level change point information at termination time according to delay clock signals corresponding to delay lines at the termination time, wherein the termination level change point information comprises a termination level change trend and a termination delay line channel number j, the termination level change trend comprises a third trend or a fourth trend, the third trend represents that the level is changed from high to low, the fourth trend represents that the level is changed from low to high, the delay clock signals corresponding to the termination delay line channel number j are different from the level of the delay clock signals corresponding to the delay line channel number j-1, and j is an integer larger than 1;

For any termination level change point information, determining a target fitting straight line corresponding to the termination level change point information from a plurality of fitting straight lines according to the termination level change trend and the termination delay line channel number j;

and carrying out average value processing on the target measurement decimal part corresponding to the information of each termination level change point to obtain a measurement decimal part M.

In one embodiment, the counting module 1406 is further to:

after receiving the measurement start signal, counting the rising edge of the level signal of the measurement reference clock when the level signal of the measurement synchronous clock is the rising edge;

and stopping counting the rising edge of the level signal of the measurement reference clock under the condition that the measurement termination signal is received, and obtaining a measurement integer part N, wherein N is a positive integer.

The respective modules in the above-described time interval measuring apparatus may be implemented in whole or in part by software, hardware, and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims

1. A method of time interval measurement, the method comprising:

When the number of the latch operations is n, determining level change point information according to the delay clock signal corresponding to the latch operation for any latch operation, wherein the level change point information comprises a target delay line channel number i and latch time information corresponding to the latch operation, the level change point information is used for representing a level change point, and in the latch operation, the delay clock signal corresponding to the target delay line channel number i is different from the level of the delay clock signal corresponding to the delay line channel number i-1, and the i is an integer greater than 1;

Carrying out connection processing on rising edges of the delay clock signals corresponding to a plurality of first delay lines, and carrying out connection processing on falling edges of the delay clock signals corresponding to a plurality of second delay lines to obtain a plurality of lines to be fitted, wherein the plurality of first delay lines are adjacent to each other in pairs, and the plurality of second delay lines are adjacent to each other in pairs;

Fitting to obtain a plurality of fitting straight lines according to the level change point information and a plurality of to-be-fitted straight lines; the delay clock signal is the measurement reference clock delayed by a plurality of delay lines, the time interval to be measured comprises a measurement integer part N and a measurement decimal part M, and the fitted straight line represents the relation between the delay line channel number corresponding to the delay line and the measurement decimal part M, wherein N is a positive integer;

2. The method according to claim 1, wherein the method further comprises:

3. The method according to claim 1, wherein the level change point information further includes a change trend, the change trend includes a first trend or a second trend, the first trend represents that the level is changed from high to low, the second trend represents that the level is changed from low to high, and fitting to obtain a plurality of fitting straight lines according to the level change point information and the plurality of straight lines to be fitted includes:

4. A method according to any one of claims 1 to 3, wherein said determining said measured fractional part M from a plurality of said fitted straight lines and said delay clock signals corresponding to each of said delay lines at said termination time instants comprises:

5. The method according to claim 1, wherein counting rising edges of a level signal of the measurement reference clock between receiving a measurement start signal and receiving a measurement end signal to obtain the measurement integer part N includes:

6. A time interval measurement chip, the chip comprising: the phase-locked loop, the whole period counting unit, the delay line output state latch and the data processing unit; wherein,

The delay line output state latch is further used for carrying out latch operation on the delay clock signal once when the level signal of the online calibration signal is a rising edge, so as to obtain the delay clock signal corresponding to the latch operation;

The data processing unit is configured to receive the delay clock signals corresponding to the n times of latching operations sent by the delay line output state latch, determine, for any one of the latching operations, level change point information according to the delay clock signal corresponding to the latching operation, where the level change point information includes a target delay line channel number i and latch time information corresponding to the latching operation, and the level change point information is used to characterize a level change point, and in the latching operation, a level of the delay clock signal corresponding to the target delay line channel number i is different from a level of the delay clock signal corresponding to a delay line channel number i-1, where i is an integer greater than 1;

Fitting to obtain a plurality of fitting straight lines according to the level change point information and a plurality of to-be-fitted straight lines; the time interval to be measured comprises a measurement integer part N and a measurement decimal part M, wherein the fitted straight line represents the relation between the delay line channel number corresponding to the delay line and the measurement decimal part M, and N is a positive integer;

7. A time interval measurement apparatus, the apparatus comprising:

the first latch module is used for carrying out latch operation on the delay clock signal once when the level signal of the online calibration signal is a rising edge, so as to obtain the delay clock signal corresponding to the latch operation;

8. The time interval measurement apparatus of claim 7, wherein the apparatus further comprises:

9. The time interval measurement apparatus of claim 7, wherein the flat change point information further includes a change trend, the change trend including a first trend or a second trend, the first trend representing a level changing from high to low and the second trend representing a level changing from low to high, the first latch module further configured to:

10. The time interval measurement device of any one of claims 7-9, wherein the first determination module is further configured to: