CN110515822B - Interrupt response time test method, device, equipment and storage medium - Google Patents
Interrupt response time test method, device, equipment and storage medium Download PDFInfo
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- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
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Abstract
The application relates to an interrupt response time test method, an interrupt response time test device, interrupt response time test equipment and a storage medium. The interrupt response time testing method comprises the steps of outputting interrupt excitation signals to a processor to be tested and a accompany device at the same time; receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time length of the processor to be tested for reading the local time; and processing the current time, the reading operation time and the local time to obtain the interrupt response time of the current test of the processor to be tested. The interrupt excitation signals are simultaneously output to the processor to be tested and the accompanying device, so that the interrupt action executed by the processor to be tested and the action of resetting or latching the accompanying device at the current moment can be performed, errors caused by inconsistent actions are avoided, and the test of the interrupt response time is more accurate. The reading operation time length of the local time of the processor to be tested is obtained, so that the interrupt response time of the processor to be tested is more accurate.
Description
Technical Field
The present disclosure relates to the field of processor technologies, and in particular, to an interrupt response time testing method, apparatus, device, and storage medium.
Background
Along with the progress of microelectronic technology, integrated circuit products are increasingly widely applied and are ubiquitous in national economy and national defense security. The processor is the core of the integrated circuit product and plays roles of calculation processing, control, scheduling and the like. The interrupt function is one of the key functions of the processor, and the interrupt response time characterizes the performance parameters of the processor. The shorter interrupt response time enables the processor to generate a faster response to external interrupts, enhancing the processing power of the processor.
In the implementation process, the inventor finds that at least the following problems exist in the conventional technology: the conventional method for testing the interrupt response time of the processor has the problem of low precision.
Disclosure of Invention
In view of the foregoing, it is desirable to provide an interrupt response time testing method, apparatus, device, and storage medium capable of improving the interrupt response time testing accuracy.
In order to achieve the above object, an embodiment of the present invention provides an interrupt response time testing method, including the steps of:
simultaneously outputting an interrupt excitation signal to a processor to be tested and a accompany device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany measuring device to clear or latch the current moment;
receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time length of the processor to be tested for reading the local time;
and processing the current time, the reading operation time and the local time to obtain the interrupt response time of the current test of the processor to be tested.
In one embodiment, after the step of processing the current time, the read operation duration and the local time to obtain the interrupt response time of the current test of the processor to be tested, the method further includes the steps of:
accumulating the test times of the interrupt response time when the interrupt response time of the current test of the processor to be tested is obtained, until the test times of the interrupt response time reach a preset value;
when the number of times of the interrupt response time test reaches a preset value, obtaining the average interrupt response time according to each interrupt response time.
In one embodiment, before the step of simultaneously outputting the interrupt excitation signal to the processor under test and the accompanying device, the method further comprises the steps of:
and performing phase alignment processing on the intermediate excitation signal.
In one embodiment, the step of obtaining a read operation duration of the processor to be tested for reading the local time includes:
indicating a processor to be tested to read the local time of the accompanying device;
receiving a local time fed back by the accompany measuring device;
when the local time of the accompanying test device is received, accumulating the test times of the read operation duration until the test times of the read operation duration reach the preset times;
when the test times of the read operation duration reach the preset times, processing each local moment to obtain the read operation duration.
In one embodiment, in the step of processing each local time to obtain the read operation duration, the read operation duration is obtained based on the following formula:
wherein DeltaT m The time length of the m-th test read operation is the time length; t (T) m+1 The local time of the (m+1) th test; t (T) m The local time of the mth test; t (T) s For a time interval in which the excitation signal is interrupted; t (T) read For the duration of the read operation.
In one embodiment, in the step of processing the current time, the read operation duration and the local time to obtain the interrupt response time of the current test of the to-be-tested processor, the interrupt response time of the to-be-tested processor is obtained based on the following formula:
T IR ＝T R -T read -T 1 ；
wherein T is IR Is an interrupt response time; t (T) read Is the read operation duration; t (T) R For local time, T 1 Is the current time.
In one embodiment, before the step of outputting the interrupt excitation signal to the processor under test, the method further includes the steps of:
and performing time error correction processing on the accompanying measuring device by adopting the second pulse signal.
The embodiment of the invention also provides an interrupt response time testing device, which comprises:
the signal output module is used for simultaneously outputting an interrupt excitation signal to the processor to be tested and the accompanying device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompanying measuring device to execute response actions, and the response actions comprise zero clearing or latching the current moment;
the local time acquisition module is used for receiving the local time fed back by the processor to be tested and the current moment fed back by the accompanying measuring device;
the read operation duration acquisition module is used for acquiring the read operation duration of the processor to be tested for reading the local time;
the data processing module is used for processing the current moment, the reading operation duration and the local time to obtain the interrupt response time of the current test of the processor to be tested.
The embodiment of the invention also provides an interrupt response time testing device, which comprises a accompany device, a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of any one of the methods when executing the computer program.
The present invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of any of the methods described above.
One of the above technical solutions has the following advantages and beneficial effects:
according to the interrupt response time testing method, the interrupt excitation signals are output to the to-be-tested processor and the accompanying device at the same time, so that interrupt action executed by the to-be-tested processor and action of resetting or latching the accompanying device at the current moment can be performed, errors caused by inconsistent actions are avoided, and the interrupt response time is tested more accurately. The interrupt excitation signal instructs the processor to be tested to execute the interrupt action and reads the local time in the accompanying test device. The local time thus read includes the interrupt response time, the current time, and the local time in the read companion device. And acquiring the reading operation time length of the processor to be tested for reading the local time, thereby acquiring the interrupt response time of the processor to be tested. Meanwhile, the interrupt response time testing method provided by the application does not need expensive instruments such as oscilloscopes, and has the advantages of low cost, high efficiency and easiness in popularization. Meanwhile, the method is suitable for processors such as CPU, SOC, MCU, DSP and the like, and board cards and complete machine systems thereof, and has high universality. The accompanying test device can adopt a programmable logic device, can carry out parallel test on multiple paths of interrupt signals, and has high test efficiency and low time cost.
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The foregoing and other objects, features and advantages of the present application will be apparent from the more particular description of the preferred embodiments of the present application as illustrated in the accompanying drawings. Like reference numerals refer to like parts throughout the drawings, and the drawings are not intentionally drawn to scale on actual size or the like, emphasis instead being placed upon illustrating the subject matter of the present application.
FIG. 1 is a first schematic flow diagram of an interrupt response time test method in one embodiment;
FIG. 2 is a second schematic flow diagram of an interrupt response time test method in one embodiment;
FIG. 3 is a third schematic flow diagram of an interrupt response time test method in one embodiment;
FIG. 4 is a fourth schematic flow diagram of an interrupt response time test method in one embodiment;
FIG. 5 is a first schematic flow diagram of a read operation duration to obtain local time read by a processor under test in one embodiment;
FIG. 6 is a second schematic flow diagram of a read operation duration to obtain local time read by a processor under test in one embodiment;
FIG. 7 is a fifth schematic flow chart diagram of an interrupt response time test method in one embodiment;
FIG. 8 is a first schematic block diagram of an interrupt response time testing apparatus in one embodiment;
FIG. 9 is a second schematic block diagram of an interrupt response time testing apparatus in one embodiment;
FIG. 10 is a third schematic block diagram of an interrupt response time testing apparatus in one embodiment;
FIG. 11 is an internal block diagram of an interrupt response time test apparatus in one embodiment;
FIG. 12 is a block diagram of the results of an interrupt response time tester in one embodiment;
FIG. 13 is a flow chart of a method for testing interrupt response time of a multi-interrupt stimulus signal in one embodiment.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to and integrated with the other element or intervening elements may also be present. The terms "read," "perform," "feedback," and similar expressions are used herein for the purpose of illustration only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
For the test of the interrupt response time, the general method is to measure the trigger and response signals by adopting an oscilloscope, and count the difference between the trigger and response signals as the interrupt response time. The method has the characteristics of simple realization, easy operation and the like, needs to rely on hardware accompany test products such as oscilloscopes and the like, and has the following defects in the process of testing the interrupt response time in actual use of the oscilloscopes: oscilloscopes are heavy, difficult to carry, high in price, incapable of performing multichannel parallel testing and low in precision.
The interrupt response time testing method provided by the application can effectively solve the problems.
In one embodiment, as shown in fig. 1, there is provided an interrupt response time testing method, including the steps of:
s110, simultaneously outputting an interrupt excitation signal to a processor to be tested and a partner device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany measuring device to clear the current time or latch the current time;
the companion device includes any device in the art that can provide a timing module. Alternatively, the companion device may comprise a programmable logic device, such as an FPGA (Field-Programmable Gate Array, programmable gate array) or a CPLD (Complex Programmable Logic Device ). A timing module in the FPGA or CPLD may calculate time based on the clock frequency provided by the local crystal oscillator. In particular, the local crystal oscillator may be a high stability clock frequency source. In a specific example, the clock frequency may be 33.33MHz or 50MHz, which can provide timing accuracy in the range of 20ms to 100 ms. The interrupt stimulus signal is one of the stimulus signals and may include a pulse-per-second signal.
It should be noted that any method in the art may be used to output the interrupt excitation signal to the processor to be tested and the accompanying device at the same time. The interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device. In one specific example, upon receipt of an interrupt stimulus signal by a processor under test, the processor under test enters an interrupt handling service routine that indicates a local time in the read companion device.
The interrupt excitation signal is used for indicating the accompany measuring device to clear or latch the current moment. Specifically, whether to instruct the companion device to perform zero clearing or latching the current time may be determined by the companion device. In a specific example, when the interrupt excitation signal is connected to the zero clearing end of the FPGA, the logic unit in the FPGA clears the current time of the timing module based on the interrupt excitation signal, and when the interrupt excitation signal is connected to the latch enabling end of the FPGA, the logic unit in the FPGA latches the current time of the timing module based on the interrupt excitation signal.
S120, receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time of the processor to be tested for reading the local time;
it should be noted that, the local time fed back by the processor to be tested and the current time fed back by the accompanying device may be obtained by any means in the art. For example: the processor to be tested can read the local time, store the local time in the storage module, and then read the local time fed back by the processor to be tested from the storage module; the local time read by the processor to be tested can also be directly received. In one specific example, the local time may be stored in an array by way of a pointer. The same applies to the current moment of receiving feedback from the accompanying measuring device.
The reading operation duration of the local time of the processor to be measured can be obtained by any technical means in the field, for example, the local time can be cleared to send a command for reading the local time, so that the processor to be measured reads the local time, and the read time is the reading operation duration. For another example, the read operation duration may be obtained by reading the local time multiple times, and by calculating the difference between the local times.
S130, processing the current moment, the reading operation duration and the local time to obtain the interrupt response time of the current test of the processor to be tested.
Specifically, the difference between the local time and the current time is the sum of the interrupt response time and the read operation duration. And processing the current moment, the reading operation duration and the local time to obtain the response time of the terminal of the current test of the processor to be tested.
In one embodiment, in the step of processing the current time, the read operation duration and the local time to obtain the interrupt response time of the current test of the to-be-tested processor, the interrupt response time of the to-be-tested processor is obtained based on the following formula:
T IR ＝T R -T read -T 1 ；
wherein T is IR Is an interrupt response time; t (T) read Is the read operation duration; t (T) R For local time, T 1 Is the current time.
According to the interrupt response time testing method, the interrupt excitation signals are output to the processor to be tested and the accompanying device at the same time, so that interrupt action executed by the processor to be tested and action of resetting or latching the accompanying device at the current moment can be performed, errors caused by inconsistent actions are avoided, and the interrupt response time is tested more accurately. The interrupt excitation signal instructs the processor to be tested to execute the interrupt action and reads the local time in the accompanying test device. The local time thus read includes the interrupt response time, the current time, and the local time in the read companion device. And acquiring the reading operation time length of the processor to be tested for reading the local time, thereby acquiring the interrupt response time of the processor to be tested. Meanwhile, the interrupt response time testing method provided by the application does not need expensive instruments such as oscilloscopes, and has the advantages of low cost, high efficiency and easiness in popularization. Meanwhile, the method is suitable for processors such as CPU, SOC, MCU, DSP and the like, and board cards and complete machine systems thereof, and has high universality. The accompanying test device can adopt a programmable logic device, can carry out parallel test on multiple paths of interrupt signals, and has high test efficiency and low time cost.
In one embodiment, as shown in fig. 2, there is provided an interrupt response time testing method, including the steps of:
s210, simultaneously outputting an interrupt excitation signal to a processor to be tested and a partner device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany measuring device to clear or latch the current moment;
s220, receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time of the processor to be tested for reading the local time;
s230, processing the current moment, the reading operation duration and the local time to obtain the interrupt response time of the current test of the processor to be tested.
S240, when the interrupt response time of the current test of the processor to be tested is obtained, accumulating the test times of the interrupt response time until the test times of the interrupt response time reach a preset value;
the preset value can be adjusted, and in actual measurement, the preset value is not lower than 1000 times. And a plurality of test results are obtained through repeated circulation, so that random errors and time errors caused by instability of a timing module in the accompanying test device are eliminated. When the accompanying measurement device is an FPGA or a CPLD, the local time of the accompanying measurement device can be influenced by the instability of the local crystal oscillator.
S250, when the test times of the interrupt response time reach a preset value, obtaining the average interrupt response time according to each interrupt response time.
Specifically, each interrupt response time is processed, and an interrupt response average time is obtained. In one particular example, the interrupt response times may be averaged to obtain an interrupt response average time. Performing multiple tests may improve the accuracy of the resulting interrupt response time.
To further illustrate the solution of this embodiment, the description is specifically provided with reference to a specific test procedure:
the interrupt response time test flow of the processor is shown in fig. 3, and the main process of running the test program in the operating system of the processor by taking the second pulse as an interrupt excitation signal is as follows:
s310, starting a second pulse and processor interrupt, and setting a processor interrupt frequency variable n to 0;
s320, the second pulse triggers a processor interrupt,
s330 and entering a processor interrupt service routine;
s340, in the interrupt service routine of the processor, the processor reads the time less than seconds in the CPLD/FPGA, marks the time as the time, and stores the time into an array through a pointer;
s350, adding 1 to the interruption time variable n;
s360, judging whether n exceeds the preset total interruption times or not;
s370, if the interrupt response times of the processor do not reach N times, continuing to wait for interrupt response; if the processor has performed N interrupt responses, then a time average value read by the processor from the CPLD/FPGA is calculated.
In one embodiment, as shown in fig. 4, before the step of simultaneously outputting the interrupt excitation signal to the processor under test and the accompanying device, the method further includes the steps of:
s410, performing phase alignment processing on the interrupt excitation signal.
The phase alignment is used for enabling the processor to be tested and the accompanying device to trigger actions at the same time; specifically, for the processor to be tested, the interrupt excitation signal triggers the processor to perform an interrupt action. For the accompanying test device, the interrupt excitation signal triggers the accompanying test device to perform zero clearing or latching.
S420, simultaneously outputting an interrupt excitation signal to the processor to be tested and the accompanying device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany measuring device to clear or latch the current moment;
s430, receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time of the processor to be tested for reading the local time;
s440, processing the current moment, the reading operation duration and the local time to obtain the interrupt response time of the current test of the processor to be tested.
The alignment processing is carried out through the multi-interrupt excitation signals, so that the difference value between the local time read by the processor to be detected and the current time is ensured, and the sum of the interrupt response time and the read operation time length is ensured, so that the interrupt response time obtained by the interrupt response time testing method provided by the embodiment is more accurate.
In one embodiment, as shown in fig. 5, the step of obtaining a read operation duration of the processor to be tested for reading the local time includes:
s510, indicating a processor to be tested to read the local time of the accompanying device;
the local time is the time read by the processor to be tested, and it should be noted that the local time and the local time refer to different times.
Specifically, the processor to be tested can be controlled in the form of sending instructions so as to read the local time of the accompanying device.
S520, receiving the local time fed back by the accompanying measuring device;
specifically, the local time of day of the companion device feedback may be received by any means known in the art.
S530, when the local time of the accompanying test device is received, accumulating the test times of the read operation duration until the test times of the read operation duration reach the preset times;
s540, when the test times of the read operation duration reach the preset times, processing each local time to obtain the read operation duration.
It should be noted that, because the local time in the accompanying device is continuously read, the difference between the local time of two adjacent readings of the processor to be tested is the reading operation duration of the processor in the mth test. Further, the obtained read operation duration can be averaged to eliminate random errors and time errors caused by instability of the accompanying measurement device.
In one embodiment, in the step of processing each local time to obtain the read operation duration, the read operation duration is obtained based on the following formula:
wherein DeltaT m The time length of the m-th test read operation is the time length; t (T) m+1 For test m+1thLocal time; t (T) m The local time of the mth test; t (T) s For a time interval in which the excitation signal is interrupted; t (T) read For the duration of the read operation.
The read operation duration of the processor to be tested is acquired through the method and the device, and the operation flow is few. If the accompanying measuring device is subjected to zero clearing processing, the reading operation duration is obtained, the problem that zero clearing action and the reading operation duration can not be performed simultaneously exists, the operation is complex, and the accuracy is low.
To further illustrate the method of the read operation duration of the present embodiment, as shown in fig. 6, a specific test procedure is specifically described. The interrupt excitation signal is a second pulse signal, and the accompanying device is a CPLD or an FPGA. The method comprises the following steps:
s610, a pulse per second interrupt (the interrupt may be a rising edge, a falling edge, or a high-low level trigger) is turned on, and the pulse per second interrupt will perform a cleaning operation on a timer below seconds in the CPLD/FPGA. Setting a circulation time variable m to be 0 in the processor;
s620, the processor reads the time less than seconds in the CPLD/FPGA through a read command and stores the time in an array in a pointer mode;
s630, adding 1 to the cycle number variable m;
s640, judging whether m exceeds a preset total number of cycles;
s650, if the number of the processor read operations does not reach M, continuing to perform the cyclic read operation; if the processor has performed M read operations, an average read operation duration of the processor is calculated.
In one embodiment, as shown in fig. 7, before the step of outputting the interrupt excitation signal to the processor under test, the method further includes the steps of:
s710, performing time error correction processing on the accompanying device by adopting the second pulse signal.
The second pulse refers to a synchronizing signal transmitted by a satellite navigation system such as a GPS or Beidou.
Specifically, the timing module of the accompanying measuring device is corrected by the second pulse signal, so that the time precision can reach 100ns.
S720, simultaneously outputting an interrupt excitation signal to the processor to be tested and the accompanying device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany measuring device to clear or latch the current moment;
s730, receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time of the processor to be tested for reading the local time;
s740, processing the current time, the reading operation time and the local time to obtain the interrupt response time of the current test of the processor to be tested.
The local time of the accompanying and testing device is corrected by adopting the second pulse signal, so that the accompanying and testing device meets the precision requirement, and the accuracy of the interrupt response time testing method of the embodiment is improved.
It should be understood that, although the steps in the flowcharts of fig. 1-7 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-7 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or steps.
In one embodiment, as shown in fig. 8, there is provided an interrupt response time testing apparatus, including:
the signal output module 810 is configured to output an interrupt excitation signal to the processor to be tested and the accompanying device at the same time; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompanying measuring device to execute response actions, and the response actions comprise zero clearing or latching the current moment;
the local time acquisition module 820 receives the local time fed back by the processor to be tested and the current time fed back by the accompanying measuring device;
a read operation duration obtaining module 830, configured to obtain a read operation duration of the to-be-detected processor when the to-be-detected processor reads the local time;
the data processing module 840 is configured to process the current time, the read operation duration and the local time to obtain an interrupt response time of the current test of the processor to be tested.
In one embodiment, as shown in fig. 9, there is provided an interrupt response time testing apparatus, including:
a signal output module 910, configured to output an interrupt excitation signal to the processor to be tested and the accompanying device at the same time; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompanying measuring device to execute response actions, and the response actions comprise zero clearing or latching the current moment;
the local time acquisition module 920 receives the local time fed back by the processor to be tested and the current time fed back by the accompanying measurement device;
a read operation duration obtaining module 930, configured to obtain a read operation duration of the to-be-detected processor when reading the local time;
the data processing module 940 is configured to process the current time, the read operation duration, and the local time to obtain an interrupt response time of the current test of the processor to be tested.
The accumulating module 950 is configured to accumulate the number of times of the interrupt response time when the interrupt response time of the current test of the processor to be tested is obtained, until the number of times of the interrupt response time reaches a preset value;
the average calculating module 960 is configured to obtain an average interrupt response time according to each interrupt response time when the number of interrupt response time tests reaches a preset value.
In one embodiment, as shown in fig. 10, there is provided an interrupt response time testing apparatus, further including:
the phase alignment module 900 is configured to perform phase alignment processing on the intermediate excitation signal.
For specific limitations of the interrupt response time test apparatus, reference may be made to the limitations of the interrupt response time test apparatus method hereinabove, and no further description is given here. The respective modules in the interrupt response time test apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, an interrupt response time testing device is provided, which may be a terminal, the internal structure of which may be as shown in fig. 11. The computer device comprises a processor, a memory, a network interface, a companion device, a display screen and an input device which are connected through a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements an interrupt response time test method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the structure shown in fig. 11 is merely a block diagram of a portion of the structure associated with the present application and is not limiting of the computer device to which the present application applies, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, an interrupt response time testing apparatus is provided, comprising a companion device, a memory, and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
simultaneously outputting an interrupt excitation signal to a processor to be tested and a accompany device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany measuring device to clear or latch the current moment;
receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time length of the processor to be tested for reading the local time;
and processing the current time, the reading operation time and the local time to obtain the interrupt response time of the current test of the processor to be tested.
In one embodiment, after the step of obtaining the interrupt response time of the current test of the processor to be tested by executing the step of processing the current time, the read operation duration and the local time by the processor by the computer program, the following steps are further implemented:
accumulating the test times of the interrupt response time when the interrupt response time of the current test of the processor to be tested is obtained, until the test times of the interrupt response time reach a preset value;
when the number of times of the interrupt response time test reaches a preset value, obtaining the average interrupt response time according to each interrupt response time.
In one embodiment, before the processor executes the computer program to output the interrupt stimulus signal to the processor under test and the companion device simultaneously, the following steps are also implemented:
and performing phase alignment processing on the intermediate excitation signal.
In one embodiment, the step of the processor performing a read operation duration to obtain a local time of the processor under test includes:
indicating a processor to be tested to read the local time of the accompanying device;
receiving a local time fed back by the accompany measuring device;
when the local time of the accompanying test device is received, accumulating the test times of the read operation duration until the test times of the read operation duration reach the preset times;
when the test times of the read operation duration reach the preset times, processing each local moment to obtain the read operation duration.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
simultaneously outputting an interrupt excitation signal to a processor to be tested and a accompany device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany measuring device to clear or latch the current moment;
receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation time length of the processor to be tested for reading the local time;
and processing the current time, the reading operation time and the local time to obtain the interrupt response time of the current test of the processor to be tested.
In one embodiment, after the step of obtaining the interrupt response time of the current test of the to-be-tested processor, the computer program when executed by the processor processes the current time, the read operation duration and the local time, further implements the following steps:
accumulating the test times of the interrupt response time when the interrupt response time of the current test of the processor to be tested is obtained, until the test times of the interrupt response time reach a preset value;
when the number of times of the interrupt response time test reaches a preset value, obtaining the average interrupt response time according to each interrupt response time.
In one embodiment, the computer program when executed by the processor processes the current time, the read operation duration and the local time, and before obtaining the interrupt response time of the current test of the processor to be tested, the following steps are further implemented:
and performing phase alignment processing on the intermediate excitation signal.
In one embodiment, the step of obtaining a read operation duration of the processor under test for reading the local time when the computer program is executed by the processor includes:
indicating a processor to be tested to read the local time of the accompanying device;
receiving a local time fed back by the accompany measuring device;
when the local time of the accompanying test device is received, accumulating the test times of the read operation duration until the test times of the read operation duration reach the preset times;
when the test times of the read operation duration reach the preset times, processing each local moment to obtain the read operation duration.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The interrupt response time test method can also be simultaneously applied to parallel test of multiple interrupt signals, and is now described with reference to specific examples, and the specific examples are as follows:
the interrupt response time tester for any pulse of the processor is shown in fig. 12, and comprises a processor to be tested and a companion device (CPLD or FPGA). In practical applications, the interrupt response time testing apparatus shown in fig. 12 may be designed and manufactured separately, or may be integrated into a complete machine system as part of a system processing platform. The second pulse is usually a synchronizing signal transmitted by a satellite navigation system such as a GPS or Beidou, and is used for synchronizing time of the accompanying measuring device and correcting errors of the timing module. Meanwhile, the second pulse signal can clear the local timing module in the CPLD or the FPGA so as to restart timing, so that the local time can be synchronous with the second pulse, the local timing module of the accompanying and detecting device can calculate the time based on the clock frequency provided by the local crystal oscillator, and the time precision can reach hundred nanoseconds. The main function of the CPLD or FPGA in the test board of fig. 12 is to provide a clock of less than local seconds for the processor to be tested, the timing module of which is similar to the function of a counter, calculates time based on the clock frequency provided by the local crystal oscillator, and provides time accuracy of hundred nanoseconds for the processor. The local crystal oscillator can be a high-stability clock frequency source, such as 33.33MHz, 50MHz and the like, and can provide timing accuracy in the range of 20ns to 100ns.
In the process of testing the response time of any impulse interruption of a processor, a second impulse signal of a satellite navigation system is adopted, and the main function of the second impulse signal is to synchronize the local time and ensure the second-level precision of the local time. In fig. 12, IR0 is a pulse per second signal, IR1, IR2, …, and IRx represents an interrupt signal for a total of x paths. An IRx interrupt signal input into the CPLD or FPGA triggers two actions: firstly, an IRx interrupt signal triggers a time latch in a CPLD or an FPGA, and latches a current time value when IRx arrives into an output register so as to be read by a processor later; meanwhile, IRx interrupt signals can be output to an interrupt input port of the processor through the transmission of the CPLD or the FPGA, and the processor is triggered to generate interrupt.
The interrupt stimulus signals IR1, IR2, …, IRx are generated by an external signal source, an external CPLD/FPGA or a CPLD/FPGA device on the test board. IR0 can be used as both a second pulse signal and an interrupt excitation signal, IRx being used only as the interrupt excitation signal. In the test process, the value of x in IRx is determined according to the available interrupt number of the processor, and the value can be 4 paths or 6 paths in general. The CPLD/FPGA on the test board needs to perform phase alignment processing on the triggered latching time and the interrupt signal output to the interrupt port of the processor according to the interrupt excitation signal of IRx, so that the reading time of the processor to be tested is ensured to be the sum of interrupt response time and processor reading operation time.
The test flow of the response time of the random impulse interruption of the processor is shown in fig. 13, and the main processing procedure is as follows:
turning on the second pulse and the processor interrupt, setting the processor interrupt number variable nx to 0 (x=0, 1,2, … represents the number of interrupt paths), and setting the processor interrupt priority;
the interrupt excitation signal triggers the processor interrupt and enters a corresponding processor interrupt service routine;
in the interrupt service routine of the processor, the processor reads the time less than or equal to the second of IRx (x=0, 1,2, …) latch in the CPLD/FPGA, and records the time as Δt R And storing the data into an array through a pointer;
the interruption time variable nx is added with 1;
judging whether Nx exceeds a preset total interruption number Nx;
if the interrupt response times of the processor do not reach Nx times, continuing to wait for interrupt response; if the processor has already performed Nx interrupt responses, then the time average value (T Rx )。
During a total of Nx interrupt responses, the processor reads a time average (T Rx ) The calculation can be performed by the following formula, where x=0, 1,2, … represent different interrupt ports.
The average interrupt response time (T) of the processor can then be derived based on the processor interrupt response time test timing relationship of fig. 3 IRx ) The following formula is shown:
T IRx ＝T Rx -T read
in practical measurement, the value of Nx is usually not lower than 1000 times.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. An interrupt response time testing method, comprising the steps of:
simultaneously outputting an interrupt excitation signal to a processor to be tested and a accompany device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompany device to clear or latch the current moment;
receiving the local time fed back by the processor to be tested and the current time fed back by the accompanying device, and acquiring the reading operation duration of the processor to be tested for reading the local time;
obtaining the interrupt response time of the current test of the processor to be tested based on the following formula:
T IR ＝T R -T read -T 1 ；
wherein T is IR For the interrupt response time; t (T) read For the read operation duration; t (T) R For the local time, T 1 And the current moment is the current moment.
2. The interrupt response time testing method according to claim 1, wherein after the step of obtaining the interrupt response time of the current test of the processor to be tested, the method further comprises the steps of:
accumulating the test times of the interrupt response time when the interrupt response time of the current test of the processor to be tested is obtained until the test times of the interrupt response time reach a preset value;
and when the test times of the interrupt response time reach a preset value, acquiring the average interrupt response time according to each interrupt response time.
3. The interrupt response time test method of claim 1, further comprising, before the step of simultaneously outputting an interrupt stimulus signal to the processor under test and the companion device, the step of:
and carrying out phase alignment processing on the interrupt excitation signal.
4. The interrupt response time testing method according to claim 1, wherein the step of obtaining a read operation duration of the processor under test for reading the local time comprises:
indicating the processor to be tested to read the local time of the accompanying device;
receiving the local time fed back by the accompanying measuring device;
when the local time of the accompanying and testing device is received, accumulating the test times of the read operation duration until the test times of the read operation duration reach the preset times;
and when the test times of the read operation duration reach the preset times, processing each local time to obtain the read operation duration.
5. The interrupt response time testing method of claim 4 wherein in the step of processing each of the local time instants to obtain the read operation duration, the read operation duration is obtained based on the following formula:
wherein DeltaT m The time length of the m-th test read operation is the time length; t (T) m+1 The local time of the (m+1) th test; t (T) m The local time of the mth test; t (T) s A time interval for said interrupt stimulus signal; t (T) read For the duration of the read operation.
6. The interrupt response time testing method of claim 1, further comprising the step of, prior to the step of outputting an interrupt stimulus signal to the processor under test:
and carrying out time error correction processing on the accompanying measuring device by adopting a second pulse signal.
7. An interrupt response time testing apparatus, comprising:
the signal output module is used for simultaneously outputting an interrupt excitation signal to the processor to be tested and the accompanying device; the interrupt excitation signal is used for indicating the processor to be tested to execute interrupt action and reading the local time in the accompanying test device; the interrupt excitation signal is used for indicating the accompanying device to execute response actions, and the response actions comprise zero clearing or latching the current moment;
the local time acquisition module is used for receiving the local time fed back by the processor to be tested and the current moment fed back by the accompanying measuring device;
the read operation duration acquisition module is used for acquiring the read operation duration of the local time read by the processor to be detected;
the data processing module is used for obtaining the interrupt response time of the current test of the processor to be tested based on the following formula:
T IR ＝T R -T read -T 1 ；
wherein T is IR For the interrupt response time; t (T) read For the read operation duration; t (T) R For the local time, T 1 And the current moment is the current moment.
8. The interrupt response time testing device of claim 7, wherein the device further comprises:
the accumulation module is used for accumulating the test times of the interrupt response time when the interrupt response time of the current test of the processor to be tested is obtained, until the test times of the interrupt response time reach a preset value;
and the average value calculation module is used for acquiring the average time of the interrupt response according to each interrupt response time when the test times of the interrupt response time reach a preset value.
9. An interrupt response time testing device comprising a companion device, a memory and a processor, the memory storing a computer program, wherein the processor, when executing the computer program, implements the steps of the method of any one of claims 1 to 6.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 6.
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