CN114623939A

CN114623939A - Method, device, equipment and medium for determining pulse frequency

Info

Publication number: CN114623939A
Application number: CN202210389470.6A
Authority: CN
Inventors: 邱杭锴; 钟奋忠; 王宾
Original assignee: Hangzhou Aochuang Photonics Technology Co ltd
Current assignee: Hangzhou Aochuang Photonics Technology Co ltd
Priority date: 2022-04-13
Filing date: 2022-04-13
Publication date: 2022-06-14

Abstract

The embodiment of the invention discloses a method, a device, equipment and a medium for determining pulse frequency. The method comprises the following steps: acquiring the clock frequency of a reference clock; counting a first count value of the reference clock and a second count value of a signal to be detected within a set time length; and determining the pulse frequency of the signal to be detected according to the clock frequency, the first counting value and the second counting value. The embodiment of the invention triggers two counters to count through one reference clock to obtain two groups of counting values, and determines the pulse frequency of the signal to be measured by combining the clock frequency of the reference clock, thereby solving the problem of abnormal data of the counter in the FPGA and improving the accuracy of measuring the pulse frequency of the signal to be measured.

Description

Method, device, equipment and medium for determining pulse frequency

Technical Field

The invention relates to the technical field of ultrafast lasers, in particular to a method, a device, equipment and a medium for determining pulse frequency.

Background

In the working process of the ultrafast laser, whether the seed source is normal needs to be detected in real time, and a commonly used detection method is to measure whether the output frequency of the seed source is normal, so that the frequency of the seed source needs to be accurately and stably measured.

In the prior art, two groups of counters are adopted for counting simultaneously, and one group of counters is triggered by a relatively stable clock and records a period of time as reference time. The other group of counters is triggered by using the frequency to be measured as a clock, and the number of rising edges, namely the number of pulse periods, of the counters in a period of time is calculated. And then calculating the frequency of the signal to be measured through a formula.

However, the signal to be measured is used as the trigger clock of the second set of counters, and the clock is unstable, because the signal to be measured is an optical signal sent by the seed source, and a burr is very easily generated in the conversion and transmission process by using the optical sensor to convert the signal to be measured into an electrical signal.

Disclosure of Invention

The invention provides a method, a device, equipment and a medium for determining a pulse frequency, which are used for solving the problem that an internal counter of an FPGA (field programmable gate array) is abnormal due to burrs of a signal to be measured, so that the accuracy of measuring the frequency of the signal to be measured is improved.

According to an aspect of the present invention, there is provided a method of determining a pulse frequency, including:

acquiring the clock frequency of a reference clock;

counting a first count value of the reference clock and a second count value of a signal to be detected within a set time length;

and determining the pulse frequency of the signal to be detected according to the clock frequency, the first counting value and the second counting value.

According to another aspect of the present invention, there is provided a pulse frequency determination apparatus, including:

the clock frequency acquisition module is used for acquiring the clock frequency of the reference clock;

the counting value counting module is used for counting a first counting value of the reference clock and a second counting value of the signal to be detected within a set time length;

and the pulse frequency determining module is used for determining the pulse frequency of the signal to be detected according to the clock frequency, the first counting value and the second counting value.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the method of determining a pulse frequency according to any of the embodiments of the invention.

According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the method for determining a pulse frequency according to any one of the embodiments of the present invention when the computer instructions are executed.

According to the technical scheme of the embodiment of the invention, the clock frequency of the reference clock is obtained; counting a first count value of the reference clock and a second count value of a signal to be detected within a set time length; and determining the pulse frequency of the signal to be detected according to the clock frequency, the first counting value and the second counting value. The embodiment of the invention triggers two counters to count through one reference clock to obtain two groups of counting values, and simultaneously determines the pulse frequency of the signal to be measured by combining the clock frequency of the reference clock, thereby solving the problem of abnormal data of the counter in the FPGA and improving the accuracy of measuring the frequency of the signal to be measured.

It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a method for determining a pulse frequency according to an embodiment of the present invention;

fig. 2 is a schematic diagram illustrating an implementation of beating a signal to be tested by using a reference clock according to an embodiment of the present invention;

fig. 3 is a schematic flowchart of an implementation of a method for determining a pulse frequency according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an apparatus for determining a pulse frequency according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of an electronic device implementing a method for determining a pulse frequency according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a flowchart of a method for determining a pulse frequency according to an embodiment of the present invention, where this embodiment is applicable to a case of determining a pulse frequency of a signal to be measured, and the method may be executed by a pulse frequency determining apparatus, and may be generally integrated in a device having a function of determining a pulse frequency, where the device may be an electronic device such as a server, a mobile terminal, or a server cluster. As shown in fig. 1, the method specifically includes the following steps: as shown in fig. 1, the method includes:

and S110, acquiring the clock frequency of the reference clock.

The clock frequency is used for describing the number of pulses generated by the periodic pulse signal in unit time. The reference clock can be selected according to the user's requirement, for example, it can be a clock signal generated by a quartz crystal oscillator, and the reference clock is a stable clock source.

And S120, counting a first count value of the reference clock in the set duration and a second count value of the signal to be detected.

The first count value and the second count value are count values obtained by simultaneously counting two groups of counters, and trigger clocks of the two groups of counters adopt stable reference clocks. The first count value may be a value at which the first set of counters count the number of cycles required within a set time period. The second count value may be a value obtained by counting the number of rising edges of the signal to be measured in the set time duration by the second group of counters. Of course, each rising edge of the signal to be measured can be understood as a pulse period. The set time length may be adjusted according to the required accuracy of the measurement frequency, and the embodiment of the present invention is not limited, and may be, for example, 1 millisecond. For example, if the set time duration is 1 ms and the reference clock frequency is 100 mhz, the first set of counters needs to count 100000 cycles.

Specifically, the first group of counters and the second group of counters count simultaneously, the first group of counters continuously count until a maximum count value of a set time length is reached, a first count value (maximum count value) of the reference clock is counted, and meanwhile, a value counted by the second group of counters for the number of rising edges of the signal to be measured is counted.

In the embodiment, the stable reference clock is used as the counter trigger clock, so that the problem of unstable signals to be detected in the existing scheme is solved, the abnormal condition of the counter of the signals to be detected can be prevented, and the measurement result of the pulse frequency can be more stable and accurate.

Optionally, counting a second count value of the signal to be detected within the set time duration includes:

and counting the number of rising edges of the signal to be detected in the set time length based on the reference clock to obtain a second count value.

Here, the rising edge refers to the moment (time) at which the digital level changes from the low level (digital "0") to the high level (digital "1").

According to the embodiment of the invention, the signal to be detected within the set time can be beaten for two beats through the stable reference clock, and the rising edge of the signal to be detected can be judged through beating for two beats, so that the number of the rising edges of the signal to be detected can be counted to obtain the second counting value.

Optionally, counting the number of rising edges of the signal to be measured in the set time length based on the reference clock to obtain a second count value, including:

shooting a signal to be detected based on a reference clock to obtain a first shooting signal;

beating the first beating signal based on the reference clock to obtain a second beating signal;

and counting the number of rising edges of the signal to be detected in the set time length according to the first beating signal and the second beating signal to obtain a second count value.

The first beat signal may be a signal obtained by sampling a signal to be detected with a reference clock. The second beat signal may be a signal obtained by sampling the first beat signal with a reference clock.

Specifically, the signal point at the previous moment of the signal to be measured is triggered to be sampled on the rising edge of the reference clock, after the sampling is completed, a first beat signal is obtained, the signal point at the previous moment of the first beat signal is triggered to be sampled on the rising edge of the reference clock, after the sampling is completed, a second beat signal is obtained, the first beat signal and the second beat signal are used together as a condition for judging the rising edge of the signal to be measured, and a value for counting the number of the rising edges of the signal to be measured in a set time length is used as a second count value.

In this embodiment, since sampling is triggered on the rising edge of the reference clock and sampling is not performed during the non-rising edge, there may be an error of one period at each of the head and tail ends, and there are two periods in total. The larger the first count value is, the smaller the influence of the error of two cycles is. Therefore, if the error is to be reduced, the clock frequency of the reference clock can be increased, i.e., the error time is reduced. It is also possible to increase the set time period, i.e., to decrease the proportion of the error.

Optionally, the step of counting the number of rising edges of the signal to be measured in the set duration according to the first beat signal and the second beat signal to obtain a second count value includes:

within a set time length, when a signal of a reference clock is at a rising edge, level values of a first beating signal and a second beating signal are obtained;

when the first tapping signal is at a high level and the second tapping signal is at a low level, the second count value is incremented by 1.

Specifically, within a set time length, when a signal of the reference clock is at a rising edge, level values of the first tapping signal and the second tapping signal are obtained to judge the rising edge of the signal to be detected, when the first tapping signal is at a high level and the second tapping signal is at a low level, the rising edge of the signal to be detected is judged, and an operation of adding 1 to the second count value is performed.

And S130, determining the pulse frequency of the signal to be measured according to the clock frequency, the first counting value and the second counting value.

Wherein the pulse frequency is the number of times of effective discharge occurring in the discharge gap in a unit time.

Specifically, the first count value is a value obtained by counting the number of required cycles in the set time period by the first group of counters, and the set time period can be calculated by the following formula: the first count value is referenced to the clock period. The second count value represents a pulse period generated by the signal to be measured within the set time length, and one pulse period can be calculated by the following formula: the duration/second count value is set. Therefore, the pulse frequency of the signal to be measured can be calculated by the following formula: the second count value/the set duration can be obtained as the pulse frequency, i.e., the second count value/(the first count value × the reference clock period), and the pulse frequency of the signal to be measured can be determined according to the fact that the reference clock frequency is equal to 1/the reference clock period.

Optionally, determining the pulse frequency of the signal to be measured according to the clock frequency, the first count value and the second count value and calculating according to the following formula:

pulse frequency (second count value x clock frequency)/first count value.

It should be noted that the second count value in the pulse frequency of the signal to be measured is a value that is stored when the first count value reaches the maximum first count value of the set duration. For example, if the set time is 1 ms and the reference clock period is 10 ns, the maximum value of the first count value is: 100000-1. The first count value in the pulse frequency of the signal to be measured is the maximum first count value.

According to the technical scheme of the embodiment of the invention, the clock frequency of the reference clock is obtained; counting a first count value of a reference clock and a second count value of a signal to be detected in a set time length; and determining the pulse frequency of the signal to be measured according to the clock frequency, the first counting value and the second counting value. The embodiment of the invention triggers two counters to count through one reference clock to obtain two groups of counting values, and determines the pulse frequency of the signal to be measured by combining the clock frequency of the reference clock, thereby solving the problem of abnormal data of the counter in the FPGA and improving the accuracy of measuring the frequency of the signal to be measured.

Fig. 2 is a schematic diagram illustrating an implementation of beating a signal to be measured by using a reference clock according to an embodiment of the present invention. As shown in fig. 2, the reference clock is a stable clock source, the stable reference clock is used to beat the signal to be detected for two beats, the first beating signal is a signal obtained by sampling the signal to be detected by using the reference clock, the second beating signal is a signal obtained by sampling the first beating signal by using the reference clock, the dotted line represents a rising edge of the corresponding reference clock, and the sampling of the signal to be detected is triggered at the rising edge of the reference clock. The first group of counters record the number of cycles of the reference clock in a set time length, and the second group of counters record the number of rising edges of the signal to be tested, wherein when the first beating signal is at a high level and the second beating signal is at a low level, the rising edges of the signal to be tested are judged.

Fig. 3 is a schematic flowchart of an implementation of a method for determining a pulse frequency according to an embodiment of the present invention. As shown in fig. 3, the first group of counters and the second group of counters count simultaneously, and first, the first group of counters continuously count, for example, the first group of counters perform an operation of adding 1, and when the first group of counters count to a maximum first count value of a set duration, the first group of counters clear the first count value. When detecting that beat 1 is high level and beat 2 is low level, namely the signal to be measured has rising edge, the second count value is accumulated by 1, when the first count value reaches the maximum value, the second count value at this time is stored and can be recorded as data, and then the second count value is also cleared by the second group of counters. Thereafter, the first group of counters counts again, and the value of the data is updated when the first count value reaches the maximum first count value. It should be noted that the trigger clocks of all counters are reference clocks, and the pulse frequency of the signal to be measured can be obtained according to the following formula: the pulse frequency of the signal to be measured is data and the reference clock frequency/the maximum first counting value.

Fig. 4 is a schematic structural diagram of a pulse frequency determining apparatus according to an embodiment of the present invention.

As shown in fig. 4, the apparatus includes:

a clock frequency obtaining module 210, configured to obtain a clock frequency of a reference clock;

a count value counting module 220, configured to count a first count value of the reference clock and a second count value of the signal to be detected within a set time duration;

a pulse frequency determining module 230, configured to determine a pulse frequency of the signal to be measured according to the clock frequency, the first count value, and the second count value.

Optionally, the count value statistic module 220 includes:

and the second count value obtaining unit is used for counting the number of rising edges of the signal to be measured in the set time length based on the reference clock to obtain a second count value.

Optionally, the second count value obtaining unit includes:

the first beat signal obtaining subunit is configured to beat the signal to be detected based on the reference clock to obtain a first beat signal;

a second beat signal obtaining subunit, configured to perform beating on the first beat signal based on the reference clock to obtain a second beat signal;

and the second count value obtaining subunit is used for counting the number of rising edges of the signal to be detected in the set time length according to the first beat signal and the second beat signal to obtain a second count value.

Optionally, the second count value obtaining subunit is further configured to:

within the set time length, when a signal of the reference clock is at a rising edge, acquiring level values of the first beating signal and the second beating signal;

Optionally, the pulse frequency determining module 230 is further configured to: calculated according to the following formula:

pulse frequency (second count value x clock frequency)/first count value.

The device for determining the pulse frequency provided by the embodiment of the invention can execute the method for determining the pulse frequency provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.

FIG. 5 illustrates a schematic diagram of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 5, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM)12, a Random Access Memory (RAM)13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM)12 or the computer program loaded from a storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. Processor 11 performs the various methods and processes described above, such as the determination of the method pulse frequency.

In some embodiments, the determination of the pulse frequency of the method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the determination of the pulse frequency of the method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the determination of the method pulse frequency by any other suitable means (e.g. by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user may provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for determining a pulse frequency, comprising:

acquiring the clock frequency of a reference clock;

2. The method of claim 1, wherein counting the second count value of the signal to be tested within the set time period comprises:

3. The method of claim 2, wherein counting the number of rising edges of the signal to be measured within a set time period based on the reference clock to obtain a second count value comprises:

beating the signal to be detected based on the reference clock to obtain a first beating signal;

and counting the number of rising edges of the signal to be detected in a set time length according to the first beating signal and the second beating signal to obtain a second counting value.

4. The method according to claim 3, wherein counting the number of rising edges of the signal to be measured within a set time period according to the first beat signal and the second beat signal to obtain a second count value, comprises:

5. The method of claim 1, wherein determining the pulse frequency of the signal under test based on the clock frequency, the first count value, and the second count value is calculated according to the following equation:

pulse frequency (second count value x clock frequency)/first count value.

6. An apparatus for determining a pulse frequency, comprising:

7. The apparatus of claim 6, wherein the count value statistic module comprises:

8. The apparatus according to claim 7, wherein the second count value obtaining unit includes:

9. An electronic device, characterized in that the electronic device comprises:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of determining a pulse frequency of any one of claims 1-5.

10. A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions for causing a processor to implement the method for determining a pulse frequency according to any one of claims 1 to 5 when executed.