CN115412469B - Tolerance detection method, computer device and readable storage medium - Google Patents
Tolerance detection method, computer device and readable storage medium Download PDFInfo
- Publication number
- CN115412469B CN115412469B CN202211352701.2A CN202211352701A CN115412469B CN 115412469 B CN115412469 B CN 115412469B CN 202211352701 A CN202211352701 A CN 202211352701A CN 115412469 B CN115412469 B CN 115412469B
- Authority
- CN
- China
- Prior art keywords
- baud rate
- pulse width
- tolerance
- detection
- determining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
- H04L43/0894—Packet rate
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Communication Control (AREA)
Abstract
The application discloses a tolerance detection method, a system computer device and a readable storage medium, wherein the tolerance detection method comprises the following steps: acquiring a current clock frequency, a sampling mode and a preset baud rate detection table; determining a reference baud rate in the baud rate detection table in response to a tolerance detection operation; calculating a baud rate register value according to the current clock frequency, the sampling mode and the reference baud rate; outputting a baud rate to be tested according to the baud rate register value, and determining a pulse width corresponding to the baud rate to be tested as a reference pulse width; and outputting the tolerance range of the baud rate to be detected based on the reference pulse width, and recording the tolerance range into the baud rate detection table. The tolerance detection scheme provided by the application improves the reliability of tolerance detection.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a tolerance detection method, a computer device, and a readable storage medium.
Background
With the continuous development and improvement of science and technology, the application scenarios of Micro Control Units (MCUs) are becoming more and more abundant, wherein Universal Asynchronous Receiver/Transmitter (UART) plays a very important role in the application of the MCU chip. In many UART application scenarios, accurate UART baud rates are a fundamental requirement for various application modes.
At present, the UART baud rate in the MCU is detected by receiving data sent by another UART, and during the actual sending process, the sent baud rate is continuously changed to determine the bit error rate currently received by the UART, thereby determining the tolerance of the UART.
Disclosure of Invention
In view of the above technical problems, the present application provides a tolerance detection method, a computer device, and a readable storage medium, which improve reliability of tolerance detection.
In order to solve the above technical problem, the present application provides a tolerance detection method, including:
acquiring a current clock frequency, a sampling mode and a preset baud rate detection table;
determining a reference baud rate in the baud rate detection table in response to a tolerance detection operation;
calculating a baud rate register value according to the current clock frequency, the sampling mode and the reference baud rate;
outputting a baud rate to be tested according to the baud rate register value, and determining a pulse width corresponding to the baud rate to be tested as a reference pulse width;
and outputting the tolerance range of the baud rate to be detected based on the reference pulse width, and recording the tolerance range into the baud rate detection table.
Optionally, in some embodiments of the present application, the outputting the tolerance range of the baud rate to be measured based on the reference pulse width includes:
determining a current word length mode;
and outputting the tolerance range of the baud rate to be tested according to the current word length mode and the reference pulse width.
Optionally, in some embodiments of the present application, the outputting the tolerance range of the baud rate to be measured according to the current word length mode and the reference pulse width includes:
determining an expected value corresponding to the current word length mode;
acquiring baud rate data of the universal asynchronous transceiver under the baud rate to be detected;
and detecting the difference between the expected value and the baud rate data, and outputting the tolerance range of the baud rate to be detected according to the detection result, the upper limit mark and the lower limit mark.
Optionally, in some embodiments of the application, the outputting the tolerance range of the baud rate to be detected according to the detection result, the upper limit flag, and the lower limit flag includes:
when the baud rate data is detected not to be an expected value and the lower limit flag is not set, determining the current pulse width as a first pulse width, and calculating the lower limit baud rate according to the first pulse width;
and when the baud rate data is detected not to be an expected value, the lower limit flag is set, and the upper limit flag is not set, determining the current pulse width as a second pulse width, and calculating the upper limit baud rate according to the second pulse width.
Optionally, in some embodiments of the present application, the method further includes:
when the baud rate data is detected to be an expected value and the lower limit mark or the upper limit mark is not set, sending a pulse signal to a waveform generator;
receiving a square wave returned by the waveform generator according to the pulse signal;
and determining the growth direction of the current square wave according to the square wave.
Optionally, in some embodiments of the present application, before the obtaining of the current clock frequency, the sampling mode, and the preset baud rate detection table, the method further includes:
outputting an initial baud rate table;
acquiring a preset reference clock frequency and baud rate calculation formula;
calculating a reference baud rate according to the baud rate calculation formula and the reference clock frequency;
and updating the initial baud rate table based on the reference baud rate to obtain a baud rate detection table.
Optionally, in some embodiments of the present application, the determining a reference baud rate in the baud rate detection table in response to the tolerance detection operation includes:
responding to the parameter adjustment operation aiming at the baud rate detection table, and adjusting the baud rate in the baud rate detection table;
and responding to the selection operation aiming at the adjusted baud rate detection table, and determining the baud rate corresponding to the selection operation as the reference baud rate.
In a second aspect, the present application further provides a tolerance detection method, including:
triggering to enter a tolerance detection mode in response to a tolerance detection operation;
detecting the receiving tolerance of the baud rate corresponding to a preset baud rate detection table in the tolerance detection mode;
and displaying the tolerance detection result.
The present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method as described above when executing the computer program.
The present application also provides a computer storage medium having a computer program stored thereon, which, when being executed by a processor, carries out the steps of the method as described above.
As described above, the present application provides a tolerance detection method, a computer device, and a readable storage medium, after acquiring a current clock frequency, a sampling mode, and a preset baud rate detection table, responding to a tolerance detection operation, determining a reference baud rate in the baud rate detection table, then calculating a baud rate register value according to the current clock frequency, the sampling mode, and the reference baud rate, then outputting a baud rate to be detected according to the baud rate register value, determining a pulse width corresponding to the baud rate to be detected as a reference pulse width, and finally outputting a tolerance range of the baud rate to be detected based on the reference pulse width, and recording the tolerance range into the baud rate detection table. In the tolerance detection scheme provided by the application, a baud rate register value is calculated based on a reference baud rate in a preset baud rate detection table, then the baud rate to be detected is output through the calculated baud rate register value, finally, a tolerance range of the baud rate to be detected is output through a pulse width corresponding to the baud rate to be detected, and the tolerance range is recorded by using the baud rate detection table, so that the situation that the UART receives data and received data which are repeatedly compared in a tolerance calculation process can be avoided, the receiving tolerance time of the UART is saved, the UART receiving tolerance detection function is designed in the chip, the interference of external factors can be avoided, and the reliability of tolerance detection is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a tolerance detection apparatus provided herein;
FIG. 2 is a schematic diagram of a baud rate detection table provided in the present application;
fig. 3 is a schematic structural diagram of a baud rate calculation unit provided in the present application;
FIG. 4 is a schematic diagram of a waveform generator provided herein;
FIG. 5 is a schematic diagram of a data checking unit provided in the present application;
FIG. 6 is a schematic flow chart of a tolerance detection method provided herein;
fig. 7 is another schematic flow chart corresponding to the tolerance detection method provided in the present application.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings. With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of a claim "comprising a" 8230a "\8230means" does not exclude the presence of additional identical elements in the process, method, article or apparatus in which the element is incorporated, and further, similarly named components, features, elements in different embodiments of the application may have the same meaning or may have different meanings, the specific meaning of which should be determined by its interpretation in the specific embodiment or by further combination with the context of the specific embodiment.
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning in themselves. Thus, "module", "component" or "unit" may be used mixedly.
The following embodiments related to the present application are specifically described, and it should be noted that the order of description of the embodiments in the present application is not limited to the order of priority of the embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a tolerance detection apparatus provided in the present application. The application provides a tolerance detection device 1, this tolerance detection device 1 is integrated in the chip, and it includes baud rate computational element, waveform generator, universal Asynchronous Receiver Transmitter (UART) and data detection unit, and in this application, has increased a baud rate detection table in the chip inside, and this baud rate detection table has stored the last lower limit value of the baud rate of can predetermineeing programmable commonly used and waiting to write back the baud rate.
The baud rate calculation unit can acquire the current UART working clock frequency and an oversampling mode in UART register configuration, read an element to be detected in a baud rate detection table, and set a UART frequency divider according to the baud rate of the UART;
the waveform generator records the baud rate of the current UART, calculates the pulse width under the baud rate, sets the pulse width as a reference pulse width, simulates square waves with the duty ratio of 50% according to the pulse width, and is connected to a data receiving pin of the UART inside the MCU.
The data checking unit can acquire a word length bit of the current UART, and judge whether the value of a DR register of the UART is an expected value or not, if the judgment result is true, the data checking unit sends an instruction to the waveform generator, the waveform generator increases a clock period of the waveform generator on the basis of the reference pulse width, the data checking unit repeatedly checks whether the data is the expected value or not, once an unexpected value appears, the data checking unit sends a feedback signal to the baud rate calculating unit to indicate that the lower limit of the baud rate is acquired, the baud rate calculating unit records a baud rate lower limit completion flag, and calculates the lower limit of the baud rate at the moment and writes the baud rate back to the list structure; then the waveform generator reduces a clock period of the waveform generator on the basis of the reference pulse width, and repeats the steps until the data checking unit sends a feedback signal to the baud rate calculating unit to indicate that the upper limit of the baud rate is acquired, the baud rate calculating unit records a baud rate upper limit completion mark and calculates the upper limit baud rate at the moment and writes the upper limit baud rate back to the list structure; after the writing is finished, the baud rate calculation unit automatically acquires the next element to be tested in the list until the whole list is traversed.
Further, please refer to fig. 2, fig. 2 is a schematic structural diagram of the baud rate detection table provided in the present application, the baud rate detection table is a readable and writable list, each list element is an array, and includes a baud rate Buad0 to be detected, a baud rate lower limit value Buad0_ Down, and a baud rate upper limit value Buad0_ Up; the length of the baud rate detection table and the baud rate to be detected are controlled by the baud rate calculation unit, and after UART is enabled, the baud rate is calculatedUART (universal asynchronous receiver/transmitter) with unit acquiring working clock frequency clk And after the integer division operation is carried out on the reference frequency 1MHz, the product of the integer division operation and the Baud rate reference value Baud _ ref is calculated to obtain the Baud rate Buadrate, namely, the formula is adopted for calculation:
。
therefore, initialization of the default value of the baud rate to be tested is completed, for example, the initialization setting of the default value of the baud rate to be tested when the UART operating clock is 8M is shown in table 1, and the baud rate to be tested can be set and changed by a tester.
TABLE 1
Referring to fig. 3, fig. 3 is a schematic structural diagram of the baud rate calculating unit provided in the present application, after the UART reception tolerance checking mode is set to be turned on, the baud rate calculating unit automatically obtains baud rate elements to be measured in the baud rate list and loads the baud rate elements into the operation module, the operation module obtains a current UART clock and an oversampling mode set by the UART to automatically calculate a UART _ DIV value (register frequency division value), and a calculation formula is as follows:
where OVER8 denotes the oversampling pattern (1: representing 8 times oversampling 0: representing 16 times oversampling), F CLK Indicating the UART clock and BaudRate the BaudRate rate to be measured. And writing the baud rate integer part and the baud rate decimal part into corresponding positions of the register according to the calculation result in a UART oversampling mode.
The baud rate calculation unit receives the signal from the data check unit, sets the lower limit flag and the upper limit flag to obtain the current pulse width from the waveform generator, calculates the corresponding lower limit baud rate and the upper limit baud rate by the operation module, and writes back the lower limit baud rate and the upper limit baud rate corresponding to the baud rate detection table respectively.
In the formula, S represents the current pulse width of the waveform generator, and Baud represents the lower limit value or the upper limit value of the Baud rate obtained by calculation.
The waveform generator sets the increasing direction of the pulse width according to the lower limit flag and the upper limit flag.
TABLE 2
Referring to fig. 4, fig. 4 is a schematic structural diagram of a waveform generator 20 according to the present invention, which uses a standard high-speed clock as a time base for waveform generation, wherein the standard high-speed clock is required to satisfy a multiple of the UART oversampling mode, for example, the standard high-speed clock is required to generate a pulse width satisfying at least 8 times of the standard high-speed clock period in the 8-fold oversampling mode of the UART.
The pulse width operation module obtains the baud rate to be measured of the baud rate calculation unit, calculates the pulse width under the baud rate, sets the pulse width as a reference pulse width, and sets the increasing direction of the pulse width according to the indication of the baud rate calculation unit. The pulse width operation module receives the pulse width increasing signal of the data checking unit and increases one standard high-speed clock period each time based on the original pulse width.
The waveform generation module sets pulse width parameters according to the operation result of the pulse width operation module, generates square waves with the duty ratio of 50%, and outputs the square waves to a data receiving pin of the UART.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a data checking unit provided in the present application, where a non-empty state of a UART receive data register triggers a data checking unit to read the UART data register once. The data checking unit can automatically acquire the word length mode of the UART, check whether the UART data is an expected value according to the acquired word length mode, if the expected value indicates that the current baud rate is within the UART receiving tolerance, immediately send a pulse signal to the waveform generator and indicate that the pulse width continues to increase; if the current baud rate is not the expected value and is indicated to be out of the UART receiving tolerance, a pulse signal is immediately sent to the baud rate calculation unit to indicate that the lower limit or the upper limit of the baud rate is acquired.
TABLE 3
In the tolerance detection scheme provided by the application, a baud rate register value is calculated based on a reference baud rate in a preset baud rate detection table, then the baud rate to be detected is output through the baud rate register value, finally, a tolerance range of the baud rate to be detected is output through a pulse width corresponding to the baud rate to be detected, and the tolerance range is recorded by using the baud rate detection table, so that the situation that the UART receives data and received data which are repeatedly compared in a tolerance calculation process can be avoided, the receiving tolerance time of the UART is saved, the UART receiving tolerance detection function is designed in the chip, the interference of external factors can be avoided, and the reliability of tolerance detection is improved.
The following are detailed below. It should be noted that the description sequence of the following embodiments is not intended to limit the priority sequence of the embodiments.
A tolerance detection method, comprising: acquiring a current clock frequency, a sampling mode and a preset baud rate detection table; determining a reference baud rate in a baud rate detection table in response to a tolerance detection operation; calculating a baud rate register value according to the current clock frequency, the sampling mode and the reference baud rate; outputting a baud rate to be tested according to the baud rate register value, and determining the pulse width corresponding to the baud rate to be tested as a reference pulse width; and outputting the tolerance range of the baud rate to be detected based on the reference pulse width, and recording the tolerance range into a baud rate detection table.
Referring to fig. 6, fig. 6 is a schematic flowchart illustrating a tolerance detection method according to an embodiment of the present disclosure. The specific process of the number tolerance detection method may be as follows:
101. and acquiring the current clock frequency, the sampling mode and a preset baud rate detection table.
In the field of electronic communications, baud (Baud), i.e., modulation rate, refers to the rate at which a carrier is modulated by a valid data signal, i.e., the number of times the modulation state of the carrier changes per unit time. The baud rate is a measure of the number of transmitted symbols per unit time, and is a measure of the symbol transmission rate, which is expressed in terms of the number of times the carrier modulation state changes per unit time, i.e., the number of transmitted symbols per unit time.
In signal processing, oversampling refers to the process of sampling a signal at a frequency much higher than twice its bandwidth or its highest frequency. Generally meaning that the sampling frequency is higher than twice the highest frequency of the signal.
The tolerance detection operation may be triggered by an operation and maintenance person, or may be triggered by a microcontroller chip (Micro Control Unit, MCU), for example, the operation and maintenance person may trigger the tolerance detection operation through an upper computer system, or may trigger the tolerance detection operation within a set time period by the MCU, which may be specifically set according to actual conditions, and is not described herein.
The baud rate detection table may be pre-constructed, and after the tolerance detection operation is triggered, the preset baud rate detection table may be obtained, that is, optionally, in some embodiments, before the step "obtaining the current clock frequency, the sampling mode, and the preset baud rate detection table", the method may specifically include:
(11) Outputting an initial baud rate table;
(12) Acquiring a preset reference clock frequency and baud rate calculation formula;
(13) Calculating a reference baud rate according to a baud rate calculation formula and a reference clock frequency;
(14) And updating the initial baud rate table based on the reference baud rate to obtain a baud rate detection table.
Please refer to the foregoing embodiments for specific representation forms of the baud rate detection table and the baud rate calculation formula, which are not described herein again.
102. In response to the tolerance detection operation, a reference baud rate is determined in a baud rate detection table.
For example, specifically, the operation and maintenance personnel may manually select a reference baud rate in the baud rate detection table, and optionally, in some embodiments, when the reference baud rate is determined in the baud rate detection table, the operation and maintenance personnel may further manually adjust data in the baud rate detection table, that is, the step "responding to the tolerance detection operation, and determining the reference baud rate in the baud rate detection table" may specifically include:
(21) Responding to the parameter adjustment operation aiming at the baud rate detection table, and adjusting the baud rate in the baud rate detection table;
(22) And responding to the selection operation aiming at the adjusted baud rate detection table, and determining the baud rate corresponding to the selection operation as the reference baud rate.
103. And calculating the baud rate register value according to the current clock frequency, the sampling mode and the reference baud rate.
The baud rate register is used for configuring the baud rate, so that after the current clock frequency, the sampling mode and the reference baud rate are obtained, and the baud rate register value is calculated, the baud rate of the UART can be configured according to the baud rate register value.
104. And outputting the baud rate to be tested according to the baud rate register value, and determining the pulse width corresponding to the baud rate to be tested as the reference pulse width.
105. And outputting the tolerance range of the baud rate to be detected based on the reference pulse width, and recording the tolerance range into a baud rate detection table.
In serial communication, a certain error is allowed to exist in the baud rate, and when the error exceeds a certain range, a data communication error is generated, so that the tolerance range is kept in a preset range capable of normal communication, optionally, in some embodiments, the tolerance range of the baud rate to be measured may be output according to the current word length mode and the reference pulse width, that is, the step "outputting the tolerance range of the baud rate to be measured based on the reference pulse width" may specifically include:
(31) Determining a current word length mode;
(32) And outputting the tolerance range of the baud rate to be measured according to the current word length mode and the reference pulse width.
Computers use binary coding to represent numbers, characters, instructions, and other control information. When a computer stores, transmits or operates, a group of binary codes as a unit is called a word, and the number of bits of binary bits in a word is called a word length.
For example, specifically, an expected value corresponding to the current word length mode may be determined, and then, a difference between the baud rate data of the UART at the baud rate to be measured and the expected value is calculated, so as to determine a tolerance range corresponding to the baud rate to be measured, that is, optionally, in some embodiments, the step "outputting the tolerance range of the baud rate to be measured according to the current word length mode and the reference pulse width" may specifically include:
(41) Determining an expected value corresponding to the current word length mode;
(42) Acquiring baud rate data of the universal asynchronous transceiver under the baud rate to be detected;
(43) And detecting the difference between the expected value and the baud rate data, and outputting the tolerance range of the baud rate to be detected according to the detection result, the upper limit mark and the lower limit mark.
For example, after the baud rate to be measured is determined, the lower limit flag and the upper limit flag are initialized to be 0, the reference pulse width under the baud rate to be measured is calculated, and when the data check unit returns a judgment result to be true each time, a standard high-speed clock cycle is increased on the basis of the reference pulse width, and the increasing direction is determined by the states of the lower limit flag and the upper limit flag. It should be noted that, the data checking unit acquires UART word length mode information, automatically determines whether the received data is an expected value, returns a determination result to the pulse width operation module if the received data is the expected value, and returns a determination result to the baud rate calculation unit if the received data is the expected value, otherwise returns the determination result to the baud rate calculation unit to be false, that is, optionally, in some embodiments, the step "output the tolerance range of the baud rate to be measured according to the detection result, the upper limit flag, and the lower limit flag" may specifically include:
(51) When the baud rate data is detected not to be an expected value and the lower limit flag is not set, determining the current pulse width as a first pulse width, and calculating the lower limit baud rate according to the first pulse width;
(52) And when the baud rate data is detected not to be an expected value, the lower limit flag is set, and the upper limit flag is not set, determining the current pulse width as a second pulse width, and calculating the upper limit baud rate according to the second pulse width.
In some embodiments of the present application, the lower limit flag is set, i.e., the lower limit flag is set to 1, and the upper limit flag is set, i.e., the upper limit flag is set to 1.
It can be understood that the lower limit flag is not set, which indicates that the process of detecting the lower limit of the baud rate is currently in progress; when the upper limit flag is not set, the detection of the upper limit of the baud rate is currently performed.
For example, when the data check unit returns that the determination result is true each time, a standard high-speed clock cycle is further increased on the basis of the reference pulse width, and the increasing direction is determined by the states of the lower limit flag and the upper limit flag, that is, optionally, in some embodiments, the step "outputting the tolerance range of the baud rate to be measured according to the detection result, the upper limit flag, and the lower limit flag" may specifically include:
(61) When the baud rate data is detected to be an expected value and the lower limit mark or the upper limit mark is not set, sending a pulse signal to the waveform generator;
(62) Receiving a square wave returned by a waveform generator according to the pulse signal;
(63) And determining the growth direction of the current square wave according to the square wave.
When the data checking unit returns that the judgment result is true every time, a standard high-speed clock period is increased on the basis of the reference pulse width, after the waveform generating module receives the result of the pulse width operation module, a square wave with a duty ratio of 50% is generated, the 6 UART data receiving pin receives the square wave generated by the waveform generating module, and the UART waits for receiving a non-empty flag setting, namely, until the UART setting.
It should be noted that, in some embodiments of the present application, after determining the baud rate to be measured, it may be determined whether the length of the baud rate detection table is 0, and if the length of the baud rate detection table is not 0, the baud rate to be measured is obtained from the baud rate list, and the length of the baud rate list is automatically reduced by 1; when the length of the baud rate detection table is 0, the UART receiving tolerance is acquired, and therefore the tolerance detection process of the application is completed.
From the above, the present application provides a tolerance detection method, which includes obtaining a current clock frequency, a sampling mode and a preset baud rate detection table, responding to a tolerance detection operation, determining a reference baud rate in the baud rate detection table, then calculating a baud rate register value according to the current clock frequency, the sampling mode and the reference baud rate, then outputting a baud rate to be detected according to the baud rate register value, determining a pulse width corresponding to the baud rate to be detected as a reference pulse width, and finally outputting a tolerance range of the baud rate to be detected based on the reference pulse width, and recording the tolerance range into the baud rate detection table. In the tolerance detection scheme provided by the application, a baud rate register value is calculated based on a reference baud rate in a preset baud rate detection table, then the baud rate to be detected is output through the calculated baud rate register value, finally, a tolerance range of the baud rate to be detected is output through a pulse width corresponding to the baud rate to be detected, and the tolerance range is recorded by using the baud rate detection table, so that the situation that the UART receives data and received data which are repeatedly compared in a tolerance calculation process can be avoided, the receiving tolerance time of the UART is saved, the UART receiving tolerance detection function is designed in the chip, the interference of external factors can be avoided, and the reliability of tolerance detection is improved.
Referring to fig. 7, fig. 7 is another schematic flow chart of a tolerance detection method according to an embodiment of the present application. The specific process of the tolerance detection method can be as follows:
201. in response to a tolerance detection operation, triggering entry into a tolerance detection mode.
202. And detecting the receiving tolerance of the baud rate corresponding to a preset baud rate detection table in a tolerance detection mode.
203. And displaying the tolerance detection result.
For example, specifically, configuring the UART to use 8MHz as an operating clock, setting the UART to be in 16 times oversampling mode, setting the word length to be in 8-bit mode, measuring the receiving tolerance of the UART in this mode, it can be designed to generate a square wave with 50% duty cycle by TIM. The UART tolerance detection mode is started in response to tolerance detection operation triggered by operation and maintenance personnel, the baud rate calculation unit, the waveform generator and the data check unit can detect the receiving tolerance of the common baud rate corresponding to the baud rate detection table according to the current configuration of the UART, the result is written back to the baud rate detection table, the operation and maintenance personnel output the result to the upper computer for analysis, and the detection efficiency can be improved.
In view of the above, the present application provides a tolerance detection method, which responds to a tolerance detection operation, triggers entering a tolerance detection mode, detects a reception tolerance of a baud rate corresponding to a preset baud rate detection table in the tolerance detection mode, and finally displays a tolerance detection result. In the tolerance detection scheme that this application provided, fortune dimension personnel can detect UART's receiving tolerance fast through triggering tolerance detection operation to, can export the result to the host computer and carry out the analysis, thereby when guaranteeing the reliability of tolerance testing result, improve detection efficiency.
It will be understood by those skilled in the art that all or part of the steps of the methods of the above embodiments may be performed by instructions or by associated hardware controlled by the instructions, which may be stored in a computer readable storage medium and loaded and executed by a processor.
To this end, the present application provides a readable storage medium, in which a plurality of instructions are stored, and the instructions can be loaded by a processor to execute the steps in any one of the tolerance detection methods provided by the embodiments of the present application.
The above operations can be implemented in the foregoing embodiments, and are not described in detail herein.
Wherein the readable storage medium may include: read Only Memory (ROM), random Access Memory (RAM), magnetic or optical disks, and the like.
Since the instructions stored in the readable storage medium can execute the steps in any data detection method provided in the embodiments of the present application, the beneficial effects that can be achieved by any tolerance detection method provided in the embodiments of the present application can be achieved, which are detailed in the foregoing embodiments and will not be described herein again.
Embodiments of the present application further provide a chip, which includes a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device in which the chip is installed executes the method in the above various possible embodiments.
It is to be understood that the foregoing scenarios are only examples, and do not constitute a limitation on application scenarios of the technical solutions provided in the embodiments of the present application, and the technical solutions of the present application may also be applied to other scenarios. For example, as can be known by those skilled in the art, with the evolution of system architecture and the emergence of new service scenarios, the technical solution provided in the embodiments of the present application is also applicable to similar technical problems.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device in the embodiment of the application can be merged, divided and deleted according to actual needs.
In the present application, the same or similar descriptions of terms, technical solutions and/or application scenarios will generally be described in detail only when they occur for the first time, and when they occur repeatedly later, they will not be repeated again for brevity, and in understanding the technical solutions and the like of the present application, reference may be made to the related detailed descriptions and the like before the same or similar descriptions of terms, technical solutions and/or application scenarios and the like which are not described in detail later.
In the present application, each embodiment is described with emphasis, and reference may be made to the description of other embodiments for parts that are not described or illustrated in any embodiment.
All possible combinations of the technical features in the embodiments are not described in the present application for the sake of brevity, but should be considered as the scope of the present application as long as there is no contradiction between the combinations of the technical features.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, memory Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.
The above embodiments describe a tolerance detection method, a tolerance detection device, and a storage medium provided in the embodiments of the present application in detail, and a specific example is applied in the present application to explain the principle and the implementation of the present invention, and the description of the above embodiments is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (9)
1. A tolerance detection method, comprising:
acquiring a current clock frequency, a sampling mode and a preset baud rate detection table;
determining a reference baud rate in the baud rate detection table in response to a tolerance detection operation;
calculating a baud rate register value according to the current clock frequency, the sampling mode and the reference baud rate;
outputting a baud rate to be tested according to the baud rate register value, and determining a pulse width corresponding to the baud rate to be tested as a reference pulse width;
and outputting the tolerance range of the baud rate to be detected based on the reference pulse width, and recording the tolerance range into the baud rate detection table.
2. The method of claim 1, wherein outputting the tolerance range for the baud rate under test based on the reference pulse width comprises:
determining a current word length mode;
and outputting the tolerance range of the baud rate to be tested according to the current word length mode and the reference pulse width.
3. The method of claim 2, wherein outputting the tolerance range of the baud rate to be measured according to the current word length mode and the reference pulse width comprises:
determining an expected value corresponding to the current word length mode;
acquiring baud rate data of the universal asynchronous transceiver under the baud rate to be detected;
and detecting the difference between the expected value and the baud rate data, and outputting the tolerance range of the baud rate to be detected according to the detection result, the upper limit mark and the lower limit mark.
4. The method according to claim 3, wherein the outputting the tolerance range of the baud rate to be measured according to the detection result, the upper limit flag and the lower limit flag comprises:
when the baud rate data is detected not to be an expected value and the lower limit flag is not set, determining the current pulse width as a first pulse width, and calculating a lower limit baud rate according to the first pulse width;
and when the baud rate data is detected not to be an expected value, the lower limit flag is set, and the upper limit flag is not set, determining the current pulse width as a second pulse width, and calculating the upper limit baud rate according to the second pulse width.
5. The method of claim 4, further comprising:
when the baud rate data is detected to be an expected value and the lower limit mark or the upper limit mark is not set, sending a pulse signal to a waveform generator;
receiving a square wave returned by the waveform generator according to the pulse signal;
and determining the growth direction of the current square wave according to the square wave.
6. The method according to any one of claims 1 to 5, wherein before obtaining the current clock frequency, the sampling pattern and the preset baud rate detection table, the method further comprises:
outputting an initial baud rate table;
acquiring a preset reference clock frequency and baud rate calculation formula;
calculating a reference baud rate according to the baud rate calculation formula and the reference clock frequency;
and updating the initial baud rate table based on the reference baud rate to obtain a baud rate detection table.
7. The method of any of claims 1 to 5, wherein determining a reference baud rate in a baud rate detection table in response to the tolerance detection operation comprises:
responding to the parameter adjustment operation aiming at the baud rate detection table, and adjusting the baud rate in the baud rate detection table;
and responding to the selection operation aiming at the adjusted baud rate detection table, and determining the baud rate corresponding to the selection operation as the reference baud rate.
8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the tolerance detection method according to any one of claims 1 to 7 when executing the computer program.
9. A readable storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps of the tolerance detection method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211352701.2A CN115412469B (en) | 2022-11-01 | 2022-11-01 | Tolerance detection method, computer device and readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211352701.2A CN115412469B (en) | 2022-11-01 | 2022-11-01 | Tolerance detection method, computer device and readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115412469A CN115412469A (en) | 2022-11-29 |
| CN115412469B true CN115412469B (en) | 2023-03-24 |
Family
ID=84168527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211352701.2A Active CN115412469B (en) | 2022-11-01 | 2022-11-01 | Tolerance detection method, computer device and readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115412469B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116742763B (en) * | 2023-08-14 | 2023-11-17 | 苏州水芯电子科技有限公司 | Fast charging protocol chip, method executed by fast charging protocol chip and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111800249A (en) * | 2020-07-06 | 2020-10-20 | 山东管理学院 | Method and system for improving error tolerance range of baud rate of serial communication |
| CN114623939A (en) * | 2022-04-13 | 2022-06-14 | 杭州奥创光子技术有限公司 | Method, device, equipment and medium for determining pulse frequency |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100525548B1 (en) * | 2000-12-29 | 2005-10-31 | 엘지전자 주식회사 | Baudrate Detection Circuit of Universal Asynchronous Receiver/Transmitter |
| JP2011234128A (en) * | 2010-04-27 | 2011-11-17 | Yazaki Corp | Baud rate detecting device for serial communication, baud rate correcting device for serial communication, and baud rate detecting method for serial communication |
| CN111459727B (en) * | 2019-12-25 | 2023-07-14 | 山东有人物联网股份有限公司 | Intelligent automatic test system and method for serial port baud rate maximum error-free tolerance range |
| CN114006842B (en) * | 2021-10-29 | 2023-03-10 | 北京中科昊芯科技有限公司 | Method, device, equipment and medium for detecting baud rate |
-
2022
- 2022-11-01 CN CN202211352701.2A patent/CN115412469B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111800249A (en) * | 2020-07-06 | 2020-10-20 | 山东管理学院 | Method and system for improving error tolerance range of baud rate of serial communication |
| CN114623939A (en) * | 2022-04-13 | 2022-06-14 | 杭州奥创光子技术有限公司 | Method, device, equipment and medium for determining pulse frequency |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115412469A (en) | 2022-11-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101729872B1 (en) | Training for mapping swizzled data command/address signals | |
| CN115412469B (en) | Tolerance detection method, computer device and readable storage medium | |
| CN115547381B (en) | Gate signal generating circuit of data gate signal and signal generating method thereof | |
| US20100008237A1 (en) | Method for testing data packet transceiver using loop back packet generation | |
| CN104541174B (en) | Method, system and apparatus for evaluation of input/output buffer circuitry | |
| JP2001352350A (en) | Measurement system and method by statistic eye-diagram of continuous bit stream | |
| CN101583054A (en) | Method for realizing that optical interface supports multiple rate patterns by adopting optical module and device | |
| CN110543404A (en) | Server, hard disk lighting method and system and computer readable storage medium | |
| EP2700961B1 (en) | Test and measurement instrument with auto-sync for bit-error detection | |
| WO2018175558A1 (en) | Method and system for generating rfid labels using rfid encoder attachment | |
| CN112860495A (en) | Debugging method of I2C slave device, I2C master device and storage medium | |
| CN114039807B (en) | Baud rate self-adaption method, device, computer equipment and storage medium | |
| CN115562916A (en) | Method, device and medium for evaluating signal quality | |
| CN114443537A (en) | Method, device, equipment and medium for configuring parameters of PCIE signal sending terminal | |
| CN115328708A (en) | Parameter testing method and device for serial peripheral interface timing sequence | |
| CN103856263A (en) | Method and device for testing high-speed link | |
| CN1201517C (en) | Detection method of synchronous serial-data transmission | |
| KR101429257B1 (en) | Rate and timing generator in memory tester | |
| CN111796977A (en) | Multi-port UART function testing method based on test board | |
| KR101563123B1 (en) | Method for testing device under test | |
| KR101544967B1 (en) | Method for testing device under test | |
| CN117251322A (en) | Training device and method for positioning data eye diagram | |
| CN111817780B (en) | Time delay equalization method, device and system | |
| CN117330942B (en) | Chip debugging method and related device | |
| US20230410929A1 (en) | Memory chip test method and apparatus, medium, and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |