CN117784569A

CN117784569A - Time synchronization precision testing method

Info

Publication number: CN117784569A
Application number: CN202311800068.3A
Authority: CN
Inventors: 秦晨; 田磊; 杨志乾; 刘欢
Original assignee: Shanghai Yingheng Electronic Co ltd
Current assignee: Shanghai Yingheng Electronic Co ltd
Priority date: 2023-12-25
Filing date: 2023-12-25
Publication date: 2024-03-29

Abstract

The invention discloses a time synchronization precision testing method. The method is applied to an upper computer of a time synchronization precision testing system, and pulse signals are transmitted according to a preset period by triggering a signal generator in the system; acquiring different receiving times of the MCU chip and each SOC chip in the system on the same pulse signal and different receiving times of the same SOC chip on two adjacent pulse signals; based on different receiving time of the same pulse signal by the MCU chip and each SOC chip, testing first time precision between the MCU chip and each SOC chip; and testing the second time precision in the same SOC chip based on different receiving time and preset period of the same SOC chip to two adjacent pulse signals. The technical scheme of the invention provides a novel method for testing time synchronization precision, which is used for measuring the time synchronization precision in the early stage of software development and finding out the problem of the time synchronization precision in advance.

Description

Time synchronization precision testing method

Technical Field

The invention relates to the technical field of time synchronization test, in particular to a time synchronization precision test method.

Background

In recent years, with the daily and new development of intelligent technology in the automobile industry, the intelligent driving field has a great breakthrough, from L1 to L2++, from semi-automatic driving to automatic driving under partial scenes, from the initial single constant-speed cruising function or lane keeping, to the functions of the adaptive cruising function, the automatic braking system, the lane auxiliary keeping system and the like in the current stage, which all require a domain controller to make a correct decision on the information of a sensor in a short time so as to cope with a complex driving scene, so that the time synchronization of acquiring the sensor between a reference chip and a decision chip in the domain controller becomes particularly important.

For time synchronization precision test measures, most of time delay performance angles from actual functions are adopted at present to measure time synchronization precision. In the later stage of software development and in the integrated test stage, if the problem of time synchronization precision occurs, a large amount of time is needed to check the software problem, and the project time schedule can be influenced. There is a need for a time synchronization accuracy measurement method that can discover a time synchronization accuracy problem in advance.

Disclosure of Invention

The invention provides a time synchronization precision testing method, which is used for measuring time synchronization precision in the early stage of software development and finding out the problem of the time synchronization precision in advance.

According to an aspect of the present invention, there is provided a time synchronization accuracy testing method applied to an upper computer of a time synchronization accuracy testing system, the time synchronization accuracy testing system further including a domain controller and a signal generator, the domain controller including a micro control unit MCU chip and at least one system-on-a-chip SOC chip, the method including:

triggering the signal generator to emit pulse signals according to a preset period;

different receiving times of the MCU chip and each SOC chip on the same pulse signal and different receiving times of the same SOC chip on two adjacent pulse signals are obtained;

based on different receiving time of the same pulse signal by the MCU chip and each SOC chip, testing first time precision between the MCU chip and each SOC chip by a preset inter-chip time precision algorithm;

and testing a second time precision in the same SOC chip through a time precision algorithm in the preset chip based on different receiving times of the same SOC chip on two adjacent pulse signals and the preset period.

According to another aspect of the present invention, there is provided a time synchronization accuracy testing apparatus integrated with an upper computer of a time synchronization accuracy testing system, the time synchronization accuracy testing system further including a domain controller and a signal generator, the domain controller including a micro control unit MCU chip and at least one system-on-chip SOC chip, the apparatus comprising:

the pulse signal emission triggering module is used for triggering the signal generator to emit pulse signals according to a preset period;

the pulse signal receiving time acquisition module is used for acquiring different receiving times of the MCU chip and each SOC chip on the same pulse signal and different receiving times of the same SOC chip on two adjacent pulse signals;

the inter-chip time precision testing module is used for testing the first time precision between the MCU chip and each SOC chip through a preset inter-chip time precision algorithm based on different receiving time of the MCU chip and each SOC chip to the same pulse signal;

and the on-chip time precision testing module is used for testing the second time precision in the same SOC chip through a preset on-chip time precision algorithm based on different receiving time of the same SOC chip to two adjacent pulse signals and the preset period.

According to another aspect of the present invention, there is provided a time synchronization accuracy testing system including: the system comprises a signal generator, a domain controller and an upper computer; the domain controller comprises an MCU chip and at least one SOC chip;

the signal generator is used for transmitting pulse signals according to a preset period;

the MCU chip and the SOC chip are used for receiving the pulse signals and sending the time information of the received pulse signals to the upper computer;

the upper computer is used for executing the time synchronization precision testing method according to any embodiment of the invention.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the time synchronization accuracy testing method of any one of the embodiments of the present invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the time synchronization accuracy testing method according to any one of the embodiments of the present invention when executed.

The technical scheme of the embodiment of the invention is applied to an upper computer of a time synchronization precision testing system, the time synchronization precision testing system also comprises a domain controller and a signal generator, wherein the domain controller comprises a Micro Control Unit (MCU) chip and at least one system-level system-on-chip (SOC) chip, and pulse signals are transmitted according to a preset period by triggering the signal generator; different receiving times of the MCU chip and each SOC chip on the same pulse signal and different receiving times of the same SOC chip on two adjacent pulse signals are obtained; based on different receiving time of the same pulse signal by the MCU chip and each SOC chip, testing first time precision between the MCU chip and each SOC chip by a preset inter-chip time precision algorithm; based on the different receiving time and the preset period of two adjacent pulse signals of the same SOC chip, a novel time synchronization precision testing method is provided by a technical means of testing the second time precision in the same SOC chip through a time precision algorithm in the preset chip, the time synchronization precision is measured in the early stage of software development, and the problem of the time synchronization precision is found in advance.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1a is a flowchart of a time synchronization accuracy testing method according to a first embodiment of the present invention;

FIG. 1b is a schematic diagram showing a pulse signal sending time and a chip recording a pulse signal receiving time according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a time synchronization accuracy testing device according to a second embodiment of the present invention;

fig. 3a is a schematic structural diagram of a time synchronization accuracy testing system according to a third embodiment of the present invention;

FIG. 3b is a schematic diagram of another time synchronization accuracy testing system according to the third embodiment of the present invention;

fig. 4 is a schematic structural diagram of an electronic device implementing a time synchronization accuracy testing method according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1a is a flowchart of a time synchronization accuracy testing method provided in an embodiment of the present invention, where the embodiment may be suitable for a case of performing a time synchronization accuracy test on a Chip that is involved in decision making in a vehicle domain controller, the method may be performed by a time synchronization accuracy testing device, the time synchronization accuracy testing device may be implemented in a form of hardware and/or software, the time synchronization accuracy testing device may be configured in an upper computer of a time synchronization accuracy testing System, the time synchronization accuracy testing System may further include a domain controller and a signal generator, and the domain controller may include an MCU (Microcontroller Unit, micro control unit) Chip and at least one SOC (System on Chip) Chip. As shown in fig. 1a, the method comprises:

s110, the trigger signal generator transmits pulse signals according to a preset period.

In this embodiment, for example, a pulse signal with a duty ratio of 10% and an amplitude of 1.8V at 1Hz can be emitted by the signal generator as a time measurement standard of 1 second. The setting of the pulse signal is only an example and is not a limitation of the present embodiment.

The triggering mode of the signal generator can be triggered by an upper computer or manually.

S120, acquiring different receiving times of the MCU chip and each SOC chip on the same pulse signal and different receiving times of the same SOC chip on two adjacent pulse signals.

The pulse signal sent by the signal generator can be received by the MCU chip and the SOC chip in the domain controller, so that the purpose of testing the time synchronization precision in the chip or the chip is achieved.

In an alternative embodiment, obtaining different receiving times of the same pulse signal by the MCU chip and each SOC chip, and different receiving times of two adjacent pulse signals by the same SOC chip, includes: after determining that the signal generator transmits the current pulse signal according to the preset period, acquiring the current first receiving time of the MCU chip to the current pulse signal and acquiring the current second receiving time of each SOC chip to the current pulse signal; after determining that the signal generator transmits the next pulse signal according to the preset period, returning to acquire the next first receiving time of the MCU chip to the next pulse signal, and acquiring the next second receiving time of each SOC chip to the next pulse signal until the signal generator stops transmitting the pulse signal.

In this embodiment, since the pulse signal is periodically transmitted, the MCU chip and each SOC chip also periodically receive the pulse signal.

Taking an MCU chip and an SOC chip as an example for explanation, the current first sending of the pulse signal records that the current sending time is t1, correspondingly, the MCU chip records that the receiving time of the MCU chip to the current first pulse signal is t3 (namely the current first receiving time), and the SOC chip records that the receiving time of the MCU chip to the current first pulse signal is t5 (namely the current second receiving time); the pulse signal is sent out for the second time after a preset period, the time is recorded as t2, the MCU chip records the receiving time of the pulse signal for the second time as a second first receiving time t4 (corresponding to the next first receiving time), and the SOC chip records the receiving time of the pulse signal for the second time as a second receiving time t6 (corresponding to the next second receiving time); and so on until the signal generator stops transmitting the pulse signal. And the MCU chip and the SOC chip can timely upload the recorded receiving time information to the upper computer, so that the upper computer can acquire different receiving times (such as t3 and t 5) of the MCU chip and the SOC chip on the same pulse signal respectively and different receiving times (such as t5 and t 6) of the same SOC chip on two adjacent pulse signals.

For example, the periodic emission time of the pulse signal, and the reception time of the pulse signal by the MCU chip and the SOC chip may be as shown in fig. 1 b.

If the number of SOC chips is plural, each SOC chip may be numbered, and the receiving time information recorded by each SOC chip may be uploaded as a catalog.

S130, testing first time precision between the MCU chip and each SOC chip through a preset inter-chip time precision algorithm based on different receiving time of the same pulse signal by the MCU chip and each SOC chip.

In an alternative embodiment, the following operations may be performed for each SOC chip: calculating a difference value between the current first receiving time and the current second receiving time as a current first time precision between the MCU chip and the current SOC chip; the difference between the next first reception time and the next second reception time is calculated as the next first time accuracy between the MCU chip and the current SOC chip.

Specifically, when the number of SOC chips is one, the example of S120 may use |t5-t3| as the first time precision (i.e., the current first time precision) between the MCU chip and the SOC chip; the |t6-t4| may be taken as the second first time precision (i.e., the next first time precision) between the MCU chip and the SOC chip.

When the number of the SOC chips is multiple, one current SOC chip can be determined in sequence according to the number of the SOC chips. Replacing the current SOC chip with the SOC chip in the S120 example, then |t5-t3| may be taken as the first time precision (i.e., the current first time precision) between the MCU chip and the current SOC chip; the |t6-t4| may be taken as the second first time precision (i.e., the next first time precision) between the MCU chip and the current SOC chip. And obtaining a plurality of first time accuracies between the MCU chip and each SOC chip until all the SOC chips are processed.

S140, based on different receiving time and preset period of the same SOC chip to two adjacent pulse signals, testing second time precision in the same SOC chip through a time precision algorithm in the preset chip.

In an alternative embodiment, the following operations may be performed for each SOC chip:

if the current pulse signal is not the first pulse signal, after determining that the current second receiving time of the current SOC chip to the current pulse signal is acquired, determining a first difference value between the current second receiving time and a previous second receiving time adjacent to the current second receiving time; taking the second difference value between the first difference value and the preset period as the current second time precision in the current SOC chip;

if the current pulse signal is the first pulse signal, after determining that the next second receiving time of the current SOC chip to the current pulse signal is acquired, determining a new first difference value between the current second receiving time and the next second receiving time; and taking the new first difference value and a new second difference value between preset periods as the next second time precision in the current SOC chip.

Specifically, when the number of SOC chips is one or more, the SOC chip in the S120 example is regarded as the current SOC chip of the one or more SOC chips, and the current pulse signal in the S120 example is the first pulse signal. The second difference is |t6-t5| -1s, and the second difference is used as the second time precision, wherein |t6-t5| is the first difference.

If the current pulse signal is not the first pulse signal, the method for determining the second time precision after acquiring the previous second receiving time adjacent to the current second receiving time is the same as the scheme.

Optionally, a time precision threshold (for example, 200 μs) may be preset, and the current first time precision, the next first time precision, the current second time precision, and the next second time precision calculated each time are compared with the preset time precision threshold, and a time synchronization precision test report may be generated according to the comparison result and displayed to the user, so that the user performs adaptive adjustment according to the test report.

Example two

Fig. 2 is a schematic structural diagram of a time synchronization accuracy testing device according to a second embodiment of the present invention. The device can be integrated in an upper computer of a time synchronization precision testing system, the time synchronization precision testing system can also comprise a domain controller and a signal generator, the domain controller can comprise a micro control unit MCU chip and at least one system-level SOC chip, as shown in FIG. 2, and the device comprises: a pulse signal transmission triggering module 210, a pulse signal receiving time acquisition module 220, an inter-chip time precision test module 230 and an intra-chip time precision test module 240. Wherein:

a pulse signal transmitting triggering module 210, configured to trigger the signal generator to transmit a pulse signal according to a preset period;

the pulse signal receiving time obtaining module 220 is configured to obtain different receiving times of the same pulse signal by the MCU chip and each SOC chip, and different receiving times of two adjacent pulse signals by the same SOC chip;

the inter-chip time precision testing module 230 is configured to test a first time precision between the MCU chip and each SOC chip by presetting an inter-chip time precision algorithm based on different receiving times of the same pulse signal by the MCU chip and each SOC chip, respectively;

the on-chip time precision testing module 240 is configured to test the second time precision in the same SOC chip by using an on-chip time precision algorithm based on different receiving times of two adjacent pulse signals by the same SOC chip and the preset period.

Optionally, the pulse signal receiving time acquisition module 220 may specifically be configured to:

after determining that the signal generator transmits a current pulse signal according to the preset period, acquiring the current first receiving time of the MCU chip to the current pulse signal and acquiring the current second receiving time of each SOC chip to the current pulse signal;

after determining that the signal generator transmits the next pulse signal according to the preset period, returning to acquire the next first receiving time of the MCU chip to the next pulse signal, and acquiring the next second receiving time of each SOC chip to the next pulse signal until the signal generator stops transmitting the pulse signal.

Optionally, the inter-chip time precision testing module 230 may specifically be configured to:

the following operations are performed for each SOC chip:

calculating a difference value between the current first receiving time and the current second receiving time as a current first time precision between the MCU chip and a current SOC chip;

and calculating the difference value between the next first receiving time and the next second receiving time as the next first time precision between the MCU chip and the current SOC chip.

Optionally, the on-chip time precision testing module 240 may specifically be configured to:

the following operations are performed for each SOC chip:

if the current pulse signal is the first pulse signal, after determining that the next second receiving time of the current SOC chip to the current pulse signal is acquired, determining a new first difference value between the current second receiving time and the next second receiving time; and taking the new first difference value and the new second difference value between the preset periods as the next second time precision in the current SOC chip.

The time synchronization precision testing device provided by the embodiment of the invention can execute the time synchronization precision testing method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example III

Fig. 3a is a schematic structural diagram of a time synchronization accuracy testing system according to a third embodiment of the present invention. As shown in fig. 3a, the system comprises: a signal generator 310, a domain controller 320, and an upper computer 330; the domain controller 320 includes one MCU chip 3201 and at least one SOC chip 3202;

the signal generator 310 is configured to transmit a pulse signal according to a preset period;

the MCU chip 3201 and the SOC chip 3202 are configured to receive the pulse signal, and send time information of receiving the pulse signal to the upper computer 330;

the upper computer 330 is configured to execute the time synchronization accuracy testing method according to any embodiment of the present invention, where the method includes:

triggering the signal generator 310 to emit a pulse signal according to a preset period;

different receiving times of the MCU chip 3201 and each SOC chip 3202 on the same pulse signal and different receiving times of the same SOC chip 3202 on two adjacent pulse signals are obtained;

based on different receiving times of the MCU chip 3201 and each SOC chip 3202 to the same pulse signal, testing first time precision between the MCU chip 3201 and each SOC chip 3202 through a preset inter-chip time precision algorithm;

based on the different receiving times of the same SOC chip 3202 to the two adjacent pulse signals and the preset period, a second time precision in the same SOC chip 3202 is tested through a preset intra-chip time precision algorithm.

Optionally, the time synchronization accuracy testing system may further include: a network harness 340;

the network wire harness is used for connecting the domain controller and the upper computer through a wire harness main joint of the domain controller, and transmitting time information between the domain controller and the upper computer.

Optionally, the time synchronization accuracy testing system may further include: a test harness 350;

the test harness is used for connecting the signal generator to the MCU chip and each SOC chip of the domain controller through a plurality of digital signal test points which respectively correspond to the MCU chip and each SOC chip on the domain controller.

Fig. 3b is a schematic structural diagram of another time synchronization accuracy testing system according to the third embodiment of the present invention. The time synchronization accuracy test system is composed of a domain controller 320, a network harness 340, an upper computer 330, a signal generator 310 and a test harness 350. The domain controller 320 is connected to the host computer 330 via a network harness 340, and the signal generator 310 is connected to the domain controller 320 via a test harness 350. The domain controller 320 includes an MCU chip 3201, an SOC chip 3202, a wire harness main connector 3203, and a digital signal measuring point 3204. Both the MCU chip 3201 and the SOC chip 3202 can perform a read operation on the digital signal test points 3204. The harness main header 3203 has an interface to the network harness 340.

Example IV

Fig. 4 shows a schematic diagram of an electronic device 400 that may be used to implement an embodiment of the invention. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 4, the electronic device 400 includes at least one processor 401, and a memory communicatively connected to the at least one processor 401, such as a Read Only Memory (ROM) 402, a Random Access Memory (RAM) 403, etc., in which the memory stores a computer program executable by the at least one processor, and the processor 401 may perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM) 402 or the computer program loaded from the storage unit 408 into the Random Access Memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the electronic device 400 may also be stored. The processor 401, the ROM 402, and the RAM 403 are connected to each other by a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.

Various components in electronic device 400 are connected to I/O interface 405, including: an input unit 406 such as a keyboard, a mouse, etc.; an output unit 407 such as various types of displays, speakers, and the like; a storage unit 408, such as a magnetic disk, optical disk, etc.; and a communication unit 409 such as a network card, modem, wireless communication transceiver, etc. The communication unit 409 allows the electronic device 400 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

Processor 401 may be a variety of general purpose and/or special purpose processing components with processing and computing capabilities. Some examples of processor 401 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 401 performs the various methods and processes described above, such as the time synchronization accuracy test method.

In some embodiments, the time synchronization accuracy testing method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 408. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 400 via the ROM 402 and/or the communication unit 409. When a computer program is loaded into RAM 403 and executed by processor 401, one or more steps of the time synchronization accuracy testing method described above may be performed. Alternatively, in other embodiments, processor 401 may be configured to perform the time synchronization accuracy test method in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. The time synchronization precision testing method is applied to an upper computer of a time synchronization precision testing system, and the time synchronization precision testing system also comprises a domain controller and a signal generator, wherein the domain controller comprises a micro control unit MCU chip and at least one system-level SOC chip, and is characterized by comprising the following components:

2. The method of claim 1, wherein obtaining different reception times of the same pulse signal by the MCU chip and each SOC chip, respectively, and different reception times of two adjacent pulse signals by the same SOC chip, comprises:

3. The method of claim 2, wherein testing the first time accuracy between the MCU chip and each SOC chip by a preset inter-chip time accuracy algorithm based on different times of receipt of the same pulse signal by the MCU chip and each SOC chip, respectively, comprises:

the following operations are performed for each SOC chip:

4. The method of claim 2, wherein testing a second time precision within the same SOC chip by a preset on-chip time precision algorithm based on different times of receipt of two adjacent pulse signals by the same SOC chip and the preset period, comprises:

the following operations are performed for each SOC chip:

5. The utility model provides a time synchronization precision testing arrangement, integrates in time synchronization precision testing system's host computer, time synchronization precision testing system still includes domain controller and signal generator, domain controller includes a little control unit MCU chip and at least one system level SOC chip, its characterized in that includes:

6. A time synchronization accuracy testing system, comprising: the system comprises a signal generator, a domain controller and an upper computer; the domain controller comprises an MCU chip and at least one SOC chip;

the upper computer is used for executing the time synchronization precision testing method of claims 1-4.

7. The system of claim 6, further comprising: a network harness;

8. The system of claim 6, further comprising a test harness;

9. An electronic device, the electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform a time synchronization accuracy testing method of any one of claims 1-4.

10. A computer readable storage medium storing computer instructions for causing a processor to perform a time synchronization accuracy testing method according to any one of claims 1-4.