CN117009283A - Multi-core multi-chip data processing method, device, chip and storage medium - Google Patents
Multi-core multi-chip data processing method, device, chip and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a multi-core multi-chip data processing method, a device, a chip and a storage medium, comprising the following steps: after receiving the calculation core synchronization request, the target chip receives the core synchronization data sent by all the second calculation cores through the first calculation cores in the target chip, and then sends the chip synchronization data to the first calculation cores corresponding to the rest chips; after detecting the first computing cores corresponding to all chips and receiving all chip synchronization data, determining that the inter-chip synchronization is completed; and sending the core synchronization data to each second computing core through the first computing core, and if each second computing core is determined to receive the core synchronization data, determining that the on-chip synchronization is completed. The technical scheme of the embodiment of the invention can improve the synchronization efficiency of the computing cores in the multi-core multi-chip architecture and the data processing performance of the multi-core multi-chip architecture.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a chip, and a storage medium for processing multi-core multi-chip data.
Background
With the development of artificial intelligence (Artificial Intelligence, AI), conventional computing system architectures have gradually shifted to a multi-core multi-chip mode, i.e., a computing system architecture including a plurality of chips each including a plurality of computing cores.
When the existing multi-core multi-chip architecture realizes the synchronization of the computing cores, each computing core is generally required to send synchronous data to all other computing cores, so that the synchronization efficiency of the computing cores is low, and the data processing performance of the multi-core multi-chip architecture is seriously affected.
Disclosure of Invention
The invention provides a multi-core multi-chip data processing method, a device, a chip and a storage medium, which can improve the synchronization efficiency of computing cores in a multi-core multi-chip architecture and the data processing performance of the multi-core multi-chip architecture.
According to an aspect of the present invention, there is provided a multi-core multi-chip data processing method applied to a target chip of a multi-core multi-chip, the method including:
after receiving the calculation core synchronization request, receiving the core synchronization data sent by all second calculation cores through the first calculation cores in the target chip, and then sending the chip synchronization data to the first calculation cores corresponding to the rest chips;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip;
after detecting the first computing cores corresponding to all chips and receiving all chip synchronization data, determining that the inter-chip synchronization is completed;
and sending the core synchronization data to each second computing core through the first computing core, and if each second computing core is determined to receive the core synchronization data, determining that the on-chip synchronization is completed.
Optionally, after receiving the request for synchronizing the computing cores, before receiving the core synchronization data sent by all the second computing cores through the first computing core in the target chip, the method further includes:
acquiring all computing cores included in a target chip;
and screening the first computing core and the second computing core from all computing cores according to the transmission performance and the computing performance corresponding to each computing core.
Optionally, the method further comprises:
after detecting that a target computing core in a target chip receives a function computing request, receiving computing data sent by an associated computing core in each associated chip through the target computing core;
and processing the calculation data according to the function calculation request through the target calculation core, and sending the processing result to each associated calculation core.
Optionally, after receiving the request for synchronizing the computing cores, receiving, by the first computing core in the target chip, core synchronization data sent by all the second computing cores, including:
after receiving the calculation core synchronization request, if each second calculation core is detected to be executing the calculation function, after determining that each second calculation core is executing the calculation function, sending core synchronization data to the first calculation core through each second calculation core.
Optionally, the core synchronization data includes identification information of a computing core; the chip synchronization data includes identification information of the chip.
According to another aspect of the present invention, there is provided a multi-core multi-chip data processing apparatus applied to a target chip among multi-core multi-chips, the apparatus comprising:
the core synchronous data transmitting module is used for receiving the core synchronous data transmitted by all the second computing cores through the first computing cores in the target chip after receiving the computing core synchronous request, and then transmitting the chip synchronous data to the first computing cores corresponding to the rest chips;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip;
the inter-chip synchronization module is used for detecting the first computing cores corresponding to all the chips, and determining that the inter-chip synchronization is finished after receiving all the chip synchronization data;
and the on-chip synchronization module is used for sending the core synchronization data to each second computing core through the first computing core, and if each second computing core is determined to receive the core synchronization data, the on-chip synchronization is determined to be completed.
Optionally, the apparatus further includes:
the computing core acquisition module is used for acquiring all computing cores included in the target chip;
and the computing core screening module is used for screening the first computing core and the second computing core from all the computing cores according to the transmission performance and the computing performance corresponding to each computing core.
According to another aspect of the present invention, there is provided a chip including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the multi-core multi-chip data processing method according to any one of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute the method for processing multi-core multi-chip data according to any one of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the multi-core multi-chip data processing method according to any of the embodiments of the present invention.
According to the technical scheme provided by the embodiment of the invention, after the target chip receives the core synchronization request, the core synchronization data sent by all the second computing cores are received through the first computing cores, then the chip synchronization data are sent to the first computing cores corresponding to all the remaining chips, after all the first computing cores corresponding to all the chips are detected, the inter-chip synchronization is confirmed to be completed, the core synchronization data are sent to all the second computing cores through the first computing cores, if each second computing core is confirmed to receive the core synchronization data, the technical means of the intra-chip synchronization is confirmed to be completed, and the synchronization efficiency of the computing cores in the multi-core multi-chip architecture and the data processing performance of the multi-core multi-chip architecture can be improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a multi-core multi-chip data processing method provided according to an embodiment of the present invention;
FIG. 2 is a flow chart of another multi-core multi-chip data processing method provided in accordance with an embodiment of the present invention;
FIG. 3 is a schematic diagram of a multi-core multi-chip data processing apparatus according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a chip for implementing a multi-core multi-chip data processing method according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a flowchart of a multi-core multi-chip data processing method according to a first embodiment of the present invention, where the method may be performed by a multi-core multi-chip data processing device, the device may be implemented in hardware and/or software, and the device may be configured in a target chip with a data processing function. As shown in fig. 1, the method includes:
step 110, after receiving the request for synchronizing the computing cores, receiving the core synchronizing data sent by all the second computing cores through the first computing cores in the target chip, and then sending the chip synchronizing data to the first computing cores corresponding to the remaining chips.
In this embodiment, the target chip may be any chip in a multi-core multi-chip architecture. In an actual multi-core multi-chip architecture, each compute core may need to perform multiple compute function functions, the multi-core multi-chip may need to perform a compute core synchronization (all core sync) once before executing to a particular function, and after completing the compute core synchronization, perform subsequent functions through each compute core.
In a specific embodiment, after the target chip receives the computing core synchronization request, the corresponding synchronization data (i.e., core synchronization data) may be sent to the first computing core by the second computing core in the target chip. The first computing core is a computing core0 used for data transmission in the target chip; the second computing core is a computing core1 for performing data computation in the target chip.
After receiving the core synchronization data sent by all the second computing cores, the first computing core in the target chip can perform global broadcasting, that is, the synchronization data (also called chip synchronization data) corresponding to the target chip is sent to the first computing cores in the remaining chips (which may include the target chip).
Step 120, after detecting the first computing cores corresponding to all the chips, all the chip synchronization data are received, and determining that the inter-chip synchronization is completed.
In this embodiment, after detecting that each first computing core receives the chip synchronization data sent by all the other first computing cores in the multi-core multi-chip architecture, it may be determined that synchronization is completed between the multiple chips.
And 130, sending core synchronization data to each second computing core through the first computing core, and if each second computing core is determined to receive the core synchronization data, determining that the on-chip synchronization is completed.
In this embodiment, after the inter-chip synchronization is completed, corresponding synchronization data (i.e., core synchronization data) may be sent to each second computing core through the first computing core in the target chip, and if each second computing core in the target chip receives the core synchronization data, it may be determined that the target chip completes the inter-chip synchronization.
In a specific embodiment, after the synchronization process described above is completed, subsequent functions may be performed by each compute core in the multi-core multi-chip architecture.
In this embodiment, in the multi-core multi-chip architecture, data transmission is performed by adopting a first computing core, data computation is performed by a second computing core, each second computing core is managed by the first computing core, global synchronization of the multi-core multi-chip system can be achieved through an inter-chip and intra-chip cooperation synchronization mechanism, and synchronization efficiency of the computing cores and data processing performance of the multi-core multi-chip architecture are improved.
According to the technical scheme provided by the embodiment of the invention, after the target chip receives the core synchronization request, the core synchronization data sent by all the second computing cores are received through the first computing cores, then the chip synchronization data are sent to the first computing cores corresponding to all the remaining chips, after all the first computing cores corresponding to all the chips are detected, the inter-chip synchronization is confirmed to be completed, the core synchronization data are sent to all the second computing cores through the first computing cores, if each second computing core is confirmed to receive the core synchronization data, the technical means of the intra-chip synchronization is confirmed to be completed, and the synchronization efficiency of the computing cores in the multi-core multi-chip architecture and the data processing performance of the multi-core multi-chip architecture can be improved.
On the basis of the above embodiment, the method further includes: after detecting that a target computing core in a target chip receives a function computing request, receiving computing data sent by an associated computing core in each associated chip through the target computing core; and processing the calculation data according to the function calculation request through the target calculation core, and sending the processing result to each associated calculation core.
In this embodiment, if the target computing core in the target chip receives the function computing request, the data to be computed may be sent to the target computing core through the associated computing core in the associated chip corresponding to the target chip, and after the target computing core receives the data, the data may be computed by using the corresponding computing function, and then the computing result is sent to each associated computing core. The correlation chip is understood to be a chip having a data dependency relationship with the target chip.
The advantage of this arrangement is that compared with the mode of receiving and transmitting data by using chips in the multi-core multi-chip architecture in the prior art, a processing mode of directly receiving and transmitting data by using a computing core is provided, so that the data processing efficiency of the multi-core multi-chip architecture can be improved.
Fig. 2 is a flowchart of a multi-core multi-chip data processing method according to a second embodiment of the present invention, where the foregoing embodiment is further refined. As shown in fig. 2, the method includes:
step 210, obtaining all computing cores included in the target chip, and screening the first computing core and the second computing core from all computing cores according to the transmission performance and the computing performance corresponding to each computing core.
In this embodiment, the performance of different computing cores in the target chip is different. Alternatively, according to the performance priority of each computing core in the target chip, a computing core with a higher priority of transmission data is selected from all computing cores as a first computing core0, and then a computing core with a higher priority of computing performance is selected as a second computing core1.
The first computing core is used for receiving and transmitting data, and the second computing core is used for computing the data.
220. After receiving the calculation core synchronization request, if each second calculation core is detected to be executing the calculation function, after determining that each second calculation core is executing the calculation function, sending core synchronization data to the first calculation core through each second calculation core.
In one implementation of this embodiment, the core synchronization data includes identification information of the computing core, such as an identification number (Identity document, ID), a model number, or a serial number corresponding to the computing core.
And 230, transmitting the chip synchronization data to the first computing cores corresponding to the rest chips through the first computing cores in the target chips.
In one implementation manner of this embodiment, the chip synchronization data includes identification information of the chip, for example, an ID, a model number, or a serial number corresponding to the chip.
Step 240, after detecting the first computing cores corresponding to all the chips, all the chip synchronization data are received, and then the inter-chip synchronization is determined to be completed.
Step 250, sending core synchronization data to each second computing core through the first computing core, and if each second computing core is determined to receive the core synchronization data, determining that the on-chip synchronization is completed.
According to the technical scheme provided by the embodiment of the invention, through acquiring all computing cores included in a target chip, screening first computing cores and second computing cores in all computing cores according to transmission performance and computing performance corresponding to the computing cores, after receiving a computing core synchronization request, if each second computing core is detected to execute a computing function, after determining that each second computing core is executing the computing function, sending core synchronization data to the first computing core through each second computing core, sending chip synchronization data to the first computing cores corresponding to the rest chips through the first computing cores in the target chip, detecting the first computing cores corresponding to all chips, determining that inter-chip synchronization is completed after all chip synchronization data are received, sending core synchronization data to each second computing core through the first computing cores, and if determining that each second computing core is receiving the core synchronization data, determining that inter-chip synchronization is completed, thereby improving the synchronization efficiency of the computing cores in a multi-chip architecture and the data processing performance of the multi-chip architecture.
Fig. 3 is a schematic structural diagram of a multi-core multi-chip data processing apparatus according to a third embodiment of the present invention, where, as shown in fig. 3, the apparatus includes: a core synchronization data transmission module 310, an inter-chip synchronization module 320, and an intra-chip synchronization module 330.
The core synchronization data sending module 310 is configured to receive, after receiving a core synchronization request, core synchronization data sent by all second computing cores through a first computing core in the target chip, and then send the core synchronization data to first computing cores corresponding to the remaining chips;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip;
the inter-chip synchronization module 320 is configured to detect first computing cores corresponding to all chips, and determine that inter-chip synchronization is completed after receiving all chip synchronization data;
and the on-chip synchronization module 330 is configured to send, through the first computing core, core synchronization data to each second computing core, and if it is determined that each second computing core receives the core synchronization data, determine that on-chip synchronization is completed.
According to the technical scheme provided by the embodiment of the invention, after the target chip receives the core synchronization request, the core synchronization data sent by all the second computing cores are received through the first computing cores, then the chip synchronization data are sent to the first computing cores corresponding to all the remaining chips, after all the first computing cores corresponding to all the chips are detected, the inter-chip synchronization is confirmed to be completed, the core synchronization data are sent to all the second computing cores through the first computing cores, if each second computing core is confirmed to receive the core synchronization data, the technical means of the intra-chip synchronization is confirmed to be completed, and the synchronization efficiency of the computing cores in the multi-core multi-chip architecture and the data processing performance of the multi-core multi-chip architecture can be improved.
On the basis of the above embodiment, the core synchronization data includes identification information of a computing core; the chip synchronization data includes identification information of the chip.
The apparatus further comprises:
the computing core acquisition module is used for acquiring all computing cores included in the target chip;
the computing core screening module is used for screening the first computing core and the second computing core from all computing cores according to the transmission performance and the computing performance corresponding to each computing core;
the computing data receiving module is used for receiving computing data sent by the associated computing cores in each associated chip through the target computing cores after detecting that the target computing cores in the target chips receive the function computing requests;
and the processing result sending module is used for processing the calculation data according to the function calculation request through the target calculation core and sending the processing result to each associated calculation core.
The core synchronization data transmission module 310 includes:
and the function detection unit is used for sending the core synchronization data to the first computing core through each second computing core after determining that each second computing core finishes executing the computing function if each second computing core is detected to execute the computing function after receiving the computing core synchronization request.
The device can execute the method provided by all the embodiments of the invention, and has the corresponding functional modules and beneficial effects of executing the method. Technical details not described in detail in the embodiments of the present invention can be found in the methods provided in all the foregoing embodiments of the present invention.
Fig. 4 shows a schematic diagram of the structure of a chip 10 that may be used to implement an embodiment of the invention. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 4, the chip 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the chip 10 can also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
The various components in the chip 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the chip 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a multi-core multi-chip data processing method.
In some embodiments, the multi-core multi-chip data processing method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the chip 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the multi-core multi-chip data processing method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the multi-core multi-chip data processing method in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a chip having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or a trackball) through which a user can provide input to the chip. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A multi-core multi-chip data processing method, characterized in that it is applied to a target chip among multi-core multi-chips, the method comprising:
after receiving the calculation core synchronization request, receiving the core synchronization data sent by all second calculation cores through the first calculation cores in the target chip, and then sending the chip synchronization data to the first calculation cores corresponding to the rest chips;
the first computing core is a computing core used for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip;
after detecting the first computing cores corresponding to all chips and receiving all chip synchronization data, determining that the inter-chip synchronization is completed;
and sending the core synchronization data to each second computing core through the first computing core, and if each second computing core is determined to receive the core synchronization data, determining that the on-chip synchronization is completed.
2. The method of claim 1, wherein after receiving the compute core synchronization request, before receiving, by a first compute core in the target chip, the core synchronization data sent by all second compute cores, further comprising:
acquiring all computing cores included in a target chip;
and screening the first computing core and the second computing core from all computing cores according to the transmission performance and the computing performance corresponding to each computing core.
3. The method according to claim 1, wherein the method further comprises:
after detecting that a target computing core in a target chip receives a function computing request, receiving computing data sent by an associated computing core in each associated chip through the target computing core;
and processing the calculation data according to the function calculation request through the target calculation core, and sending the processing result to each associated calculation core.
4. The method of claim 1, wherein receiving, by a first computing core in the target chip after receiving the computing core synchronization request, core synchronization data sent by all second computing cores, comprises:
after receiving the calculation core synchronization request, if each second calculation core is detected to be executing the calculation function, after determining that each second calculation core is executing the calculation function, sending core synchronization data to the first calculation core through each second calculation core.
5. The method of claim 1, wherein the core synchronization data includes identification information of a computing core; the chip synchronization data includes identification information of the chip.
6. A multi-core multi-chip data processing apparatus for application to a target chip of a multi-core multi-chip, the apparatus comprising:
the core synchronous data transmitting module is used for receiving the core synchronous data transmitted by all the second computing cores through the first computing cores in the target chip after receiving the computing core synchronous request, and then transmitting the chip synchronous data to the first computing cores corresponding to the rest chips;
the first computing core is a computing core for data transmission in the target chip; the second computing core is a computing core used for data computation in the target chip;
the inter-chip synchronization module is used for detecting the first computing cores corresponding to all the chips, and determining that the inter-chip synchronization is finished after receiving all the chip synchronization data;
and the on-chip synchronization module is used for sending the core synchronization data to each second computing core through the first computing core, and if each second computing core is determined to receive the core synchronization data, the on-chip synchronization is determined to be completed.
7. The apparatus of claim 6, wherein the apparatus further comprises:
the computing core acquisition module is used for acquiring all computing cores included in the target chip;
and the computing core screening module is used for screening the first computing core and the second computing core from all the computing cores according to the transmission performance and the computing performance corresponding to each computing core.
8. A chip, the chip comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the multi-core, multi-chip data processing method of any one of claims 1-5.
9. A computer readable storage medium storing computer instructions for causing a processor to perform the multi-core multi-chip data processing method of any one of claims 1-5.
10. A computer program product, characterized in that it comprises a computer program which, when executed by a processor, implements the multi-core multi-chip data processing method according to any of claims 1-5.
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| CN117472844B (en) * | 2023-12-27 | 2024-03-19 | 中诚华隆计算机技术有限公司 | Multi-chip module and data processing method |
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