JP2595583Y2 - Delay generator for semiconductor test equipment - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay generator for use in a semiconductor test apparatus for providing a set delay to each output of a timing generator provided for each measurement channel.

[0002]

2. Description of the Related Art FIG. 3A shows a conventional apparatus. IC under test
Measurement channel 11 corresponding with the pin of the device (not shown) are provided distributed in a plurality of boards 12 ₁ to 12 _n. Each measurement channel 11 is provided with a timing generator 13 as shown in FIG. 3B, and the output of the timing generator 13 is delayed by a plurality of variable delay generators 14 by the respective delay amounts to obtain a desired timing pulse. It is possible to output as.

Conventionally, the amount of delay of each variable delay generator 14 is adjusted by connecting one variable delay generator 14 for each measurement channel 11 to a measurement circuit 17 by controlling a multiplexer 16 under the control of a CPU 15. And go. As shown in FIG. 4, for example, each of the variable delay generators 14 includes a plurality of cascaded delay stages 18 in which one of the direct path 51 and the path of the delay element 52 is selected by the multiplexer 53. The delay element 52 utilizes the propagation delay T _pd in the multi-stage connection gate IC. By setting for each multiplexer 53 , the delay amount is measured for all possible paths from the input terminal to the output terminal. The measurement of the delay amount is performed by configuring and oscillating an oscillation circuit including the path of the variable delay generator, and measuring the oscillation cycle. The measured delay amounts of the respective paths are arranged in ascending order, and those in which the difference between the delay amounts becomes a predetermined value ΔT are sequentially taken out. That delay amount T _a, T _a + Δ
_{T, T a + 2ΔT, T} a + 3ΔT, to select each route of .... A delay amount of 0,
ΔT, 2ΔT, 3ΔT, by entering the data indicating ..., the delay amount _{T a, T a + ΔT,} T a + 2ΔT,
Each delay stage 1 for taking each path of T _a + 3ΔT,.
The data for controlling the eight multiplexers 53 is output to control the corresponding multiplexer 53 . Data indicating a desired delay amount is set in the latch circuit 21, and the output thereof controls each multiplexer 53 via the data converter 19 to set a delay corresponding to the desired delay amount .

[0004]

As described above, in the prior art, the delay amount has been adjusted one by one for each of the plurality of variable delay generators 14 for each measurement channel.
Therefore, for example, the number of measurement channels 11 is 512, the number of variable delay generators 14 provided for one measurement channel is 7,
When the number of delay stages 18 of one delay generator 14 is 10, it is necessary to measure the amount of delay 512 × 7 × 1024 times,
For this reason, the measurement time becomes longer, and it is necessary for the CPU 15 to set the data for each of the delay generators by the number of times described above.

[0005]

SUMMARY OF THE INVENTION A semiconductor test device according to the present invention is provided.
The delay generator for test equipment supports each pin of the IC element under test.
Timing for each measurement channel provided in
Generator, and set the output of each timing generator.
Variable delay generator that can delay a specified amount of delay
Are provided, and each of the variable delay generators
Depending on the setting, one of the path to be given and the path to give no delay
Delay stages to be selected by cascade connection.
It was in the delay generator for a semiconductor test apparatus, a plurality of the
Variable delay generators are divided into multiple groups, and each group has a delay.
A delay amount adjustment circuit is provided, and each of these delay amount adjustment circuits
For each variable delay generator belonging to that group,
Variable delay generator from its input to its output
All of the routes in sequence, and for each
Measure the delay amount of the variable delay generator and set each of these path selection settings.
And the corresponding measured value, it is necessary for the variable delay generator
What route should be set for each set delay amount
Has a means to determine how.

[0006]

FIG. 1 shows an embodiment of the present invention, in which parts corresponding to those in FIG. 3 are denoted by the same reference numerals. In this embodiment, the delay amount adjustment circuit 22 ₁ in each board 12 ₁ to 12 _n
To 22 _n are provided. These delay amount adjusting circuits 22 _1-
22n adjusts the delay amount of each of the plurality of variable delay generators belonging to each measurement channel in the board to which each belongs.
Delay adjusting circuit 22 ₁ through 22 _n are identical structure, shows a specific example in FIG.

When a start pulse is given from terminal 23,
The oscillator 24 starts oscillating. The output of the oscillator 24 is frequency-divided by a frequency divider 25, and the frequency-divided output is counted by a counter 26. Using the count value of the counter 26 as an address,
The instruction code memory 27 is read. The instruction codes sequentially read from the memory 27 are decoded by the decoder 28, and the decoded output causes the address pointer 29 to address and read the memory 31. The memory 31 stores data for setting the system to be measured, that is, the delay generator 14 to a predetermined operation mode. Therefore, data for setting the delay generator 14 to the measurement mode and memory addresses are stored in the internal bus. 32 are sequentially output. When the predetermined data set is completed, the oscillation of the oscillator 24 is stopped, the flip-flop 33 is set, and a pulse is generated by the pulse generator 34 at the set output.
The multiplexer 35 is controlled by the data set by the output of the memory 31 to select one of the variable delay generators 14, and when the gate 36 is opened at the output of the decoder 28, a loop including the selected delay generator 14 is performed. Is formed, and the pulse from the pulse generator 34 oscillates in this loop. This oscillation output is frequency-divided by a divider 37, and the frequency of the frequency-divided output is changed by a scaler 38.
Is measured by counting the reference clock from the terminal 39.

The delay amount for the set delay amount (one path in FIG. 4) of the selected variable delay generator 14 is measured, and the measurement result is stored in the storage memory 41. Variable delay generator 14 similarly selected
Are sequentially set, and the delay amount is measured. The measurement results are sorted by the arithmetic unit 42 as described above, and the one having the target accuracy interval ΔT is selected, and the correspondence between the target delay amount and the setting data is stored in the conversion memory 43. Similarly, for the other delay generators 14, the correspondence between the set delay amount and the set data is obtained. The above is automatically performed for all the variable delay generators belonging to the board.

With such a configuration, the CPU 1
5 be given a start command for delay adjustment in the delay adjusting circuit 22 ₁ through 22 _n, for all of the variable delay generator 14 of the delay amount adjustment circuit 22 ₁ through 22 _n is in each automatically the board Adjust the delay amount. The obtained data of each conversion memory 43 is transferred to the CPU 15.

[0010]

As described above, according to the present invention, a delay amount adjusting circuit is provided for each of a plurality of variable delay generators, and each variable amount adjusting circuit automatically adjusts the variable delay generator belonging thereto. Therefore, if the number of groups of the variable delay generators (the number of boards 12 in the embodiment) is N,
By itself, the adjustment time is reduced to 1 / N of the conventional one. In addition, since each delay adjustment circuit forms a loop for the delay generator to be adjusted within the board and performs measurement, for example, the loop length is short, and one measurement is conventionally performed for the entire variable delay generator. Since the circuit 17 is used, the average loop length becomes long, whereas the present invention is, for example, about one fifth. For this reason, in the present invention, the adjustment time is reduced to about 1 / 5N as compared with the related art, and the adjustment time can be significantly shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of a delay adjustment circuit.

FIG. 3A is a block diagram for explaining conventional delay amount adjustment, and FIG. 3B is a block diagram showing a timing generator and a plurality of variable delay generators.

FIG. 4 is a block diagram showing a specific example of a variable delay generation amount 14;

Claims (1)

(57) [Scope of request for utility model registration] A timing generator is provided for each measurement channel provided for each pin of an IC device under test, and a variable delay generator capable of delaying the output of each timing generator by a set delay amount. Each of the variable delay generators is provided with a path for providing a delay.
And one of the routes that do not give delay according to the setting
In a delay generator for a semiconductor test device in which a plurality of delay stages are connected in cascade , a plurality of the variable delay generators are divided into a plurality of groups.
A delay amount adjustment circuit is provided for each group, and each of these delay amount adjustment circuits belongs to the group.
For each variable delay generator, its input to the variable delay generator
Select and set all possible routes from to the output end
And the amount of delay of the variable delay generator
Measure and select each of these route selection settings and their corresponding measured values
From the set delay required for the variable delay generator.
In contrast, there is a means to determine which route should be set.
A delay generator for a semiconductor test apparatus.