JP2002064370A - Edge detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an edge detecting circuit capable of preventing malfunction caused by chattering. SOLUTION: The state of an edge detection target signal IN is detected by a chattering detecting part 100. On the basis of the output signal of the chattering detecting part 100, a timer 200 is reset when the edge detection target signal IN is at low level, resetting is canceled when the edge detection target signal IN is at high level, and time measuring is performed. Therefore, time, when the edge detection target signal IN becomes at high level, is measured and after time, when the edge detection target signal IN is continuously at high level, exceeds prescribed time, an output signal is made active. When the time, in which the output signal of the timer part 200 becomes in an active state, is continued for a prescribed time further, an edge detecting signal preparing part 300 prepares an edge detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an edge detection circuit which does not cause a malfunction due to chattering when an input signal including chattering, that is, an edge detection target signal is taken into a digital system.

[0002]

2. Description of the Related Art When an incoming input signal asynchronous to a digital system is taken into the digital system, the edge of the input signal is detected and the output signal is often used. However, if there is chattering at the edge of the input signal, the edge detection malfunctions, and as a result, the digital system also malfunctions.

[0003] An asynchronous input signal is, for example, as shown in FIG.
This means that the incoming edge of the input signal IN is at an arbitrary time with respect to the cycle of the clock signal CLK. Since an external input signal and an internal clock (CLK) are often asynchronous, they are described as asynchronous input signals.

FIG. 5 is a circuit diagram showing a configuration of a conventional edge detection circuit. This edge detection circuit is composed of two D flip-flops 1 and 2. The D flip-flop 1 receives the power supply voltage V _CC as a data input D,
The edge detection target signal IN input from 0 is the clock input CK. Also, the D flip-flop 2
The non-inverted output Q of the flip-flop 1 is used as the data input D, and the clock signal CL input from the clock terminal 60 is used.
K is the clock input CK, and the non-inverted output Q is the output terminal 7
0 is output to the outside as an edge detection signal OUT. The non-inverted output Q of the D flip-flop 2 is D
It is provided as a reset input R of the flip-flop 1.

[0005] The operation of the conventional edge detection circuit thus configured will be described with reference to a waveform diagram shown in FIG. FIG. 6 shows a clock signal CL input from a clock terminal 60.
K, the edge detection target signal IN input from the input terminal 50, and the non-inverted output Q of the D flip-flop 1 (signal S
1) and the non-inverted output Q of the D flip-flop 2, that is, the edge detection signal OUT.
In FIG. 6, a number n (n = 1 to 20) shown near each rising edge of the waveform of the clock signal CLK.
Means the time of the n-th pulse of the clock signal CLK, and the time tn (n = 1 to 20) used in the following description
It corresponds to.

Since the rising edge of the edge detection target signal IN arriving from the time t2 to the time t3 is the clock input CK of the D flip-flop 1, the non-inverted output Q of the D flip-flop 1, that is, the signal S1 is low. Transition from level to high level.

Immediately before time t3, D flip-flop 2
Is high, the non-inverted output Q of the D flip-flop 2, that is, the edge detection signal OUT shifts from low to high at the rising edge of the clock signal CLK at time t3. I do. At this time, the non-inverted output Q of the D flip-flop 2
Is applied as a reset input R to the D flip-flop 1, so that the non-inverted output Q of the D flip-flop 1, that is, the signal S1, returns from the high level to the low level.

Next, at the rising edge of the clock signal CLK at time t4, the non-inverted output Q of the D flip-flop 2 also returns from the high level to the low level.

Therefore, it is possible to detect the rising edge of the edge detection target signal IN and obtain an edge detection signal OUT having a pulse width of one cycle of the clock signal CLK.

This edge detection signal OUT is used in a digital system as a signal corresponding to the edge of the edge detection target signal IN.

[0011]

However, in the conventional edge detection circuit, if there is chattering at the edge of the edge detection target signal IN, a malfunction occurs in the edge detection, and as a result, the digital system also malfunctions. There was a problem.

As shown in FIG. 6, from time t11 to time t11
12, the rising edge of the edge detection target signal IN arrives, and after time t13, the edge detection target signal IN
Returns to the low level, and the chattering that the rising edge arrives again from the time t14 to the time t15 is included, and at each rising edge of the edge detection target signal IN, between the time t2 and the time t3. Edge detection is performed in the same manner as the rising edge of the incoming edge detection target signal IN, and the edge detection signal OUT is output.

If the edge detection signal OUT is used in a digital system, the system may malfunction. For example, in a system in which the frequency of the edge detection target signal IN is measured by counting the edge detection signal OUT, the count is increased more than originally, and the accurate frequency of the edge detection target signal IN cannot be captured. .

Accordingly, an object of the present invention is to provide an edge detection circuit which can prevent a malfunction due to chattering.

[0015]

An edge detection circuit according to a first aspect of the present invention includes a chattering detection section, a timer section, and an edge detection signal generation section.

The chattering detection section has a function of detecting the state of the edge detection target signal.

The timer section is reset based on the output signal of the chattering detection section when the edge detection target signal is in an inactive state, and is reset when the edge detection target signal is in an active state and performs time measurement. Has a function of measuring the time during which the edge detection target signal is in the active state, and setting the output signal to the active state after the time during which the edge detection target signal is continuously in the active state exceeds a predetermined time. .

The edge detection signal generation section has a function of generating an edge detection signal when the time during which the output signal of the timer section is in the active state exceeds a predetermined time.

According to the above arrangement, the time when the edge detection target signal is in the active state is measured, and when the time exceeds a predetermined time, the output signal of the timer section is set to the active state, and the timer section is activated. Since the edge detection signal is generated when the time during which the output signal is in the active state exceeds a predetermined time, the edge detection signal is generated after chattering stops. As a result, even when chattering is included in the edge detection target signal, there is an effect that edge detection is performed accurately, and there is an advantage that the system does not malfunction even when used in a digital system.

According to a second aspect of the present invention, in the edge detecting circuit of the first aspect, the chattering detecting section and the edge detecting signal creating section are configured as follows.

The above-mentioned chattering detection section inputs a first D flip-flop using a power supply voltage as a data input and an edge detection target signal as a clock input, and inputs an edge detection target signal and a non-inverted output of the first D flip-flop. 2
The output of the two-input NAND circuit is an output of the chattering detection unit.

The edge detection signal generating section comprises a second D flip-flop using the output signal of the timer section as a data input and a clock signal as a clock input, and outputs the non-inverted output of the second D flip-flop to the first D flip-flop. The signal is supplied to the flip-flop as a reset input, and the non-inverted output of the second D flip-flop is used as the output of the edge detection signal generation unit.

According to this configuration, if the time during which the output signal of the timer section is in the active state continues for a predetermined time (until a clock signal is generated), the edge detection signal is generated in response to the clock signal generated at that time. Will occur. Other operations are the same as those of the first aspect.

According to a third aspect of the present invention, in the edge detecting circuit of the second aspect, the timer unit is configured as follows.

The timer section is composed of a plurality of stages of D flip-flops each having an inverted output and a data input connected to each other and each having the output of the two-input NAND circuit as a reset input, and a clock signal of the first stage D flip-flop. A clock input, inverted outputs of the D flip-flops of the first and subsequent stages are used as clock inputs of the next D flip-flop, and a non-inverted output of the last D flip-flop is used as an output signal of the timer unit.

According to this configuration, the same operation as the second aspect is provided.

An edge detection circuit according to a fourth aspect of the present invention includes a chattering detection section, a timer section, and an edge detection signal generation section.

The chattering detector has a function of detecting the state of the edge detection target signal.

The timer section is reset based on the output signal of the chattering detection section when the edge detection target signal is in an inactive state, and is reset when the edge detection target signal is in an active state and performs time measurement. Has a function of measuring the time during which the edge detection target signal is in the active state, and setting the output signal to the active state after the time during which the edge detection target signal is continuously in the active state exceeds a predetermined time. .

The edge detection signal generation section has a function of generating an edge detection signal when the output signal of the timer section becomes active.

According to the above arrangement, the time during which the edge detection target signal is in the active state is measured, and when the time exceeds a predetermined time, the output signal of the timer section is set to the active state, and the timer section is activated. Since the edge detection signal is generated when the output signal becomes active, the edge detection signal is generated after the chattering stops. As a result, even when chattering is included in the edge detection target signal, there is an effect that edge detection is performed accurately, and there is an advantage that the system does not malfunction even when used in a digital system.

According to a fifth aspect of the present invention, in the edge detecting circuit of the fourth aspect, the chattering detecting section and the edge detecting signal creating section are configured as follows.

The above-mentioned chattering detection section inputs a first D flip-flop using a power supply voltage as a data input and an edge detection target signal as a clock input, and inputs an edge detection target signal and a non-inverted output of the first D flip-flop. 2
The output of the two-input NAND circuit is an output of the chattering detection unit.

The edge detection signal generating section includes a second D flip-flop having a power supply voltage as a data input and an output signal of a timer section as a clock input, and a non-inverted output of the second D flip-flop as a data input and a clock signal. And a third D flip-flop having a clock input of
Is supplied as a reset input to the first and second D flip-flops,
Is the output of the edge detection signal generation unit.

According to this configuration, the edge detection signal is generated immediately after the output signal of the timer section becomes active. Other operations are the same as those of the fourth aspect.

According to a sixth aspect of the present invention, in the edge detection circuit of the fifth aspect, the timer section is configured as follows.

The timer section is composed of a plurality of stages of D flip-flops each of which has an inverted output and a data input connected to each other and has the reset input of the output of the two-input NAND circuit. A clock input, inverted outputs of the D flip-flops of the first and subsequent stages are used as clock inputs of the next D flip-flop, and a non-inverted output of the last D flip-flop is used as an output signal of the timer unit.

According to this configuration, the same operation as that of the fifth aspect is obtained.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a circuit diagram showing a configuration of an edge detection circuit according to a first embodiment of the present invention. The edge detection circuit includes a chattering detection unit 100, a timer unit 200, and an edge detection signal generation unit 30.
0.

The chattering detection section 100 has a function of detecting the state of the edge detection target signal IN.

The timer unit 200 includes the chattering detection unit 1
The reset is released when the edge detection target signal IN is in an inactive state (for example, low level) based on the output signal of 00 and the reset is released when the edge detection target signal IN is in an active state (for example, high level). By measuring the time, the time during which the edge detection target signal IN is in the active state is measured, and after the time during which the edge detection target signal IN is continuously in the active state exceeds a predetermined time, the output signal is output. It has a function to activate.

The edge detection signal generating section 300 generates the edge detection signal OUT when the time during which the output signal of the timer section 200 is in the active state exceeds a predetermined time.

Here, each configuration of the chattering detecting section 100, the timer section 200, and the edge detection signal creating section 300 will be specifically described.

The above-mentioned chattering detection unit 100 comprises a first D flip-flop 1 having a power supply voltage V _CC as a data input D and an edge detection target signal IN inputted from an input terminal 50 as a clock input CK, Signal IN
And a two-input NAND circuit 40 that receives the non-inverted output Q of the first D flip-flop 1 as an input. The output of the two-input NAND circuit 40 is the output of the chattering detection unit 100.

The edge detection signal generator 300 receives the output signal of the timer 200 as a data input D,
0 from a clock signal C
And a non-inverted output Q of the second D flip-flop 2 is supplied to the first D flip-flop 1 as a reset input R.
The non-inverted output Q of the flip-flop 2 is used as an output of the edge detection signal generation unit 300 and supplied to the output terminal 70.

The timer unit 200 connects the inverted output / Q (/ means inverted) to the data input D, and sets the output of the two-input NAND circuit 40 to the reset input R at a plurality of stages (2 D flip-flop 1)
0, 20, and 30, the clock signal CLK is used as the clock input CK of the D flip-flop 10 of the first stage, and the inverted output / Q of each of the D flip-flops 10 and 20 of the subsequent stages is used as the D flip-flop 20 of the next stage. , 30 and the non-inverted output Q of the final stage D flip-flop 30 is used as the output signal of the timer unit 200.
The timer unit 200 functions as a counter for counting the number of clock signals CLK.

The operation of the edge detection circuit according to the first embodiment of the present invention configured as described above will be described with reference to the waveform diagram of FIG.

In FIG. 2, only the D flip-flop 10 and the D flip-flop 20 are used as counters constituting the timer unit 200 in the circuit diagram of FIG.

FIG. 2 shows a clock signal CLK input from the clock terminal 60, an edge detection target signal IN input from the input terminal 50, and a non-inverted output Q of the D flip-flop 1 (signal S1). ), The output signal of the two-input NAND circuit 40 (denoted as a signal S40), and the non-inverted output Q of the D flip-flops 10 and 20.
(Denoted as signals S10 and S20, respectively) and D
3 shows a non-inverted output Q of the flip-flop 2, that is, an edge detection signal OUT. In FIG. 2, numerals n (n = 1 to 20) shown near each rising edge of the waveform of the clock signal CLK indicate n of the clock signal CLK.
It means the time of the th pulse and corresponds to the time tn (n = 1 to 20) used in the following description.

First, the operation when there is no chattering will be described.

Between the time t2 and the time t3, the edge detection target signal I
When the rising edge of N arrives, the non-inverted output Q (signal S1) of the D flip-flop 1 shifts from a low level to a high level, and the output of the two-input NAND circuit 40 shifts from a high level to a low level. Then, the reset of the D flip-flops 10 and 20 of the timer unit 200 is released.

Thereafter, at time t3, the D flip-flop 10
Is output from the D flip-flop 20 at time t4.
Changes from the low level to the high level.

Next, at time t4, the output of the timer unit 200, that is, the non-inverted output Q of the D flip-flop 20 is at a high level. When the output Q changes from low level to high level, the D flip-flop 1 of the chattering detection unit 100 is reset, and the timer unit 20 is output via the two-input NAND circuit 40.
0 is also reset.

At time t5, the output of the timer unit 200, that is, the non-inverted output Q of the D flip-flop 20 is at a low level.
The non-inverted output Q of the D flip-flop 2 of 00 returns from the high level to the low level.

As described above, during the period from time t5 to time t6, the edge detection signal OUT is at the high level and is output from the output terminal 70. That is, the edge detection signal OUT is generated in response to the clock signal CLK generated after the timer unit 200 generates the output signal.

Next, the operation when chattering is present will be described.

When the rising edge, which is the chattering edge of the edge detection target signal IN, arrives between times t11 and t12, the non-inverted output Q of the D flip-flop 1 (signal S)
1) changes from low level to high level and 2
The output of the input NAND circuit 40 shifts from a high level to a low level. Then, the reset of the D flip-flops 10 and 20 of the timer unit 200 is released.

Thereafter, at time t12, D flip-flop 1
The non-inverted output Q of 0 shifts from the low level to the high level at time t13.

However, since the low-level signal arrives at the edge detection target signal IN after the time t13, the output of the two-input NAND circuit 40 returns from the low level to the high level, and the non-inverted output Q of the D flip-flop 20 is output. Returns from the high level to the low level.

When the edge detection target signal IN rises again between the time t14 and the time t15, the output of the two-input NAND circuit gate 40 shifts from the high level to the low level again, and the D flip-flop 10 and the D flip-flop The reset of the loop 20 is released again.

Thereafter, at time t15 and time t16, the non-inverted output Q of each of the D flip-flops 10 and 20 shifts from a low level to a high level.

Next, at time t16, the output of the timer unit 200, that is, the non-inverted output Q of the D flip-flop 20 is at a high level. The output Q changes from low level to high level, the D flip-flop 1 of the chattering detection unit 100 is reset, and the timer unit 200 is also reset via the two-input NAND circuit 40.

At time t17, the output of the timer unit 200, that is, the non-inverted output Q of the D flip-flop 20 is at a low level, so that at time t18, the non-inverted output Q of the D flip-flop 2 of the edge detection signal generating unit 300 becomes It will return from high level to low level.

As described above, during the period from time t17 to time t18, the edge detection signal OUT is at the high level and is output from the output terminal 70. That is, the edge detection signal OUT is generated in response to the clock signal CLK generated after the timer unit 200 generates the output signal.

As described above, the edge detection signal OUT in the edge detection circuit according to the first embodiment of the present invention.
Is delayed by the time set by the timer unit 200, but this delay does not pose a problem for the digital system. This is because, when the signal IN inputted asynchronously is taken into the digital system by the clock signal CLK, once it is taken in, all are synchronized.

In this embodiment, the timer unit 2
When the time when the output signal 00 is in the active state continues for a predetermined time (until the clock signal CLK is generated), an edge detection signal is generated in response to the clock signal CLK generated at that time.

According to the edge detection circuit of this embodiment, the time during which the edge detection target signal IN is in the active state is measured, and when the time exceeds a predetermined time, the output signal of the timer unit 200 is output. Active state,
Since the edge detection signal OUT is generated when the time during which the output signal of the timer unit 200 is in the active state further exceeds a predetermined time, the edge detection signal is generated after the chattering stops. As a result, even when chattering is included in the edge detection target signal IN, edge detection is accurately performed, and there is an advantage that the system does not malfunction even when used in a digital system.

[Second Embodiment] FIG. 3 is a circuit diagram showing a configuration of an edge detection circuit according to a second embodiment of the present invention. In this edge detection circuit, the chattering detection section 100 and the timer section 200 are the same as those in the embodiment of FIG. 1, and only the edge detection signal creation section 310 is different.

That is, the edge detection signal creating section 31
0 generates the edge detection signal OUT when the output signal of the timer unit 200 is activated.

More specifically, a second D flip-flop 2A having the power supply voltage V _CC as the data input D and the output signal of the timer section 200 as the clock input CK,
A third D flip-flop 3A having a non-inverting output Q of the flip-flop 2A as a data input D and a clock signal CLK as a clock input CK, and a non-inverting output Q of the third D flip-flop 3A 2 to the D flip-flops 1 and 2A as a reset input R,
The non-inverted output Q of the second D flip-flop 2A is used as the output of the edge detection signal creation unit 310.

Since the output triggered by the output of the timer unit 200 becomes the edge detection output signal OUT, the D flip-flop 2A outputs the edge detection signal immediately after the timer unit 200 generates the output signal. Occurs, and is output one cycle of the clock signal CLK earlier than the edge detection signal OUT in the embodiment of FIG.

At the next clock signal CLK, the D flip-flop 1 of the chattering detecting section 100 including the flip-flop 2A is output by the output signal of the flip-flop 3A.
Are reset, and the operation is the same as that of the embodiment of FIG.

FIG. 4 shows a waveform diagram of each part of the edge detection circuit of FIG. FIG. 4 shows a clock signal CLK input from the clock terminal 60, an edge detection target signal IN input from the input terminal 50, and a non-inverted output Q (denoted as a signal S1) of the D flip-flop 1. Output signal of the two-input NAND circuit 40 (denoted as signal S40)
, Non-inverted outputs Q of D flip-flops 10 and 20 (denoted as signals S10 and S20, respectively), non-inverted output Q of D flip-flop 2A, that is, edge detection signal OUT, and non-inverted output of D flip-flop 3A. The output Q is shown. In FIG. 4, a number n shown near each rising edge of the waveform of the clock signal CLK.
(N = 1 to 20) means the time of the n-th pulse of the clock signal CLK, and the time tn used in the following description.
(N = 1 to 20).

According to this embodiment, the time during which the edge detection target signal is in the active state is measured, and when the time exceeds a predetermined time, the output signal of the timer section is set to the active state, and the timer section is activated. Since the edge detection signal is generated when the output signal becomes active, the edge detection signal is generated after the chattering stops. As a result, even when chattering is included in the edge detection target signal, edge detection is accurately performed, and there is an advantage that the system does not malfunction even when used in a digital system. In the case of the edge detection circuit of this embodiment, since the edge detection signal OUT is output one clock earlier than in the first embodiment, the set time of the timer circuit 200 is shortened by one clock.

[0076]

As described above, according to the edge detection circuit of the present invention, stable edge detection can be performed even for an edge detection target signal including chattering by appropriately setting the set time in the timer section. It is possible to obtain an edge detection signal that can avoid a malfunction of the digital system.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an edge detection circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart of each part of the edge detection circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of an edge detection circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform chart of each part of the edge detection circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of a conventional edge detection circuit.

FIG. 6 is a waveform chart of each part of the edge detection circuit of FIG. 5;

[Explanation of symbols]

 1, 2, 2A, 3A D flip-flop 10, 20, 30 D flip-flop 40 2-input NAND circuit 50 input terminal 60 clock terminal 70 output terminal 100 chattering detection unit 200 timer unit 300, 310 edge detection signal generation unit

Claims (6)

[Claims] 1. A chattering detection unit for detecting a state of an edge detection target signal, wherein the edge detection target signal is reset when the edge detection target signal is in an inactive state based on an output signal of the chattering detection unit, and the edge detection target signal is reset. The reset is released when is
A timer unit that measures the time during which the edge detection target signal is in the active state, and sets the output signal to the active state after the time during which the edge detection target signal is continuously in the active state exceeds a predetermined time. An edge detection signal generation unit that generates an edge detection signal when a time during which the output signal of the timer unit is in an active state exceeds a predetermined time. 2. A first D flip-flop which receives a power supply voltage as a data input and an edge detection target signal as a clock input, and a non-inverted output of the edge detection target signal and the first D flip-flop. , And an output of the chattering detection unit, an output of the timer detection unit is used as a data input, and a clock is output. A second D flip-flop which receives a signal as a clock input, and supplies a non-inverted output of the second D flip-flop as a reset input to the first D flip-flop; 2. The edge detection circuit according to claim 1, wherein the inverted output is an output of the edge detection signal generation unit. 3. The timer section comprises a plurality of stages of D flip-flops each connecting an inverted output and a data input and using the output of a two-input NAND circuit as a reset input. Clock input, the inverted output of the D flip-flop of each stage after the first stage as the clock input of the D flip-flop of the next stage, and the non-inverted output of the D flip-flop of the last stage as the output signal of the timer unit. The edge detection circuit according to claim 2. 4. A chattering detection unit for detecting a state of an edge detection target signal, wherein the edge detection target signal is reset when the edge detection target signal is in an inactive state based on an output signal of the chattering detection unit, and the edge detection target signal is reset. The reset is released when is
A timer unit that measures the time during which the edge detection target signal is in the active state, and sets the output signal to the active state after the time during which the edge detection target signal is continuously in the active state exceeds a predetermined time. An edge detection signal generation unit that generates an edge detection signal when an output signal of the timer unit is activated. 5. A chattering detecting section, comprising: a first D flip-flop having a power supply voltage as a data input and an edge detection target signal as a clock input; and a non-inverting output of the edge detection target signal and the first D flip-flop. , And an output of the chattering detection section, an output of the timer detection section, a power supply voltage as a data input, and an output of the timer section. A second D flip-flop having a signal as a clock input, and a third D flip-flop having a non-inverted output of the second D flip-flop as a data input and a clock signal as a clock input;
Supplying the non-inverted output of the D flip-flop as a reset input to the first and second D flip-flops,
5. The edge detection circuit according to claim 4, wherein a non-inverted output of said second D flip-flop is used as an output of said edge detection signal generation section. 6. The timer section includes a plurality of stages of D flip-flops each connecting an inverted output and a data input, and using the output of a two-input NAND circuit as a reset input. Clock input, the inverted output of the D flip-flop of each stage after the first stage as the clock input of the D flip-flop of the next stage, and the non-inverted output of the D flip-flop of the last stage as the output signal of the timer unit. The edge detection circuit according to claim 5.