JPS6121681Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hardware control circuit suitable for use in conjunction with a microprocessor.

In particular, the present invention relates to a circuit for capturing state information of a controlled device and providing it to the microprocessor when automatic control is performed using a microprocessor.

In various controlled devices, their status signals can be given by the number of pulses sent out in a given period of time. This type of information includes not only mechanical rotation information but also quantities measured in electrical systems such as clocks that are gated with pulse time width signals. When such a controlled device is controlled by a microprocessor, if the status signal is directly input to the microprocessor, the processing load on the processor increases. This causes problems such as complicated software and increased control delay time.

An object of the present invention is to provide a simple hardware control circuit that takes in a status signal in the form of a pulse signal, compares it with a given set value, and outputs the comparison result as a simple bit signal.

This control circuit is used as the state signal output of the controlled device,
By using it between the input of a microprocessor, the burden on the microprocessor is reduced and speed is increased, and a servo system or feedback system can be easily constructed.

The present invention includes a gate circuit that controls the passage time of an input pulse signal arriving from a controlled system, a counter that counts the pulses that have passed through this gate circuit,
two registers that respectively accumulate values corresponding to the upper and lower limit values of the set value, and two full adder circuits that receive the contents of these registers and the contents of the counter as inputs and output carry signals; A logic circuit that receives the carry signal of this full adder circuit as an input, and the logic circuit has a signal indicating that the upper limit value has been exceeded, a signal indicating that the upper limit value is lower than the lower limit value, and a signal indicating that the lower limit value is lower than the lower limit value. The configuration is characterized in that the three signals are connected to the input of a microprocessor that controls the controlled system.

This will be explained in more detail in the drawings below.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, reference numeral 1 denotes an input conversion circuit, which is a circuit for converting an input state signal A from a controlled device into a clock frequency modulation signal. If this input state signal A can be used directly as the output A' of this circuit 1, this circuit 1 is not necessary. This output A' is given to the counter 3 via the gate circuit 2.
Input signal B is a gate control signal, and input signal C is a reset signal for counter 3.

On the other hand, in FIG. 1, 5 and 6 are registers, the contents of which are given to full adder circuits 7 and 8, respectively. The contents of the counter 3 are given to the other inputs of the full adder circuits 7 and 8. The contents of the counter 3 are given to the other inputs of the full adder circuits 7 and 8.
The carry signals of the most significant digits of the full adder circuits 7 and 8 are transmitted to an OR circuit 11 and a NOR circuit 12, respectively.
is given as an input. Circuits 5' and 6' coupled to this OR circuit 11 and NOR circuit 12 are as follows:
These are 1-bit registers for carry of registers 5 and 6, respectively. The output of this OR circuit 11 becomes an output signal D via an inversion circuit 13, and the output of the NOR circuit 12 becomes an output signal F via an inversion circuit 14.
The output of the AND circuit 15 which receives the outputs of the OR circuit 11 and the NOR circuit 12 is the output signal E.
becomes.

In the device configured in this manner, the "two's complement" of the lower limit value S _L of the control setting value is given to the register 5, and the "one's complement" of the upper limit value S _U is given to the register 6.

The input status signal from the controlled device is converted to a clock pulse frequency A' and is input to the counter 3 from the gate 2 for a fixed period of time. This counter 3
and the contents of the register 5 or 6 are subjected to full addition by a full adder circuit 7 or 8. When these carry signals are respectively calculated in circuits 11 to 15, the following signals are obtained at their outputs D, E, and F, respectively. In other words, if X is the number of pulses taken into the counter 3 with respect to the lower limit value S _L and upper limit value S _U of the set values, then when X<S _L , DEF=100 where S _L ≦X≦S _U When DEF=010 When X>S _U , DEF=001. In this way, this circuit converts into a simple bit signal whether the input status signal is below the lower limit of the set value, between the lower limit and the upper limit, or above the upper limit and sends it out. .

FIG. 2 is a diagram showing an example of the usage state of the circuit according to the present invention. Reference numeral 20 denotes a circuit according to an embodiment of the present invention, which corresponds to the circuit shown in FIG. 1 above. 21 is a microprocessor, and 22 is a controlled device. Shown in Figure 2
ABCDEF corresponds to the symbols shown in FIG. 1, respectively. G is a signal that mainly changes the contents of the set values of registers 5 and 6. H indicates the control that the microprocessor executes on the controlled device.

In such a configuration, the processor 21 first sends the signal C to the control circuit 20 to clear the contents of the counter, and then receives the input state signal A for a certain period of time using the gate signal B. Next, the above-mentioned arithmetic processing is performed and the output DEF is sent out, which causes the microprocessor 21 to send the signal H to the controlled device 22.
control. If necessary, the set value is changed using signal G. This series of operations is repeated as long as necessary.

As described above, by using the control circuit of the present invention, the burden on the microprocessor is significantly reduced, control speed is increased, control accuracy is improved, and status signals that were previously unavailable can be used. You will be able to do this. Furthermore, since the microprocessor has more leeway, the scope of its application is expanded, such as making it possible to perform controls that were previously impossible. In particular, the use of this circuit has a great effect in that a microprocessor can be easily introduced into a servo system.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a usage form of the circuit of the present invention. 1... Conversion circuit, 2... Gate circuit, 3... Counter, 5, 6... Register, 5', 6'... Most significant bit of register, 7, 8... Full adder circuit, 2
0...Circuit of the present invention, 21...Microprocessor, 22...Controlled device.

Claims (1)

[Scope of Claim for Utility Model Registration] A gate circuit that controls the passage time of an input pulse signal coming from a controlled system, a counter that counts the pulses that have passed through this gate circuit, and corresponds to the upper and lower limit values of the set value. 2 registers that each store the values to be input, and 2 that outputs a carry signal by inputting the contents of these registers and the contents of the counter above, respectively.
It is equipped with a full adder circuit and a logic circuit that receives the carry signal of this full adder circuit as input, and the logic circuit has a signal indicating that the upper limit has been exceeded, and a signal indicating that the upper limit is less than or equal to the lower limit. 1. A control circuit configured to output a signal and a signal indicating that the lower limit value has been exceeded, the three signals being connected to inputs of a microprocessor that controls the controlled system.