SU809159A1 - Decoder - Google Patents

Description

(54) DEFINER

one

The invention relates to computing and can be used in the nodes and control devices of computers and digital automation.

A command decoder is known that contains the shift register, the AND elements, the OR elements, the input register, the parcel reception logic blocks, the time relay, the execution signal generator 1.

The disadvantage of this decoder is the complexity of the design.

The closest in technical essence is a decoder containing a n-bit input register, 2 output NAND and gating bus connected to the first inputs of output NAND, and the single and zero outputs of the input register are connected to the corresponding output of the output elements and NOT through the element OR and and 2.

The disadvantage of this decoder is the complexity of the design and relatively low speed.

The purpose of the invention is to simplify the design and increase speed.

The goal is achieved by the fact that the decoder contains a n-bit input register, 2 output elements of the NAND, and the device strobe area is connected to one of the n + 1 inputs of each

i-ro (i 1,2, ..., 2) of the output element AND - NOT, it contains a pulse shaper, the output of which is connected to the first inputs of each of the n bits of the input register, and the input to the device strobe bar, the other i-oro inputs of the output element

AND-NOT (1 i 2) are connected to m (m 1,2, ..., p-1) single and zero outputs of the bits of the input () -ro binary number, respectively, of single and zero values, the inputs of the first output element AND- NOT connected to the zero outputs of each of the n bits of the input register, the second inputs of each of the n bits of the input register are connected to the corresponding input of the decoder. FIG. 1 shows a block diagram of a decipher, for example, two-bit; on

FIG. 2 - time diagram of his work.

Descriptor contains the input register

on triggers P output elements

Claims (2)

AND-NOT shaper 3 pulses; bus 4 gating; input code bus output bus 6-b, which are connected to the outputs of the output elements AND NOT. The gating bus is connected to the first inputs of the NAND output elements, and the single and zero outputs of the input register are connected to the corresponding NAND output elements. The input of the driver 3 is connected to the gate bus, and the output is connected to the input register overwrites. The decoder works as follows. In the initial state, the triggers of the input register are in the zero state, on the combinational inputs of the output element AND-NOT 2 there are resolving potentials. When a gating pulse with a duration tc (Fig. 2a) arrives on the bus 4, the NE-2 element appears; the potential of the zero level is the inverse value of the gate-pulse with a delay τ equal to the delay of one valve, i.e. NOT (Fig. 2, c). At the same time, the strobe pulse is fed to the input of the imaging unit 3, which from the leading edge of the strobe pulse generates with a delay t, a pulse of the duration which is necessary for reliable triggering of the input register (Fig. 2.6). The output pulse of the imaging unit 3 rewrites the information in the input register. After the rewriting is completed, a second gate-pulse arrives at the input of the pulse driver 3 (Fig. 2, a). A device is easier known both by the number of elements included in it and by the number of connections. In addition, the number of inputs of the output elements AND-NOT in the known decoder is n + 2, where n is the number of bits of the input register. In the decoder the number of inputs of the output elements AND-NOT is n + 1, which also simplifies the design. The strobe period T is the decryption cycle time. The maximum speed of the decoder is achieved at tc 1slviei. However, in this case, the time of the decryption cycle is T tc + t, and the time of the decryption cycle of the known decoder is T te -f- 21 :. Due to the fact that Less 2T, the maximum speed of the decoder is greater than that of the known. Claims of the Invention A decoder containing an n-bit input register, 2 output elements AND-NOT, the device gating bus being connected to one of the n + 1 inputs of each i-ro (i 1,2, ..., 2) output element AND -NON, characterized in that, in order to simplify the design and increase speed, it contains a pulse shaper, the output of which is connected to the first inputs of each of the n bits of the input register, and the input to the device strobe bus element AND-NOT (1 i 2) are connected to m (m 1,2, ..., p-1) unit and to the zero outputs of the input bits of the (i-1) -th binary number, respectively, are single and zero values, the inputs of the first output element are NOT connected to the zero outputs of each of the n bits of the input register, the second inputs of each of the bits of the input register are connected to the corresponding decryptor input tires. Sources of information taken into account during the examination 1. USSR author's certificate No. 599262, cl. G 06 F 5/02, 1974. 2. USSR author's certificate number 598066, cl. G 06 F 5/02, 1976. (prototype). T-ta) + t3an "E- but tc Tcp tsan