SU842721A1 - Parameter checking device - Google Patents

Description

(5.4) DEVICE FOR PARAMETER CONTROL

The invention relates to automation and computing and can be used to control the parameters of technical objects in computers and information-measuring devices when solving problems of rapid and reliable information processing. A device containing a block of registers, a group of elements OR, a first group of elements NOT, a first group of elements AND, a second group of elements AND, a start block, a block of fixing a parameter value, a fixing of an address, a bit of AND and OR, and the outputs of the first bits all re- histories directly, and the outputs of the remaining bits of the registers through the first bit elements AND are connected to the inputs of the corresponding elements OR groups, the outputs of which are connected to the inputs of the group of elements NOT and the information inputs of the elements AND of the first group, the control input which is connected to the control input elements of the second group and with the first output of the start-up block, the input of which is connected to the input of the device, the outputs of the elements of the first group are connected to the information inputs of the block of fixation of the parameter value, control l yuschy input coupled to the second output start block and the control input of address latch; informational inputs of which are connected to the outputs of elements AND of the second group, the first output of the group of elements YU directly, and the rest through the second bit elements AND connected to the first inputs of the bit elements OR of all registers, the second inputs of which, except the first discharge of all registers, are connected to the outputs of the corresponding first bit elements AND, the second inputs of the bit elements OR corresponding to the first bit are connected directly to its output, the outputs of the bit elements OR each In addition to the last register, they are connected to the inputs of the first and second bit elements AND subsequent bits, the outputs of the bit elements OR the last bit of all switch lines are connected to the information inputs of the second group of elements AND. The disadvantages of the known device are limited functionality, which consists in not taking into account the results of the analysis, information about the parameters, the values of which are not true, but contain both the component of the value of the parameter itself and the component of interference. A device for searching for extreme parameter values is known, comprising a switch for interrogating a switch to registers consisting of a binary counter of a decoder, a controlled oscillator, a trigger trigger, bit elements AND and OR, registers for writing values of monitored parameters, bit blocks of logic, two-input elements AND, whose inputs are connected to the switch outputs and separate logic blocks, the registration blocks of the extreme value of the parameter and its address, which allows determining the parameter that has its extreme value and its address is L22. The drawback of the device is the limited functionality of the possibilities, which consists in not taking into account the results of the analysis of information on parameters, the value of which contains the component of interference. The closest technical solution to the proposed is a device for controlling parameters, containing a block of registers, an analysis of a group of elements OR, a group of elements. And a generator, delay elements, a switch differentiating circuits in which the output control buses of the analysis nodes are connected to the inputs of an element And, the output of which through nepB5.To differentiating circuit is connected to the input of the installation in one state of the trigger, the direct output of which is connected to the input of the second register, the outputs of which are connected to the input ins switch, the output bus which is connected to the set input of a zero state

the first bit, the output of the first element OR is connected to the input of the installation in the zero state of the first trigger, the output of which is connected

to the second inputs of the elements of the first group, the output of the m.-gb of the OR element, of the group is connected to the first input of the AND element and to the first input of the third OR element, the second input of which

connected to the first installation input of the analysis node, and the output to the installation input into the single state of the first trigger and to the input of the trigger 1 setup, to the second inputs of the And group element and through the second differentiating circuit and the first delay element to the control inputs of the second register, output clock generator - through the second delay element connected to the third inputs of elements AND groups, the output of the element OR connected to the installation inputs of all analysis nodes, the input of the second delay element connected to the second installation and inputs-analysis nodes, and each of the analysis nodes contains m-bit register, groups of elements AND, -OR, triggers, elements AND, OR, NOT, and informational inputs of the analysis node are connected to the first inputs of elements AND of the first group , and the output of the i-ro element AND of the first group is connected to the i-th input of the first element OR, and to the input of the i-ro register bit, where i 1,2, .. ,, m is the output of the j-ro bit reg register, where, 3, ..., m, is connected to the J / th input of the second element OR and. the first input of the j-ro element AND the second group, the second input of which is connected to the output (jl) -ro of the element OR of the group, the output of the j-ro element AND of the second group is connected to the first input of the j-ro element AND of the third group and to the first input j element of the OR group, output. (jl) -ro element OR group is connected to the first input of the j -th element AND of the fourth group, the second input of which is connected to the control input of the -th digit, output of the -th element AND the fourth group: i: connected to the second input of the jth element of the OR group, the output of the first register bit is connected to the first input the second element OR, i with the first input of the first element AND. The third group and with the first input of the first element PfflH of the group, whose second input is connected to the input of the uniforms in the register zero state, the first installation input of the analysis node is connected to the installation input in the single state of the second trigger and all element NO the output of which is connected to the installation input to the zero state of the second trigger, the third input of the element I. is connected to the second ycTk input of the analysis node, the direct output of the second trigger is connected to the second input elements of the second and third groups To the third input of the elements AND the fourth, group, the output of the second element OR is connected to the output bus of the control unit of the analysis unit fs. The disadvantage of the device is the low speed in processing information containing interference. At discrete points in time, the device receives a series of values of the monitored parameter, which varies according to an unknown law, and which are applied to — interference. Thus, a total signal is present at the device input. The device does not solve the problem of fast signal processing, as the operator has to manually localize and exclude those parameter values that contain the interference component. The purpose of the invention is to increase the speed of processing the monitored parameters. The goal is achieved by the fact that the device for controlling parameters contains a block of registers. the first delay element, the first And element connected by the first input to the device input, the second delay element connected by the output to the input of the pulse generator and through the third delay element to the first inlay, ohm of the second And element ,, a switch, descrambler, reversible counter, driver , control unit, unit, subtraction and threshold unit, output of the first element I is connected to the input of the threshold element through a switch connected in series, control unit, reversible counter, first delay element, forming a command inverter, a rewrite unit and a subtraction unit, the second input of the reversible counter is connected to the output of the first element AND, the second output is connected to the second input of the decoder, the third output is connected to the second input of the switch, and the first output is connected to the second input of the second element AND whose output is through the decoder connected to the second input of the register unit, the output of the pulse generator is connected to the third input of the reversible counter, the output of the threshold element with the second input of the command generator, the first output of the control unit is connected to the input of the second It’s the second output to the second input of the first element I. In addition, the census block contains multiplexers, the first inputs of which are connected to the outputs of the first register-. The ditch, the second inputs to the second input of the block, and the outputs to the output of the block, the outputs of the first multiplexers are connected to the first inputs of the first registers, the second inputs of which are connected to the first input of the block, and the second register output connected to the third input of the second multiplexer. FIG. 1 shows a block diagram of the device; in fig. 2 block diagram of the rewriting of the values of monitored parameters. The device contains the first element And 1, switch 2, control unit 3, reversible counter 4, first, second and third delay elements 5,6 and 7, second element 8, pulse generator 9, decoder 10, command generator 11, rewriting unit 12 , subtracting unit 13, threshold unit 14, first registers 15, first multiplexers 16, second register. 17, the second multiplexer 18.. The device works as follows. . In the initial state, the switch 2 and the reversible counter 4 are located in the. zero states The signal from the first output of the control unit 3, which is connected to the first input of the reversible counter 4, sets the reversible counter 4 to the tracking mode and, through delay elements 6 and 7, is applied to the first input of the IZ element, closes it. At the second output of the control unit there is a potential of a logical unit, which is applied to the second input of the element I 1, prepares it for operation. At the first output of the reversible counter 4, there is no signal and, as a consequence, there is no signal to the output unit 11. At

  84 of the control output of the detector 10, there is no signal, since the AND element 8, with which it is connected, is closed. The first entry of information into the device is made by the operator, therefore this information is considered reliable. He also enters in control unit 3 and threshold value block 14: the number of controlled values of parameter N and the value of threshold 6 (not shown in Fig. 1 and Fig. 2, the information recording and input circuits are shown. The device starts from the moment of switching the device input. Pulses present the information at the device input goes to the first input of the element I 1 and from the output it goes to the input of the switch 2 to the second input of the reversing counter 4; When the switch calculates N pulses, the potential of the logical zero is established at the second output of the control unit 3 which is closed at the second input of the element AND 1 closes it.The pulses of information on the device’s course cease to arrive at the input of the switch 2, Simultaneously with the appearance of a zero potential at the second output of block 3, a signal appears at its first output volume ,, that N parameter values are recorded in rewriting unit 12. This signal, applied to the first input of the reversible counter 4, causes it to switch to the subtraction mode AND through delay element 6 starts generator 9, and through element 7 Delay prepares the element And 8 to trigger. The first pulse from the generator 9, which is applied to the third input of the reversible counter 4, the reversible counter 4 transmits (Nl) —oe state, and a signal appears at the first output indicating that the reversing counter 4 has passed into (Nl) -e condition. This signal opens the second element AND 8 and through the first delay element 5 arrives at the first input of the command generator 11 commands. By opening, the IZ element by its output signal allows reading information from the first output of the reversing counter 4 to the second input of the decoder 10. The decoder 10 decryptor (Nl) The-o state of the reversing counter 4 generates from its output a signal which is applied to the second input of the block 12

eight

rewriting, the operation of the multiplexers 16 is eliminated and, as a result of this, the readout to its control output — the 1st and 2nd values of the parameter C of the control output of the rewriting unit 12; the 1st and 2nd values of the parameter are fed to the input of the subtractor 13 , the output of which forms the absolute value of the difference between the 1st and 2nd values of the parameter, which is fed to the input of the threshold unit 14. If the difference obtained with the difference is greater than the threshold g, then the output of the threshold unit 14 is a signal that is applied to the second input of driver 11 to The command causes the appearance of a signal at its output, which affects the first input of rewrite unit 12 and goes to the first input of the first register 15 of the record, which causes the contents of the 2nd register 15 to be rewritten into the 1st register) 15 records.

Thus, the erroneous 2nd parameter value is replaced with a valid 1st value; If the difference obtained from the threshold is less than or equal to it, then there will be no signal at the output of the threshold block 14 and, as a result, there will be no rewriting. All the above processes in the device flow during one cycle of the generator 9, the Nth pulse from generator 9 reversible setter 4 goes to the zero state and at the third output a pulse appears that is applied to the installation input to the zero state of switch 2 switches switch 2 to the zero state and thus the device returns to the initial state.

The technical advantages of the proposed device are in extending the functionality of the known device, i.e. speeding up when processing controlled parameters, the gain. Which can be estimated by the following factor

N-t ,, Tp N (t3 + tT-)

Claims (3)

where N is the number of values of the monitored parameter; TQ - manual processing time; t is the recording time of one parameter value; fc-f is the period of the following clock pulses. So with the values of N 100-, t 10 sec} Tp 1 sec-, t, the value of the coefficient Kg- is equal to) i.e., the speed increases by ten notches. Claim 1. Device for controlling parameters containing block of registers first delay element, first element I, connected by the first input to the device input, second set element, connected by the output to the input of the pulse generator and through the third delay element with the first input Second element AND, characterized in that, in order to improve the speed of the device, a switchboard, a desifrater, a reversible counter, a command driver, a control unit, a subtraction unit and a threshold unit, the output of the first AND element are entered into it oedinen to the input of the threshold elements in series through the one switch, the control unit, ny reversion counter, the first delay element driver commands and overwriting unit subtractor and an output SW1. The first AND element is connected to the second input of the reversible counter, connected to the first element And the second output with the second input of the decoder, the third output with the second input of the switch, and the first output with the second input of the second element And whose output through the decoder is connected to the second input of the register unit, the output of the pulse generator is connected to the third input of the reversible counter, the output of the threshold element to the second input of the command generator, the first output of the control unit is connected to the input of the second element and the second output - to the second input. The first element is And 2. The device according to claim 1, is only because the census block contains multiplexers, the first inputs of which are connected to the outputs of the first registers, the second inputs are about the second the input of the block and the outputs to the output of the block, the outputs of the first multiplexers are connected to the first inputs of the first registers, the second inputs of which are connected to the first input of the block, and the second register output is connected to the third input of the second multiplexer. Sources of information taken into account in the examination 1. The copyright certificate. USSR № 525083, cl. Gj 06 F 7/00, 1976. 2. USSR author's certificate number 534762, cl. Q 06 F 7/00, 1977. 3. USSR author's certificate according to the application 2587969 / 18-24, cl. G 06 G: 15/36, 1978 (prototype).