SU875610A1 - Pulse signal discriminator - Google Patents

Description

(54) SELECTOR OF IMGOLARY SIGNALS The invention relates to a pulse technique, in particular to pulse selectors, and can be used to extract pulses of a given duration from a sequence of pulses of various durations. A device is known that contains a standby multivibrator, shapers of the leading edge of the reference and input pulses, and an output element. And a disadvantage of the known device is low selection accuracy. The closest to the technical essence of the invention is a pulse signal selector containing a pulse counter, the outputs of the counters that are connected to the corresponding inputs of the decoder, the master oscillator, the output of which is connected to the first input of the first element, And the second input of which is connected to the direct the output of the trigger input, a single input of which is connected to the output of a front edge generator of the input pulses, the input of which is connected to the input of the ghost front edge of the input pulses and to the input bus, the delay element, the second AND gate and the element t23 prohibition. The disadvantage of this device is the presence of a time error due to the non-synchronism of the input pulses with the pulses of the master oscillator, which reduces the accuracy of the selection. In addition, in this device, the duration of the output pulses is determined. total delay time of the signal in the pulse counter and in the decoder, and this is not enough for reliable operation of subsequent devices. The purpose of the invention is to increase the accuracy of selection and restore the duration of the selected pulses. The goal is achieved by the fact that in the pulse signal selector switch, containing a pulse counter, the output bits of which are connected to the corresponding inputs of the decoder, the master oscillator, the output of which is connected to the first input of the first element I, the second input connected to the forward output of the trigger trigger, is single the input of which is connected to the output of the front-edge driver and the input of the pulses, the input of which is connected to the entrance of the rear-edge driver of the input pulses and with the input bus, a delay element, the second element AND and the prohibition element, the third and fourth elements AND, the OR element, four AND-NOT elements, four kS-flip-flops and the decoder of the initial state of the pulse counter are entered, the first input of the first AND-NOT element is connected to the output of the giving generator and with the input of the delay element, the first output of which is connected to the first input of the second element NAND and to the first input of the second element AND, and the second output to the first input of the third element NAND and to the first input of the third element AND, the second input of which connect to the second inputs the first and second elements are And, the third inputs of which are connected to the first outputs of the first and second RS-flip-flops, respectively, the single input of the first of which is connected to the Vicode of the first AND-NAND element and to the zero input of the third RS-flip-flop, and the zero input to the output the second element AND-NOT and with a single input of the second RS-flip-flop, the zero input of which is connected to the output of the third AND-NOT element and to the single input of the third RS-flip-flop, the direct output of which is connected to the third input of the third And element, the output of which is connected to first entrance element OR, the second and third inputs of which are connected respectively to the outputs of the second and first elements AND, and you move - to the summing input of the impulse counter, the subtractive input of which is connected to the output of the fourth element I, the first input of which is connected to the first input of the first And, the second input - with the direct output of the fourth RS-flip-flop, the reset input - to the output of the fourth NAND element, the first input of which is connected to the output of the inhibit element and the single input of the fourth RS-flip-flop, Fourth way out In addition, the RS flip-flop and the third input - with the second inputs of the first, second and third elements AND-NOT and with the inverse output of the input trigger, the zero input of which is connected to the output of the trailing edge of the input pulses and the first input of the prohibition element, and the clock the input to the second input of the prohibition element and to the output of the decoder, and the outputs of the counter bits of the pulse counter are connected via the decoder of the initial state of the pulse counter with the zero input of the fourth RS flip-flop. diagram of the device; Fig. 2 shows voltage plots illustrating the formation of output impulses. The device contains a pulse counter 1, a decoder 2, a master generator 3, the first element AND 4, an input trigger 5, shapers b and 7, respectively, the front and rear edges of the input pulses, delay element 8, the second element And 9, the element of the ban 10, the third and fourth elements And 11 and 12, the element OR 13, the first, second, third and fourth elements AND-NOT 14-17, the first, second, third and fourth RS triggers 18 -21 and the decoder 22 of the initial state of the pulse counter, the bus 23 is The input bus is the device, and the direct output of the RS flip-flop 21 is the device output 24. The first inputs of the elements AND 4 and 12 are connected to the first input of the element AND-NOT 14 and. With the output of the generator 3. The first input of the element and 9 is connected to the first input of the element AND-NOT 15 and to the first output of the delay element 8, and the first input of the AND element 11 is connected to the first input element of the NAND 16 and to the second output of the delay element 8. The second inputs of the element of the NAND 14-16 are connected to the inverse output of the trigger 5, a single input of which is connected to the output of the imager 6. The inputs of the formers 6 and 7 are connected between themselves and with the input bus 23 devices. The zero input of the trigger 5 is connected to the first input of the prohibition element 10 and with the output of the imaging unit 7, and its clock input is connected to the second input of the prohibition element 10 and to the output of the decoder 2. The single and zero inputs of the RS flip-flops are respectively 18 and 20 connected to each other and the output of the element is NOT-14, and the zero and single inputs of the RS flip-flops, respectively, 18 and 19 are connected to each other and to the output of the element AND-NOT 15. The zero and single inputs of the RS flip-flops, respectively, 19 and 20 are connected to each other and to the output of the And- element NOT 16, but direct output output trigger 5 connected to the second inputs of the And 4, 9 and 11 elements, the third inputs of which are connected to the direct outputs of the RS flip-flops, respectively 18-20. The outputs of the elements 4, 9 and 11 are connected to the inputs of the element OR 13, the output of which is connected to the summing input of the counter 1, the outputs of the conversion bits of which are connected to the corresponding inputs of the decoder 2 and the decoder 22. The direct output RS of the trigger 21 is connected to the second input of the element AND 12, the output of which is connected to the subtracting input of counter 1. The output of the decoder 22 is connected to the zero input of the RS flip-flop 21, the single input and the inverse output of which are connected respectively to the first and second inputs of the element AND NOT 17, the output of which is connected to the reset input of the counter 1, and the third input to the inverse output of the trigger 5. The input of the delay element 8 is connected to the output of the generator-3, and the output of the prohibition element 10 is connected to the single input of the RS flip-flop 21.

The device triggers, when a low potential is applied to a single (zero) input, go to a single zero state, i.e. on their direct output a high (low) voltage level is established.

The difference from low potential to high at the clock input of the trigger input 5 translates it into the state opposite to that which it had occupied before the occurrence of the given - differential.

If the prohibition element 10 has a low voltage at the first input, and a high voltage at its second input, a low voltage level is maintained at its output. In all other cases, the output of the prohibition element 10 is maintained at a high voltage level.

The device works as follows.

In the initial position, the trigger 5 and the RS flip-flop 21 are in the zero state. The low voltage level from the direct output of the trigger 5 goes to the second inputs of the AND 4, 9 and 11 elements, thereby blocking the possibility of pulses coming from the output of the generator 3 or from the outputs of the delay element 8 to the summing input of the counter 1. The element 12 is blocked by the second the input is low voltage supplied from the direct output of the RS flip-flop 21, which prevents pulses from the output of the generator 3 to read the input of the counter 1. The sequence of clock pulses from the output of the generator 3 (fig.2a) is fed to the input of the element 3 The supports 8, where the pulses are converted into sequences (Fig. 26, c) taken from the first and second outputs respectively. Since the elements AND-NOT 14-16 are open through the second inputs by a high voltage level coming from the inverse output of the trigger 5, then as they arrive at their first inputs of the clock pulses, respectively, from the output of the generator 3, the first and second outputs of the delay element 8, they Output4 negative pulses are formed (respectively Fig. 2d, d, e). RS-flip-flops 18-20 are alternately pulses coming from the outputs of the elements AND-NOT, respectively, 14-16 are set to one state (fig.2h, h, and).

During the passage of the input pulse (Fig. 2k), the driver 6 triggers on the leading edge of this pulse and generates a short negative pulse (Fig. 2L), by which the trigger 5 is transferred to a single state (Fig. 2m). At the same time, the elements AND-NO 14-16 are closed at the second inputs LOW. the voltage level coming from the inverted output of the trigger 5, and the elements 4, 9 and 11 are opened - on the second inputs a high voltage level coming from the direct output of the trigger 5.

Now the RS-flip-flops 18-20 cease to operate and remain in the position in which they were at the moment of arrival of the input pulse, i.e. An optimal clock sequence is connected to counter 1 (in this case, the sequence shown in Fig. 2c). Since the element And 11 is now open on the second and third inputs, the pulses from the second output of the delay element 8 through it and through the element OR 13 (fig.2n)

5 to the summing input of counter 1, where the duration of the input ig pulses is converted into a digital code.

When the input pulse duration is equal to that specified at the output of the de0 encoder 2, a high voltage level appears (Fig. 2o), the moment of the occurrence of which coincides with the pulse generated by the driver 7 (Fig. 2n). in this case, trigger 5

5 returns to the zero state, and the output of the inhibit element 10 sets a low voltage level (Fig. 2p), by which the RS flip-flop 21 translates to a single state (Fig. 2c). A high level of voltage from the direct output of the RS flip-flop 21 is fed to the second input of the element 12, thereby allowing the passage of clock pulses from. the output of the generator 3 to the subtracting input of the counter

5 1 (fig.2t). After reading the code recorded in the counter 1 during the action of the input pulse, a low voltage level appears at the output of the decoder 22 (Fig. 2y),

0 whereby the RS flip-flop 21 returns to the zero state, i.e. the formation of the output pulse.,:

When a pulse arrives at the device input, the duration of which is shorter than the specified one, trigger 5 will be set to the zero state earlier than the necessary code will be written in counter 1, i.e. In this case, the RS flip-flop 21 cannot in any way be set to a single state, since the NAND element 17 is opened through the second and first inputs by a high voltage level, respectively, coming from the inverse output of the RS flip-flop 21 and the output of the prohibition element 10, then after the return of the trigger 5 to the initial state on the trailing edge of the input pulse, it will also open at the third input. This will cause a low voltage output at its output, jcoTopHM counter 1 will return to its initial state.

When a pulse arrives at the device input, the duration of which is longer than the specified one, RS-flip-flop 21 cannot be set to one state, since the moment of appearance of the pulse at the output of the decoder 2 does not coincide with the output pulse of the shaper 7. In this case the output of the decoder 2 enters the clock input of the trigger 5, and the latter is transferred to the zero state, thereby blocking (the passing of the clock pulses to the summing input of counter 1. After the trigger returns to the zero state, the counter 1, to to the previous case, returned to nachoshnoe state.

The introduction of the elements AND-NOT 14-16, RS-flip-flops 18-20, the element 11 and the element OR 13 makes it possible to compensate for the time error caused by the asynchronism of the input pulses with the pulses of the generator 3.

The introduction of the RS flip-flop 21, the AND 12 element, the AND-HE 17 element and the decoder 22 allows restoring the duration of the selectable pulses.

Claims (2)

1.Ichkhoki Ya.s. Pulse devices. M., Soviet Radio, 1959, with. 648. 2. USSR author's certificate 540365, cl. H 03 K 5/18, 1975.