SU598066A1 - Decoder - Google Patents

Description

(54) ENCODER

which are connected to the outputs of the output elements, AND-NOT.

In the initial state, depending on the code of the input register 1 - 1, on the combinational inputs of one of the EID 4 and 4 4 there are resolving guitenziati. When a gating pulse is received, a zero level impulse is generated at the output of the corresponding AND-NO 4-4 pulse, which blocks other output elements AND-NOT for the duration of the strobe action. The impulse from the output element AND-Hfe is also fed to the input of the additional postnigle element. AND-NOT 6, on which the embedded and zero-level momentum occurs. On the basis of the pulse generated on the element of InE 5, the code is overwritten in the input register of the decoder. In addition, a single impulse formed at the output of the AND-NOT 5 element is fed to the second inputs of the OR element 3, and the output is hoped to form the output pulse on the bus 8 at the time of rewriting the information in the input register I - 1.

The proposed decoder allows you to combine time gating and rewriting information in the input register, which increases its speed, in addition, it reduces the number of control buses.

From the timeline {see FIG. 2) it follows that in the proposed decoder, the time of the decoding cycle is T t tp +2 T, where the duration of the gating pulse p is the delay of one ventilp. Decryption cycle time in TaTs devices, where the write time in the input register.

When using J) triggers in the input register T, V1Т J therefore the performance gain is more than 21.

Claims (1)

1. USSR author's certificate NI 410386, class H 03 K 13/258, 1972. 2, USSR Author's Certificate No. 4344О5, cells: G О F 5 / О2. 1972.