JPS54127248A - Arithmetic controller - Google Patents

Arithmetic controller

Info

Publication number
JPS54127248A
JPS54127248A JP3424978A JP3424978A JPS54127248A JP S54127248 A JPS54127248 A JP S54127248A JP 3424978 A JP3424978 A JP 3424978A JP 3424978 A JP3424978 A JP 3424978A JP S54127248 A JPS54127248 A JP S54127248A
Authority
JP
Japan
Prior art keywords
signal line
counter
pulse
address
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3424978A
Other languages
Japanese (ja)
Inventor
Kiyoshi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3424978A priority Critical patent/JPS54127248A/en
Publication of JPS54127248A publication Critical patent/JPS54127248A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To obtain a high-efficiency arithmetic controller which is effective especially in debugging a program with a loop.
CONSTITUTION: By way of address bus 216 and data bus 217, CPU209 attains access to memory unit 218. Coincidence circuit 219 compares an address on bus 216 with that set to switch 220. When the both agree each other, coincidence output 221 becomes high in level and down counter 222 is made to count down by one pulse. To this counter 222, the number of repetitions of a needed loop is preset by switch 223. With load switch 224 depressed, a positive pulse is generated on signal line 226 and a load pulse is applied to counter 222 via gate 227 and signal line 228. On receiving the address coincidence pulse onto the signal line, counter 222 counts down and when the count value becomes zero, signal line 229 is made low in level. Vibrator 230, on the other hand, generates a negative pulse onto signal line 231 to clear FF203 and closes gate 206 to stop clock 208, thereby stopping the CPU.
COPYRIGHT: (C)1979,JPO&Japio
JP3424978A 1978-03-27 1978-03-27 Arithmetic controller Pending JPS54127248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3424978A JPS54127248A (en) 1978-03-27 1978-03-27 Arithmetic controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3424978A JPS54127248A (en) 1978-03-27 1978-03-27 Arithmetic controller

Publications (1)

Publication Number Publication Date
JPS54127248A true JPS54127248A (en) 1979-10-03

Family

ID=12408885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3424978A Pending JPS54127248A (en) 1978-03-27 1978-03-27 Arithmetic controller

Country Status (1)

Country Link
JP (1) JPS54127248A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106552A (en) * 1985-11-01 1987-05-18 Fujitsu Ltd Loop detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62106552A (en) * 1985-11-01 1987-05-18 Fujitsu Ltd Loop detector

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