JPS5682926A - Hang detecting circuit - Google Patents

Hang detecting circuit

Info

Publication number
JPS5682926A
JPS5682926A JP16105279A JP16105279A JPS5682926A JP S5682926 A JPS5682926 A JP S5682926A JP 16105279 A JP16105279 A JP 16105279A JP 16105279 A JP16105279 A JP 16105279A JP S5682926 A JPS5682926 A JP S5682926A
Authority
JP
Japan
Prior art keywords
counter
latch
reset
state
channel processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16105279A
Other languages
Japanese (ja)
Inventor
Shigeru Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16105279A priority Critical patent/JPS5682926A/en
Publication of JPS5682926A publication Critical patent/JPS5682926A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To reduce the structure of hardware greatly by detecting the hang state of a function block from the progress state of a counter by an information processor consisting of plural function blocks.
CONSTITUTION: When an input-output start instruction is transferred to a channel processor, set-reset latch 1 is set to set latch 20, whose output places counter 24 in a count-enable-state. Counter 24 counts up with every clock. When channel processor CHP0 transfers a complete signal to a main memory controller a certain time later, latch 1 is reset. Consequently, AND gate 29 outputs "1" and counter 24 and latch 20 are reset. On the other hand, when no complete signal is transferred from the channel processor, counter 24 counts up to a maximum count value and then generates a carry signal, so that the hang state will be recognized.
COPYRIGHT: (C)1981,JPO&Japio
JP16105279A 1979-12-12 1979-12-12 Hang detecting circuit Pending JPS5682926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16105279A JPS5682926A (en) 1979-12-12 1979-12-12 Hang detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16105279A JPS5682926A (en) 1979-12-12 1979-12-12 Hang detecting circuit

Publications (1)

Publication Number Publication Date
JPS5682926A true JPS5682926A (en) 1981-07-07

Family

ID=15727686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16105279A Pending JPS5682926A (en) 1979-12-12 1979-12-12 Hang detecting circuit

Country Status (1)

Country Link
JP (1) JPS5682926A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10691519B2 (en) 2016-09-15 2020-06-23 International Business Machines Corporation Hang detection and recovery

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10691519B2 (en) 2016-09-15 2020-06-23 International Business Machines Corporation Hang detection and recovery

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