JPS54120379A - Timer device of sequence controller - Google Patents

Timer device of sequence controller

Info

Publication number
JPS54120379A
JPS54120379A JP2802878A JP2802878A JPS54120379A JP S54120379 A JPS54120379 A JP S54120379A JP 2802878 A JP2802878 A JP 2802878A JP 2802878 A JP2802878 A JP 2802878A JP S54120379 A JPS54120379 A JP S54120379A
Authority
JP
Japan
Prior art keywords
timer
cpu
signal
module
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2802878A
Other languages
Japanese (ja)
Inventor
Hiroshi Kitano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Komatsu Ltd
Original Assignee
Komatsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Ltd filed Critical Komatsu Ltd
Priority to JP2802878A priority Critical patent/JPS54120379A/en
Publication of JPS54120379A publication Critical patent/JPS54120379A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the points of a timer in one module sharply, by means of constituting a plurality of timers by using one time counter.
CONSTITUTION: A timer module 10 generates a CPU stop requiring signal every time count period, and when the CPU may receive this, a status signal indicating that it becomes to a timer mode, is sent. When a CPU block 20 receives this signal, it causes the operation of the CPU block to be whether stopped or the CPU block to be floated from a data bus 40. The timer module 10 has a memory which has a plurality of memorized positions those memorize a set value and a present value of the timer, and has a memory circuit which memorizes flags, and it counts down the present value of the memory circuit in which flags are set, every time count period by one, and when this value becomes to 0, a time up signal is generated.
COPYRIGHT: (C)1979,JPO&Japio
JP2802878A 1978-03-10 1978-03-10 Timer device of sequence controller Pending JPS54120379A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2802878A JPS54120379A (en) 1978-03-10 1978-03-10 Timer device of sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2802878A JPS54120379A (en) 1978-03-10 1978-03-10 Timer device of sequence controller

Publications (1)

Publication Number Publication Date
JPS54120379A true JPS54120379A (en) 1979-09-18

Family

ID=12237282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2802878A Pending JPS54120379A (en) 1978-03-10 1978-03-10 Timer device of sequence controller

Country Status (1)

Country Link
JP (1) JPS54120379A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5890404U (en) * 1981-12-07 1983-06-18 株式会社明電舎 Timer/counter circuit
JPS6174103U (en) * 1984-10-17 1986-05-20

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5890404U (en) * 1981-12-07 1983-06-18 株式会社明電舎 Timer/counter circuit
JPS6174103U (en) * 1984-10-17 1986-05-20

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