JPS56135223A - Interruption device - Google Patents
Interruption deviceInfo
- Publication number
- JPS56135223A JPS56135223A JP3797580A JP3797580A JPS56135223A JP S56135223 A JPS56135223 A JP S56135223A JP 3797580 A JP3797580 A JP 3797580A JP 3797580 A JP3797580 A JP 3797580A JP S56135223 A JPS56135223 A JP S56135223A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- input
- output device
- selector
- names
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To improve the efficiency of utilization of an input-output device by holding plural processor names in one input-output device, by selectively outputting processor names in predetermined order, and by allowing another processor to be used when an in-use processor does not open. CONSTITUTION:Holding selector 1 is provided which holds plural processor namesin an input-output device and then outputs selectively those processor names in predetermined order. Further, access to the input-output device from the processor on bus 10 that corresponds to a name selected by selector 1 is monitored; if the access is not attained for a certain time or longer, time-out signal 101 is outputted from timer circuit 2 and then the processor that corresponds to the selected name is interrupted by interrupting circuit 3. If the interruption of circuit 3 does not end in a certain time, timer circuit 4 applies time-out signal 103 to controller 5, which resets selector 1 to select another processor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3797580A JPS56135223A (en) | 1980-03-25 | 1980-03-25 | Interruption device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3797580A JPS56135223A (en) | 1980-03-25 | 1980-03-25 | Interruption device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56135223A true JPS56135223A (en) | 1981-10-22 |
JPS6235149B2 JPS6235149B2 (en) | 1987-07-30 |
Family
ID=12512562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3797580A Granted JPS56135223A (en) | 1980-03-25 | 1980-03-25 | Interruption device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56135223A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0260757U (en) * | 1988-10-27 | 1990-05-07 |
-
1980
- 1980-03-25 JP JP3797580A patent/JPS56135223A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6235149B2 (en) | 1987-07-30 |
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