JPS54104260A - Analog input system - Google Patents

Analog input system

Info

Publication number
JPS54104260A
JPS54104260A JP1058578A JP1058578A JPS54104260A JP S54104260 A JPS54104260 A JP S54104260A JP 1058578 A JP1058578 A JP 1058578A JP 1058578 A JP1058578 A JP 1058578A JP S54104260 A JPS54104260 A JP S54104260A
Authority
JP
Japan
Prior art keywords
converter
data
process signal
input
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1058578A
Other languages
Japanese (ja)
Inventor
Kuniyoshi Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1058578A priority Critical patent/JPS54104260A/en
Publication of JPS54104260A publication Critical patent/JPS54104260A/en
Pending legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To make it possible to collect data at a high speed paying attention to that when a process signal is in a stationary state, and its variation is a little.
CONSTITUTION: Computer CPU executes an input instruction by considering a process signal to be at an actuation time. On receiving the address of an input point, control part 505 controls multiplexer 501, sample holding circuit 502 holds the data of the point, and A/D converter 503 A/D-converts and sends out them to the CPU. When the process signal becomes stationary, the CPU sets data forecasted at the stationary time into random access memory 504. At every time when A/D converter 503 operates, control part 505 reads out data forecasted from an address in memory 504 equivalent to the input point and presets them to A/D converter 503, thereby comparing the difference with the input signal in sequence.
COPYRIGHT: (C)1979,JPO&Japio
JP1058578A 1978-02-03 1978-02-03 Analog input system Pending JPS54104260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1058578A JPS54104260A (en) 1978-02-03 1978-02-03 Analog input system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1058578A JPS54104260A (en) 1978-02-03 1978-02-03 Analog input system

Publications (1)

Publication Number Publication Date
JPS54104260A true JPS54104260A (en) 1979-08-16

Family

ID=11754313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1058578A Pending JPS54104260A (en) 1978-02-03 1978-02-03 Analog input system

Country Status (1)

Country Link
JP (1) JPS54104260A (en)

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